The goal of this commit is to remove 'implict val p: XSConfig' in our code becasue it's inconvenient

Use fake Icache to fetch 8 instructions per cycle.

* microbench test fails even L2 is disabled

TODO:
* Injecting interrupts in decode stage with NOP.
* Save mstatus.mie to mstatus.mpie

* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
  SimpleBusUH