This commit adds fpStateReadOut and fpStateReadIn ports to Scheduler to
support reading fp reg states from other schedulers.

It should have better timing because now ExuBlock(0) has only int
regfile and busytable. This block does not need fp writeback any more.

* Fix a div 1 bug
* Fix a typo

* bump difftest
* alu: fix max and maxu result
* alu: fix src1 generated by opcode
Co-authored-by: Zhangfw <471348957@qq.com>

This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is also removed from CtrlBlock.

Now the module organization becomes:
* ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs
* ExuBlock_1: Fp RS, Fp RF, Fp FUs
* MemBlock: Load/Store FUs

Besides, load queue has 80 entries and store queue has 64 entries now.

This commit fixes a bug that causes pc to be wrong values when a jump is
blocked for issue and a new jump instruction enters reservation station.
When the jump for issue is blocked, we should latch its pc value because
the entry has been deallocated from rs (and pc no longer exists in the
pc mem).

* change ROB to 256 entries
* change physical register file to 192 entries
* re-organize reservation stations, function units and regfile

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

This commit adds storage for PC in JUMP reservation station. Jalr needs
four operands now, including rs1, pc, jalr_target and imm. Since Jump
currently stores two operands and imm, we have to allocate extra space
to store the one more extra operand for jalr.

It should be optimized later (possibly by reading jalr_target when
issuing the instruction).

This commit also adds regression check for PC usages. PC should not
enter decode stage.

This commit applys Definition and Instance for some modules. Refer to
https://github.com/chipsalliance/chisel3/pull/2045.

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH, PACKW to ALU

* Add fused logicZexth, addwZext, addwSexth

* Add instruction fusion test cases to CI

* Bmu: support zbk* instructions

* ci: add zbk* instruction test

* New SRT4 divider that may improve timing

See "Digital reurrence dividers with reduced logical depth"

* SRT16 Int Divider that is working properly

* Fix bug related to div 1

* Timing improved version of SRT16 int divider

* Add copyright and made some minor changes

* Fix bugs related to div 0

* Fix another div 0 bug

* Fix another special case bug

instead of chisel var in MEFreeList.scala

This commit adds performance counters for function units that have
feedback to reservation stations, including FMA, Load and Store.
We add performance counters to show how many instructions are issued for
multiple times.

This commit splits FMA instructions into FMUL and FADD for execution.

When the first two operands are ready, an FMA instruction can be issued
and the intermediate result will be written back to RS after two cycles.
Since RS currently has DataArray to store the operands, we reuse it to
store the intermediate FMUL result.

When an FMA enters deq stage and leaves RS with only two operands, we
mark it as midState ready at this clock cycle T0.

If the instruction's third operand becomes ready at T0, it can be
selected at T1 and issued at T2, when FMUL is also finished. The
intermediate result will be sent to FADD instead of writing back to RS.
If the instruction's third operand becomes ready later, we have the data
in DataArray or at DataArray's write port. Thus, it's ok to set midState
ready at clock cycle T0.

The separation of FMA instructions will increase issue pressure since RS
needs to issue more times. However, it larges reduce FMA latency if many
FMA instructions are waiting for the third operand.

This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBlock, but it cannot work
if the function units have feedbacks to RS. In this commit it is
removed.

This commit adds a victim index option for oldestFirst. For LOAD, the
first issue port has better performance and thus we set the victim index
to 0. For other function units, we use the last issue port.

1) generate ptr and preg in a vec first
2) use renameEnable to replace common parts in allocating logic

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

1) bug fix: updateArchRefCounter should be related with pdest, not
old_pdest
2) remove complicated logic of headPtr recovery when flushing

This commit adds manual reset for every register in Regfile. Previously
the reset is done by add reset values to the registers. However,
physically general-purpose register file does not have reset values.

Since all the regfile always has the same writeback data, we don't need
to explicitly assign reset data.

This commit adds critical_wakeup_*_* counters to indicate which function
units wake up the instructions in RS. Previously we have wait_for_src_*
counters but they cannot represent where the critical operand (the last
waiting operand) comes from.

We need these counters to optimize fast wakeup logic. If some
instructions critically depend on some other instructions, we can think
of how we can optimize the wakeup process.

Furthermore, this commit also adds a specific counter for FMAs that
wakeup other FMAs' third operand. This helps us to decide which strategy
is used for FMA fast issue.

nothing changed but add one parameter to control if ldtlb and sttlb are the same
now there two similar parameters:

outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same'
refillBothTlb: when this is true, the four tlb are same(require outReplace to be true)

* mmu.tlb: add param refillBothTlb to refill both ld & st tlb

* mmu.tlb: set param refillBothTlb to false

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, instructions with exceptions will enter ROB when they are
dispatched. Thus, actually we don't need the exception vector when an
instruction enters a function unit.

* exceptionVec, flushPipe, replayInst are reset when an instruction
enters function units.

* For execution units that don't have exceptions, we reset their output
exception vectors to avoid ROB to record them.

* Move replayInst to CtrlSignals.

This commit moves issue select logic in reservation stations to stage 0
from stage 1. It helps timing of stage 1, which load-to-load requires.

Now, reservation stations have the following stages:

* S0: enqueue and wakeup, select. Selection results are RegNext-ed.
* S1: data/uop read and data bypass. Bypassed results are RegNext-ed.
* S2: issue instructions to function units.

This commit adds 3-bit shift fused instructions. When the program
tries to add 8-byte index, these may be used.

List of fused instructions added in this commit:

* szewl3: `slli r1, r0, 32` + `srli r1, r0, 29`

* sr29add: `srli r1, r0, 29` + `add r1, r1, r2`

This commit simplifies status logic in reservations stations. Module
StatusArray is mostly rewritten.

The following optimizations are applied:

* Wakeup now has higher priority than enqueue. This reduces the length
of the critical path of ALU back-to-back wakeup.

* Don't compare fpWen/rfWen if the reservation station does not have
float/int operands.

* Ignore status.valid or redirect for srcState update. For data capture,
these are necessary and not changed.

* Remove blocked and scheduled conditions in issue logic when the
reservation station does not have loadWait bit and feedback.

This commit changes how uop and data are read in reservation stations.
It helps the issue timing.

Previously, we access payload array and data array after we decide the
instructions that we want to issue. This method makes issue selection
and array access serialized and brings critial path.

In this commit, we add one more read port to payload array and data
array. This extra read port is for the oldest instruction. We decide
whether to issue the oldest instruction and read uop/data
simultaneously. This change reduces the critical path to each selection
logic + read + Mux (previously it's selection + arbitration + read).

Variable oldestOverride indicates whether we choose the oldest ready
instruction instead of the normal selection. An oldestFirst option is
added to RSParams to parameterize whether we need the age logic. By
default, it is set to true unless the RS is for ALU. If the timing for
aged ALU rs meets, we will enable it later.

This commit adds some simple instruction fusion cases in decode stage.
Currently we only implement instruction pairs that can be fused into
RV64GCB instructions.

Instruction fusions are detected in the decode stage by FusionDecoder.
The decoder checks every two instructions and marks the first
instruction fused if they can be fused into one instruction. The second
instruction is removed by setting the valid field to false.

Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc.

Currently, ftq in frontend needs every instruction to commit. However,
the second instruction is removed from the pipeline and will not commit.
To solve this issue, we temporarily add more bits to isFused to indicate
the offset diff of the two fused instruction. There are four
possibilities now. This feature may be removed later.

This commit also adds more instruction fusion cases that need changes
in both the decode stage and the funtion units. In this commit, we add
some opcode to the function units and fuse the new instruction pairs
into these new internal uops.

The list of opcodes we add in this commit is shown below:
- szewl1: `slli r1, r0, 32` + `srli r1, r0, 31`
- szewl2: `slli r1, r0, 32` + `srli r1, r0, 30`
- byte2: `srli r1, r0, 8` + `andi r1, r1, 255`
- sh4add: `slli r1, r0, 4` + `add r1, r1, r2`
- sr30add: `srli r1, r0, 30` + `add r1, r1, r2`
- sr31add: `srli r1, r0, 31` + `add r1, r1, r2`
- sr32add: `srli r1, r0, 32` + `add r1, r1, r2`
- oddadd: `andi r1, r0, 1`` + `add r1, r1, r2`
- oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2`
- orh48: mask off the first 16 bits and or with another operand
         (`andi r1, r0, -256`` + `or r1, r1, r2`)

Furthermore, this commit adds some complex instruction fusion cases to
the decode stage and function units. The complex instruction fusion cases
are detected after the instructions are decoded into uop and their
CtrlSignals are used for instruction fusion detection.

We add the following complex instruction fusion cases:
- addwbyte: addw and mask it with 0xff (extract the first byte)
- addwbit: addw and mask it with 0x1 (extract the first bit)
- logiclsb: logic operation and mask it with 0x1 (extract the first bit)
- mulw7: andi 127 and mulw instructions.
        Input to mul is AND with 0x7f if mulw7 bit is set to true.

* Alu: fix andn, orn, xnor

* Decode: change instruction name

This commit assigns exu.io.out.fflags to RegNext(fu.io.fflags) if the
function unit has fastUopOut but has not implemented it. Previously
it causes a bug that fflags may be one cycle earlier than expected.

This commit also removes the extra logic in FmacExeUnit and
FmiscExeUnit. They are exactly the same as ExeUnit now.

* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly raised after sfence.vma

* backend, roq: [bug fix] won't label me with exception as writebacked

This commit adds support for load balance between different issue ports
when the function unit is not pipelined and the reservation station has
more than one issue ports.

We use a ping pong bit to decide which port to issue the instruction. At
every clock cycle, the bit is flipped.

This commit adds assertion in MaskData to check the width of mask
and data. When the width of mask is smaller than the width of data,
(~mask & data) and (mask & data) will always clear the upper bits
of the data. This usually causes unexpected behavior.

This commit adds explicit width declarations where MaskData is used.

* FMA: spearate fadd/fmul/fma

* exu: enable fast uop out from fmacExeUnit
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>