mmu.tlb: ptw resp will refill both ld & st tlb (#1029)

nothing changed but add one parameter to control if ldtlb and sttlb are the same
now there two similar parameters:

outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same'
refillBothTlb: when this is true, the four tlb are same(require outReplace to be true)

* mmu.tlb: add param refillBothTlb to refill both ld & st tlb

* mmu.tlb: set param refillBothTlb to false

src/main/scala/xiangshan/Parameters.scala

@@ -173,6 +173,7 @@ case class XSCoreParameters
     normalAsVictim = true,
     outReplace = true
   ),
+  refillBothTlb: Boolean = false,
   btlbParameters: TLBParameters = TLBParameters(
     name = "btlb",
     normalNSets = 1,
@@ -327,6 +328,7 @@ trait HasXSParameter {
   val EnableFastForward = coreParams.EnableFastForward
   val RefillSize = coreParams.RefillSize
   val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
+  val refillBothTlb = coreParams.refillBothTlb
   val useBTlb = coreParams.useBTlb
   val itlbParams = coreParams.itlbParameters
   val ldtlbParams = coreParams.ldtlbParameters

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -139,23 +139,37 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   dtlb_st.map(_.sfence := sfence)
   dtlb_ld.map(_.csr := tlbcsr)
   dtlb_st.map(_.csr := tlbcsr)
-  if (ldtlbParams.outReplace) {
-    val replace_ld = Module(new TlbReplace(exuParameters.LduCnt, ldtlbParams))
-    replace_ld.io.apply_sep(dtlb_ld.map(_.replace), io.ptw.resp.bits.data.entry.tag)
-  }
-  if (sttlbParams.outReplace) {
-    val replace_st = Module(new TlbReplace(exuParameters.StuCnt, sttlbParams))
-    replace_st.io.apply_sep(dtlb_st.map(_.replace), io.ptw.resp.bits.data.entry.tag)
+  if (refillBothTlb) {
+    require(ldtlbParams.outReplace == sttlbParams.outReplace)
+    require(ldtlbParams.outReplace)
+
+    val replace = Module(new TlbReplace(exuParameters.LduCnt + exuParameters.StuCnt, ldtlbParams))
+    replace.io.apply_sep(dtlb_ld.map(_.replace) ++ dtlb_st.map(_.replace), io.ptw.resp.bits.data.entry.tag)
+  } else {
+    if (ldtlbParams.outReplace) {
+      val replace_ld = Module(new TlbReplace(exuParameters.LduCnt, ldtlbParams))
+      replace_ld.io.apply_sep(dtlb_ld.map(_.replace), io.ptw.resp.bits.data.entry.tag)
+    }
+    if (sttlbParams.outReplace) {
+      val replace_st = Module(new TlbReplace(exuParameters.StuCnt, sttlbParams))
+      replace_st.io.apply_sep(dtlb_st.map(_.replace), io.ptw.resp.bits.data.entry.tag)
+    }
   }
 
+
   if (!useBTlb) {
     (dtlb_ld.map(_.ptw.req) ++ dtlb_st.map(_.ptw.req)).zipWithIndex.map{ case (tlb, i) =>
       tlb(0) <> io.ptw.req(i)
     }
     dtlb_ld.map(_.ptw.resp.bits := io.ptw.resp.bits.data)
     dtlb_st.map(_.ptw.resp.bits := io.ptw.resp.bits.data)
-    dtlb_ld.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector.take(exuParameters.LduCnt)).orR)
-    dtlb_st.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector.drop(exuParameters.LduCnt)).orR)
+    if (refillBothTlb) {
+      dtlb_ld.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector).orR)
+      dtlb_st.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector).orR)
+    } else {
+      dtlb_ld.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector.take(exuParameters.LduCnt)).orR)
+      dtlb_st.map(_.ptw.resp.valid := io.ptw.resp.valid && Cat(io.ptw.resp.bits.vector.drop(exuParameters.LduCnt)).orR)
+    }
   } else {
     val btlb = Module(new BridgeTLB(BTLBWidth, btlbParams))
     btlb.suggestName("btlb")