backend,exu: load balance between issue ports (#947)

This commit adds support for load balance between different issue ports
when the function unit is not pipelined and the reservation station has
more than one issue ports.

We use a ping pong bit to decide which port to issue the instruction. At
every clock cycle, the bit is flipped.

src/main/scala/xiangshan/backend/ExuBlock.scala

@@ -93,6 +93,7 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
     }
   }
 
+  // Optimizations for wakeup and writeback timing
   // Timing priority: RegNext(rs.fastUopOut) > fu.writeback > arbiter.out(--> io.rfWriteback --> rs.writeback)
   // Filter condition: allWakeupFromRS > hasExclusiveWbPort > None
   // The higher priority, the better timing.
@@ -168,4 +169,24 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
     }
   }
 
+  // Optimizations for load balance between different issue ports
+  // When a reservation station has at least two issue ports and
+  // the corresponding function unit does not have fixed latency (not pipelined),
+  // we let the function units alternate between each two issue ports.
+  val multiIssueFuConfigs = fuConfigs.filter(_._2 >= 2).filter(_._1.needLoadBalance).map(_._1)
+  val multiIssuePortsIdx = flattenFuConfigs.zipWithIndex.filter(x => multiIssueFuConfigs.contains(x._1))
+  val multiIssue = multiIssueFuConfigs.map(cfg => multiIssuePortsIdx.filter(_._1 == cfg).map(_._2))
+  multiIssue.foreach(ports => {
+    val numPingPong = ports.length / 2
+    for (i <- 0 until numPingPong) {
+      val index = ports.drop(2 * i).take(2)
+      println(s"Enable issue load balance between ports $index")
+      val pingpong = RegInit(false.B)
+      pingpong := !pingpong
+      when (pingpong) {
+        scheduler.io.issue(index(0)) <> fuBlock.io.issue(index(1))
+        scheduler.io.issue(index(1)) <> fuBlock.io.issue(index(0))
+      }
+    }
+  })
 }

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -89,6 +89,7 @@ case class ExuConfig
   val allWakeupFromRS = !hasUncertainlatency && (wbIntPriority <= 1 || wbFpPriority <= 1)
   val wakeupFromExu = !wakeupFromRS
   val hasExclusiveWbPort = (wbIntPriority == 0 && writeIntRf) || (wbFpPriority == 0 && writeFpRf)
+  val needLoadBalance = hasUncertainlatency && !wakeupFromRS
 
   def canAccept(fuType: UInt): Bool = {
     Cat(fuConfigs.map(_.fuType === fuType)).orR()

src/main/scala/xiangshan/package.scala

@@ -594,7 +594,7 @@ package object xiangshan {
   val stdCfg = FuConfig(
     "std",
     fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1,
-    writeIntRf = false, writeFpRf = false, hasRedirect = false, UncertainLatency()
+    writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1)
   )
 
   val mouCfg = FuConfig(