alu, decode: fix alu instruction and change instruction name (#1012)

* Alu: fix andn, orn, xnor

* Decode: change instruction name

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -239,7 +239,7 @@ object XDecode extends DecodeConstants {
     SH2ADDU_W   -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh2add_uw, Y, N, N, N, N, N, N, SelImm.IMM_X),
     SH3ADDU_W   -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh3add_uw, Y, N, N, N, N, N, N, SelImm.IMM_X),
     ADDU_W      -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.add_uw, Y, N, N, N, N, N, N, SelImm.IMM_X),
-    SLLIU_W     -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slli_uw, Y, N, N, N, N, N, N, SelImm.IMM_I),
+    SLLIU_W     -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slli_uw, Y, N, N, N, N, N, N, SelImm.IMM_I)
   )
 }
 

src/main/scala/xiangshan/backend/decode/Instructions.scala

@@ -188,8 +188,8 @@ object Instructions {
   def CLMULHW            = BitPat("b0000101??????????011?????0111011")
   def SHFLW              = BitPat("b0000100??????????001?????0111011")
   def UNSHFLW            = BitPat("b0000100??????????101?????0111011")
-  def BEXTW              = BitPat("b0000100??????????110?????0111011")
-  def BDEPW              = BitPat("b0100100??????????110?????0111011")
+  def BMEXTW              = BitPat("b0000100??????????110?????0111011")
+  def BMDEPW              = BitPat("b0100100??????????110?????0111011")
   def PACKW              = BitPat("b0000100??????????100?????0111011")
   def ZEXT_H             = BitPat("b000010000000?????100?????0111011")
   def PACKUW             = BitPat("b0100100??????????100?????0111011")

src/main/scala/xiangshan/backend/fu/Alu.scala

@@ -237,12 +237,12 @@ class AluDataModule(implicit p: Parameters) extends XSModule {
   val binv = src1 ^ bitShift
   val bext = srl(0)
 
-  val andn    = ~(src1 & src2)
-  val orn     = ~(src1 | src2)
-  val xnor    = ~(src1 ^ src2)
-  val and     = ~andn
-  val or      = ~orn
-  val xor     = ~xnor
+  val andn    = src1 & ~src2
+  val orn     = src1 | ~src2
+  val xnor    = src1 ^ ~src2
+  val and     = src1 & src2
+  val or      = src1 | src2
+  val xor     = src1 ^ src2
   val sgtu    = sub(XLEN)
   val sltu    = !sgtu
   val slt     = xor(XLEN-1) ^ sltu

src/main/scala/xiangshan/backend/fu/Bmu.scala

@@ -19,7 +19,7 @@ class CountModule(implicit p: Parameters) extends XSModule {
   }
   def clzi(msb: Int, left: UInt, right: UInt): UInt = {
     Mux(left(msb),
-      Cat(left(msb) & right(msb), !right(msb), if(msb==1)right(0) else right(msb-1, 0)),
+      Cat(left(msb) && right(msb), !right(msb), if(msb==1)right(0) else right(msb-1, 0)),
       left)
   }