misc: use Definition and Instance for modules (#1067)

This commit applys Definition and Instance for some modules. Refer to
https://github.com/chipsalliance/chisel3/pull/2045.

src/main/scala/xiangshan/backend/FUBlock.scala

@@ -18,6 +18,7 @@ package xiangshan.backend
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
+import chisel3.experimental.hierarchy.Instance
 import chisel3.util._
 import utils._
 import xiangshan._
@@ -116,7 +117,8 @@ class FUBlock(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) extends XS
     val fmaMid = if (numFma > 0) Some(Vec(numFma, new FMAMidResultIO)) else None
   })
 
-  val exeUnits = configs.map(c => Seq.fill(c._2)(ExeUnit(c._1))).reduce(_ ++ _)
+  val exuDefs = configs.map(_._1).map(ExeUnitDef(_))
+  val exeUnits = configs.zip(exuDefs).map(x => Seq.fill(x._1._2)(Instance(x._2))).reduce(_ ++ _)
   println(exeUnits)
   val intExeUnits = exeUnits.filter(_.config.readIntRf)
   // TODO: deal with Std units

src/main/scala/xiangshan/backend/exu/ExeUnit.scala

@@ -19,11 +19,12 @@ package xiangshan.backend.exu
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
+import chisel3.experimental.hierarchy.{Definition, instantiable, public}
 import chisel3.util._
 import utils._
 import xiangshan._
 import xiangshan.backend.Std
-import xiangshan.backend.fu.fpu.{FPUSubModule, FMA}
+import xiangshan.backend.fu.fpu.{FMA, FPUSubModule}
 import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer}
 
 class FenceIO(implicit p: Parameters) extends XSBundle {
@@ -32,7 +33,9 @@ class FenceIO(implicit p: Parameters) extends XSBundle {
   val sbuffer = new FenceToSbuffer
 }
 
-class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config: ExuConfig) {
+@instantiable
+class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) {
+
   val disableSfence = WireInit(false.B)
   val csr_frm = WireInit(frm.getOrElse(0.U(3.W)))
 
@@ -118,16 +121,16 @@ class StdExeUnit(implicit p: Parameters) extends ExeUnit(StdExeUnitCfg)
 class FmacExeUnit(implicit p: Parameters) extends ExeUnit(FmacExeUnitCfg)
 class FmiscExeUnit(implicit p: Parameters) extends ExeUnit(FmiscExeUnitCfg)
 
-object ExeUnit {
-  def apply(cfg: ExuConfig)(implicit p: Parameters): ExeUnit = {
+object ExeUnitDef {
+  def apply(cfg: ExuConfig)(implicit p: Parameters): Definition[ExeUnit] = {
     cfg match {
-      case JumpExeUnitCfg => Module(new JumpExeUnit)
-      case AluExeUnitCfg => Module(new AluExeUnit)
-      case MulDivExeUnitCfg => Module(new MulDivExeUnit)
-      case JumpCSRExeUnitCfg => Module(new JumpCSRExeUnit)
-      case FmacExeUnitCfg => Module(new FmacExeUnit)
-      case FmiscExeUnitCfg => Module(new FmiscExeUnit)
-      case StdExeUnitCfg => Module(new StdExeUnit)
+      case JumpExeUnitCfg => Definition(new JumpExeUnit)
+      case AluExeUnitCfg => Definition(new AluExeUnit)
+      case MulDivExeUnitCfg => Definition(new MulDivExeUnit)
+      case JumpCSRExeUnitCfg => Definition(new JumpCSRExeUnit)
+      case FmacExeUnitCfg => Definition(new FmacExeUnit)
+      case FmiscExeUnitCfg => Definition(new FmiscExeUnit)
+      case StdExeUnitCfg => Definition(new StdExeUnit)
       case _ => {
         println(s"cannot generate exeUnit from $cfg")
         null

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -18,6 +18,7 @@ package xiangshan.backend.exu
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
+import chisel3.experimental.hierarchy.{IsLookupable, instantiable, public}
 import chisel3.util._
 import utils.XSPerfAccumulate
 import xiangshan._
@@ -57,7 +58,7 @@ case class ExuConfig
   fuConfigs: Seq[FuConfig],
   wbIntPriority: Int,
   wbFpPriority: Int
-) {
+) extends IsLookupable {
   def max(in: Seq[Int]): Int = in.reduce((x, y) => if (x > y) x else y)
 
   val intSrcCnt = max(fuConfigs.map(_.numIntSrc))
@@ -98,9 +99,11 @@ case class ExuConfig
   }
 }
 
-abstract class Exu(val config: ExuConfig)(implicit p: Parameters) extends XSModule {
+@instantiable
+abstract class Exu(cfg: ExuConfig)(implicit p: Parameters) extends XSModule {
+  @public val config = cfg
 
-  val io = IO(new Bundle() {
+  @public val io = IO(new Bundle() {
     val fromInt = if (config.readIntRf) Flipped(DecoupledIO(new ExuInput)) else null
     val fromFp = if (config.readFpRf) Flipped(DecoupledIO(new ExuInput)) else null
     val redirect = Flipped(ValidIO(new Redirect))
@@ -108,11 +111,11 @@ abstract class Exu(val config: ExuConfig)(implicit p: Parameters) extends XSModu
     val out = DecoupledIO(new ExuOutput)
   })
 
-  val csrio = if (config == JumpCSRExeUnitCfg) Some(IO(new CSRFileIO)) else None
-  val fenceio = if (config == JumpCSRExeUnitCfg) Some(IO(new FenceIO)) else None
-  val frm = if (config == FmacExeUnitCfg || config == FmiscExeUnitCfg) Some(IO(Input(UInt(3.W)))) else None
-  val fmaMid = if (config == FmacExeUnitCfg) Some(IO(new FMAMidResultIO)) else None
-  val stData = if (config == StdExeUnitCfg) Some(IO(ValidIO(new StoreDataBundle))) else None
+  @public val csrio = if (config == JumpCSRExeUnitCfg) Some(IO(new CSRFileIO)) else None
+  @public val fenceio = if (config == JumpCSRExeUnitCfg) Some(IO(new FenceIO)) else None
+  @public val frm = if (config == FmacExeUnitCfg || config == FmiscExeUnitCfg) Some(IO(Input(UInt(3.W)))) else None
+  @public val fmaMid = if (config == FmacExeUnitCfg) Some(IO(new FMAMidResultIO)) else None
+  @public val stData = if (config == StdExeUnitCfg) Some(IO(ValidIO(new StoreDataBundle))) else None
 
   val functionUnits = config.fuConfigs.map(cfg => {
     val mod = Module(cfg.fuGen(p))