intel_display.c 255.6 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dmi.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include <drm/drm_dp_helper.h>
#include <drm/drm_crtc_helper.h>
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#include <linux/dma_remapping.h>
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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} intel_clock_t;

typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

#define INTEL_P2_NUM		      2
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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
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	/**
	 * find_pll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_pll)(const intel_limit_t *limit,
			 struct drm_crtc *crtc,
			 int target, int refclk,
			 intel_clock_t *match_clock,
			 intel_clock_t *best_clock);
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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int
intel_pch_rawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	WARN_ON(!HAS_PCH_SPLIT(dev));

	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
}

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock);
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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);
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static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
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		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock);
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static bool
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intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock);
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static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);

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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_display_port = {
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	.dot = { .min = 161670, .max = 227000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 97, .max = 108 },
	.m1 = { .min = 0x10, .max = 0x12 },
	.m2 = { .min = 0x05, .max = 0x06 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_g4x_dp,
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_find_best_PLL,
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 81, .max = 90 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_ironlake_dp,
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};

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static const intel_limit_t intel_limits_vlv_dac = {
	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
	.n = { .min = 1, .max = 7 },
	.m = { .min = 22, .max = 450 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_hdmi = {
	.dot = { .min = 20000, .max = 165000 },
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	.vco = { .min = 4000000, .max = 5994000},
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	.n = { .min = 1, .max = 7 },
	.m = { .min = 60, .max = 300 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_dp = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
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	.m = { .min = 22, .max = 450 },
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	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

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u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
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	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
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	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO idle wait timed out\n");
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		return 0;
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	}

	I915_WRITE(DPIO_REG, reg);
	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
		   DPIO_BYTE);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO read wait timed out\n");
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		return 0;
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	}

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	return I915_READ(DPIO_DATA);
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}

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static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
			     u32 val)
{
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	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
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	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO idle wait timed out\n");
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		return;
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	}

	I915_WRITE(DPIO_DATA, val);
	I915_WRITE(DPIO_REG, reg);
	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
		   DPIO_BYTE);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
		DRM_ERROR("DPIO write wait timed out\n");
}

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static void vlv_init_dpio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Reset the DPIO config */
	I915_WRITE(DPIO_CTL, 0);
	POSTING_READ(DPIO_CTL);
	I915_WRITE(DPIO_CTL, 1);
	POSTING_READ(DPIO_CTL);
}

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (intel_is_dual_link_lvds(dev)) {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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		   intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
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		limit = &intel_limits_ironlake_display_port;
503
	else
504
		limit = &intel_limits_ironlake_dac;
505 506 507 508

	return limit;
}

509 510 511 512 513 514
static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515
		if (intel_is_dual_link_lvds(dev))
516
			limit = &intel_limits_g4x_dual_channel_lvds;
517
		else
518
			limit = &intel_limits_g4x_single_channel_lvds;
519 520
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521
		limit = &intel_limits_g4x_hdmi;
522
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523
		limit = &intel_limits_g4x_sdvo;
524
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525
		limit = &intel_limits_g4x_display_port;
526
	} else /* The option is for other outputs */
527
		limit = &intel_limits_i9xx_sdvo;
528 529 530 531

	return limit;
}

532
static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

537
	if (HAS_PCH_SPLIT(dev))
538
		limit = intel_ironlake_limit(crtc, refclk);
539
	else if (IS_G4X(dev)) {
540
		limit = intel_g4x_limit(crtc);
541
	} else if (IS_PINEVIEW(dev)) {
542
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543
			limit = &intel_limits_pineview_lvds;
544
		else
545
			limit = &intel_limits_pineview_sdvo;
546 547 548 549 550 551 552
	} else if (IS_VALLEYVIEW(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
			limit = &intel_limits_vlv_dac;
		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
			limit = &intel_limits_vlv_hdmi;
		else
			limit = &intel_limits_vlv_dp;
553 554 555 556 557
	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
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	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560
			limit = &intel_limits_i8xx_lvds;
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		else
562
			limit = &intel_limits_i8xx_dvo;
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	}
	return limit;
}

567 568
/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
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{
570 571 572 573 574 575 576 577
	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
578 579
	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
580 581
		return;
	}
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	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
591
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
593 594 595
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;

596 597
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->type == type)
598 599 600
			return true;

	return false;
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}

603
#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

609 610 611
static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
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{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
614
		INTELPllInvalid("p1 out of range\n");
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	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
616
		INTELPllInvalid("p out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
618
		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
620
		INTELPllInvalid("m1 out of range\n");
621
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622
		INTELPllInvalid("m1 <= m2\n");
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	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
624
		INTELPllInvalid("m out of range\n");
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625
	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
626
		INTELPllInvalid("n out of range\n");
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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628
		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633
		INTELPllInvalid("dot out of range\n");
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	return true;
}

638 639
static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 641
		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
642

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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int err = target;

648
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		/*
650 651 652
		 * For LVDS just rely on its current settings for dual-channel.
		 * We haven't figured out how to reliably set up different
		 * single/dual channel state, if we even can.
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		 */
654
		if (intel_is_dual_link_lvds(dev))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

665
	memset(best_clock, 0, sizeof(*best_clock));
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667 668 669 670
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
671 672
			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 674 675 676 677
				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

680
					intel_clock(dev, refclk, &clock);
681 682
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
684 685 686
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

701 702
static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 704
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
705 706 707 708 709
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int max_n;
	bool found;
710 711
	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
712 713 714
	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 716
		int lvds_reg;

717
		if (HAS_PCH_SPLIT(dev))
718 719 720
			lvds_reg = PCH_LVDS;
		else
			lvds_reg = LVDS;
721
		if (intel_is_dual_link_lvds(dev))
722 723 724 725 726 727 728 729 730 731 732 733
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
734
	/* based on hardware requirement, prefer smaller n to precision */
735
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736
		/* based on hardware requirement, prefere larger m1,m2 */
737 738 739 740 741 742 743 744
		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

745
					intel_clock(dev, refclk, &clock);
746 747
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
748
						continue;
749 750 751
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
752 753

					this_err = abs(clock.dot - target);
754 755 756 757 758 759 760 761 762 763
					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
764 765 766
	return found;
}

767
static bool
768
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 770
			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock)
771 772 773
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
774

775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792
	if (target < 200000) {
		clock.n = 1;
		clock.p1 = 2;
		clock.p2 = 10;
		clock.m1 = 12;
		clock.m2 = 9;
	} else {
		clock.n = 2;
		clock.p1 = 1;
		clock.p2 = 10;
		clock.m1 = 14;
		clock.m2 = 8;
	}
	intel_clock(dev, refclk, &clock);
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

793 794 795
/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 797
		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock)
798
{
799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818
	intel_clock_t clock;
	if (target < 200000) {
		clock.p1 = 2;
		clock.p2 = 10;
		clock.n = 2;
		clock.m1 = 23;
		clock.m2 = 8;
	} else {
		clock.p1 = 1;
		clock.p2 = 10;
		clock.n = 1;
		clock.m1 = 14;
		clock.m2 = 2;
	}
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
	clock.p = (clock.p1 * clock.p2);
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
	clock.vco = 0;
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
819
}
820 821 822 823 824 825 826 827 828 829 830
static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
{
	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
	u32 m, n, fastclk;
	u32 updrate, minupdate, fracbits, p;
	unsigned long bestppm, ppm, absppm;
	int dotclk, flag;

831
	flag = 0;
832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887
	dotclk = target * 1000;
	bestppm = 1000000;
	ppm = absppm = 0;
	fastclk = dotclk / (2*100);
	updrate = 0;
	minupdate = 19200;
	fracbits = 1;
	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
	bestm1 = bestm2 = bestp1 = bestp2 = 0;

	/* based on hardware requirement, prefer smaller n to precision */
	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		updrate = refclk / n;
		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
				if (p2 > 10)
					p2 = p2 - 1;
				p = p1 * p2;
				/* based on hardware requirement, prefer bigger m1,m2 values */
				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
					m2 = (((2*(fastclk * p * n / m1 )) +
					       refclk) / (2*refclk));
					m = m1 * m2;
					vco = updrate * m;
					if (vco >= limit->vco.min && vco < limit->vco.max) {
						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
						absppm = (ppm > 0) ? ppm : (-ppm);
						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
							bestppm = 0;
							flag = 1;
						}
						if (absppm < bestppm - 10) {
							bestppm = absppm;
							flag = 1;
						}
						if (flag) {
							bestn = n;
							bestm1 = m1;
							bestm2 = m2;
							bestp1 = p1;
							bestp2 = p2;
							flag = 0;
						}
					}
				}
			}
		}
	}
	best_clock->n = bestn;
	best_clock->m1 = bestm1;
	best_clock->m2 = bestm2;
	best_clock->p1 = bestp1;
	best_clock->p2 = bestp2;

	return true;
}
888

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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe)
{
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	return intel_crtc->cpu_transcoder;
}

898 899 900 901 902 903 904 905 906 907 908
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 frame, frame_reg = PIPEFRAME(pipe);

	frame = I915_READ(frame_reg);

	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

909 910 911 912 913 914 915 916 917
/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
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{
919
	struct drm_i915_private *dev_priv = dev->dev_private;
920
	int pipestat_reg = PIPESTAT(pipe);
921

922 923 924 925 926
	if (INTEL_INFO(dev)->gen >= 5) {
		ironlake_wait_for_vblank(dev, pipe);
		return;
	}

927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942
	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

943
	/* Wait for vblank interrupt bit to set */
944 945 946
	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
947 948 949
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

950 951
/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
952 953 954 955 956 957 958
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
959 960 961 962 963 964
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
965
 *
966
 */
967
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
968 969
{
	struct drm_i915_private *dev_priv = dev->dev_private;
970 971
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
972 973

	if (INTEL_INFO(dev)->gen >= 4) {
974
		int reg = PIPECONF(cpu_transcoder);
975 976

		/* Wait for the Pipe State to go off */
977 978
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
979
			WARN(1, "pipe_off wait timed out\n");
980
	} else {
981
		u32 last_line, line_mask;
982
		int reg = PIPEDSL(pipe);
983 984
		unsigned long timeout = jiffies + msecs_to_jiffies(100);

985 986 987 988 989
		if (IS_GEN2(dev))
			line_mask = DSL_LINEMASK_GEN2;
		else
			line_mask = DSL_LINEMASK_GEN3;

990 991
		/* Wait for the display line to settle */
		do {
992
			last_line = I915_READ(reg) & line_mask;
993
			mdelay(5);
994
		} while (((I915_READ(reg) & line_mask) != last_line) &&
995 996
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
997
			WARN(1, "pipe_off wait timed out\n");
998
	}
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}

1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
/*
 * ibx_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Returns true if @port is connected, false otherwise.
 */
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				struct intel_digital_port *port)
{
	u32 bit;

1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
	if (HAS_PCH_IBX(dev_priv->dev)) {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG;
			break;
		default:
			return true;
		}
	} else {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG_CPT;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG_CPT;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG_CPT;
			break;
		default:
			return true;
		}
1041 1042 1043 1044 1045
	}

	return I915_READ(SDEISR) & bit;
}

1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

1069 1070
/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 1072 1073
			   struct intel_pch_pll *pll,
			   struct intel_crtc *crtc,
			   bool state)
1074 1075 1076 1077
{
	u32 val;
	bool cur_state;

E
Eugeni Dodonov 已提交
1078 1079 1080 1081 1082
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		return;
	}

1083 1084
	if (WARN (!pll,
		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085 1086
		return;

1087 1088 1089 1090 1091 1092 1093 1094
	val = I915_READ(pll->pll_reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
	     pll->pll_reg, state_string(state), state_string(cur_state), val);

	/* Make sure the selected PLL is correctly attached to the transcoder */
	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 1096 1097
		u32 pch_dpll;

		pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
		cur_state = pll->pll_reg == _PCH_DPLL_B;
		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
			  "PLL[%d] not attached to this transcoder %d: %08x\n",
			  cur_state, crtc->pipe, pch_dpll)) {
			cur_state = !!(val >> (4*crtc->pipe + 3));
			WARN(cur_state != state,
			     "PLL[%d] not %s on this transcoder %d: %08x\n",
			     pll->pll_reg == _PCH_DPLL_B,
			     state_string(state),
			     crtc->pipe,
			     val);
		}
1110
	}
1111
}
1112 1113
#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114 1115 1116 1117 1118 1119 1120

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;
1121 1122
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1123

P
Paulo Zanoni 已提交
1124 1125
	if (HAS_DDI(dev_priv->dev)) {
		/* DDI does not have a specific FDI_TX register */
1126
		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127
		val = I915_READ(reg);
1128
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 1130 1131 1132 1133
	} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
	}
1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

1148 1149 1150
	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & FDI_RX_ENABLE);
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

1168
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
P
Paulo Zanoni 已提交
1169
	if (HAS_DDI(dev_priv->dev))
1170 1171
		return;

1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

1188 1189 1190 1191 1192 1193
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
1194
	bool locked = true;
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213

	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
1214
	     pipe_name(pipe));
1215 1216
}

1217 1218
void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
1219 1220 1221
{
	int reg;
	u32 val;
1222
	bool cur_state;
1223 1224
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1225

1226 1227 1228 1229
	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

1230 1231 1232 1233 1234 1235 1236 1237 1238
	if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
	    !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
		cur_state = false;
	} else {
		reg = PIPECONF(cpu_transcoder);
		val = I915_READ(reg);
		cur_state = !!(val & PIPECONF_ENABLE);
	}

1239 1240
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
1241
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1242 1243
}

1244 1245
static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
1246 1247 1248
{
	int reg;
	u32 val;
1249
	bool cur_state;
1250 1251 1252

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1253 1254 1255 1256
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
1257 1258
}

1259 1260 1261
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

1262 1263 1264 1265 1266 1267 1268
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
	int reg, i;
	u32 val;
	int cur_pipe;

1269
	/* Planes are fixed to pipes on ILK+ */
1270
	if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 1272 1273 1274 1275
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
1276
		return;
1277
	}
1278

1279 1280 1281 1282 1283 1284 1285
	/* Need to check both planes against the pipe */
	for (i = 0; i < 2; i++) {
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 1287
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
1288 1289 1290
	}
}

1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
	int reg, i;
	u32 val;

	if (!IS_VALLEYVIEW(dev_priv->dev))
		return;

	/* Need to check both planes against the pipe */
	for (i = 0; i < dev_priv->num_plane; i++) {
		reg = SPCNTR(pipe, i);
		val = I915_READ(reg);
		WARN((val & SP_ENABLE),
		     "sprite %d assertion failure, should be off on pipe %c but is still active\n",
		     pipe * 2 + i, pipe_name(pipe));
	}
}

1310 1311 1312 1313 1314
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

E
Eugeni Dodonov 已提交
1315 1316 1317 1318 1319
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		return;
	}

1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
				       enum pipe pipe)
{
	int reg;
	u32 val;
	bool enabled;

	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
1336 1337 1338
	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
1339 1340
}

1341 1342
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

1359 1360 1361
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
1362
	if ((val & SDVO_ENABLE) == 0)
1363 1364 1365
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
1366
		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367 1368
			return false;
	} else {
1369
		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
			return false;
	}
	return true;
}

1406
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407
				   enum pipe pipe, int reg, u32 port_sel)
1408
{
1409
	u32 val = I915_READ(reg);
1410
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412
	     reg, pipe_name(pipe));
1413

1414 1415
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
	     && (val & DP_PIPEB_SELECT),
1416
	     "IBX PCH dp port still using transcoder B\n");
1417 1418 1419 1420 1421
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
				     enum pipe pipe, int reg)
{
1422
	u32 val = I915_READ(reg);
1423
	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425
	     reg, pipe_name(pipe));
1426

1427
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428
	     && (val & SDVO_PIPE_B_SELECT),
1429
	     "IBX PCH hdmi port still using transcoder B\n");
1430 1431 1432 1433 1434 1435 1436 1437
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1438 1439 1440
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441 1442 1443

	reg = PCH_ADPA;
	val = I915_READ(reg);
1444
	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1446
	     pipe_name(pipe));
1447 1448 1449

	reg = PCH_LVDS;
	val = I915_READ(reg);
1450
	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452
	     pipe_name(pipe));
1453

1454 1455 1456
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 1458
}

1459 1460 1461 1462 1463 1464 1465 1466 1467 1468
/**
 * intel_enable_pll - enable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
 * make sure the PLL reg is writable first though, since the panel write
 * protect mechanism may be enabled.
 *
 * Note!  This is for pre-ILK only.
1469 1470
 *
 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471 1472 1473 1474 1475 1476 1477
 */
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* No really, not for ILK+ */
1478
	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527

	/* PLL is protected by panel, make sure we can write it */
	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		assert_panel_unlocked(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;

	/* We do this three times for luck */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

/**
 * intel_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Make sure the pipe isn't still relying on us */
	assert_pipe_disabled(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

1528 1529
/* SBI access */
static void
1530 1531
intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		enum intel_sbi_destination destination)
1532
{
1533
	u32 tmp;
1534

1535
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536

1537
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538 1539
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
1540
		return;
1541 1542
	}

1543 1544 1545 1546 1547 1548 1549 1550
	I915_WRITE(SBI_ADDR, (reg << 16));
	I915_WRITE(SBI_DATA, value);

	if (destination == SBI_ICLK)
		tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
	else
		tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
	I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551

1552
	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553 1554
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555
		return;
1556 1557 1558 1559
	}
}

static u32
1560 1561
intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
	       enum intel_sbi_destination destination)
1562
{
1563
	u32 value = 0;
1564
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565

1566
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567 1568
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
1569
		return 0;
1570 1571
	}

1572 1573 1574 1575 1576 1577 1578
	I915_WRITE(SBI_ADDR, (reg << 16));

	if (destination == SBI_ICLK)
		value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
	else
		value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
	I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579

1580
	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581 1582
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583
		return 0;
1584 1585
	}

1586
	return I915_READ(SBI_DATA);
1587 1588
}

1589
/**
1590
 * ironlake_enable_pch_pll - enable PCH PLL
1591 1592 1593 1594 1595 1596
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
1597
static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598
{
1599
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600
	struct intel_pch_pll *pll;
1601 1602 1603
	int reg;
	u32 val;

1604
	/* PCH PLLs only available on ILK, SNB and IVB */
1605
	BUG_ON(dev_priv->info->gen < 5);
1606 1607 1608 1609 1610 1611
	pll = intel_crtc->pch_pll;
	if (pll == NULL)
		return;

	if (WARN_ON(pll->refcount == 0))
		return;
1612 1613 1614 1615

	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1616 1617 1618 1619

	/* PCH refclock must be enabled first */
	assert_pch_refclk_enabled(dev_priv);

1620
	if (pll->active++ && pll->on) {
1621
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1622 1623 1624 1625 1626 1627
		return;
	}

	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);

	reg = pll->pll_reg;
1628 1629 1630 1631 1632
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1633 1634

	pll->on = true;
1635 1636
}

1637
static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638
{
1639 1640
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641
	int reg;
1642
	u32 val;
1643

1644 1645
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);
1646 1647
	if (pll == NULL)
	       return;
1648

1649 1650
	if (WARN_ON(pll->refcount == 0))
		return;
1651

1652 1653 1654
	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1655

1656
	if (WARN_ON(pll->active == 0)) {
1657
		assert_pch_pll_disabled(dev_priv, pll, NULL);
1658 1659 1660
		return;
	}

1661
	if (--pll->active) {
1662
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1663
		return;
1664 1665 1666 1667 1668 1669
	}

	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);

	/* Make sure transcoder isn't still depending on us */
	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670

1671
	reg = pll->pll_reg;
1672 1673 1674 1675 1676
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1677 1678

	pll->on = false;
1679 1680
}

1681 1682
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
					   enum pipe pipe)
1683
{
1684
	struct drm_device *dev = dev_priv->dev;
1685
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686
	uint32_t reg, val, pipeconf_val;
1687 1688 1689 1690 1691

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure PCH DPLL is enabled */
1692 1693 1694
	assert_pch_pll_enabled(dev_priv,
			       to_intel_crtc(crtc)->pch_pll,
			       to_intel_crtc(crtc));
1695 1696 1697 1698 1699

	/* FDI must be feeding us bits for PCH ports */
	assert_fdi_tx_enabled(dev_priv, pipe);
	assert_fdi_rx_enabled(dev_priv, pipe);

1700 1701 1702 1703 1704 1705 1706
	if (HAS_PCH_CPT(dev)) {
		/* Workaround: Set the timing override bit before enabling the
		 * pch transcoder. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
1707
	}
1708

1709 1710
	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
1711
	pipeconf_val = I915_READ(PIPECONF(pipe));
1712 1713 1714 1715 1716 1717

	if (HAS_PCH_IBX(dev_priv->dev)) {
		/*
		 * make the BPC in transcoder be consistent with
		 * that in pipeconf reg.
		 */
1718 1719
		val &= ~PIPECONF_BPC_MASK;
		val |= pipeconf_val & PIPECONF_BPC_MASK;
1720
	}
1721 1722 1723

	val &= ~TRANS_INTERLACE_MASK;
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724 1725 1726 1727 1728
		if (HAS_PCH_IBX(dev_priv->dev) &&
		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
			val |= TRANS_LEGACY_INTERLACED_ILK;
		else
			val |= TRANS_INTERLACED;
1729 1730 1731
	else
		val |= TRANS_PROGRESSIVE;

1732 1733 1734 1735 1736
	I915_WRITE(reg, val | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("failed to enable transcoder %d\n", pipe);
}

1737
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738
				      enum transcoder cpu_transcoder)
1739
{
1740 1741 1742 1743 1744 1745
	u32 val, pipeconf_val;

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* FDI must be feeding us bits for PCH ports */
D
Daniel Vetter 已提交
1746
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748

1749 1750
	/* Workaround: set timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1751
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 1753
	I915_WRITE(_TRANSA_CHICKEN2, val);

1754
	val = TRANS_ENABLE;
1755
	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756

1757 1758
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
	    PIPECONF_INTERLACED_ILK)
1759
		val |= TRANS_INTERLACED;
1760 1761 1762
	else
		val |= TRANS_PROGRESSIVE;

1763
	I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764 1765
	if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("Failed to enable PCH transcoder\n");
1766 1767
}

1768 1769
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
					    enum pipe pipe)
1770
{
1771 1772
	struct drm_device *dev = dev_priv->dev;
	uint32_t reg, val;
1773 1774 1775 1776 1777

	/* FDI relies on the transcoder */
	assert_fdi_tx_disabled(dev_priv, pipe);
	assert_fdi_rx_disabled(dev_priv, pipe);

1778 1779 1780
	/* Ports must be off as well */
	assert_pch_ports_disabled(dev_priv, pipe);

1781 1782 1783 1784 1785 1786
	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	val &= ~TRANS_ENABLE;
	I915_WRITE(reg, val);
	/* wait for PCH transcoder off, transcoder state */
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787
		DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788 1789 1790 1791 1792 1793 1794 1795

	if (!HAS_PCH_IBX(dev)) {
		/* Workaround: Clear the timing override chicken bit again. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
	}
1796 1797
}

1798
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 1800 1801
{
	u32 val;

1802
	val = I915_READ(_TRANSACONF);
1803
	val &= ~TRANS_ENABLE;
1804
	I915_WRITE(_TRANSACONF, val);
1805
	/* wait for PCH transcoder off, transcoder state */
1806 1807
	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
		DRM_ERROR("Failed to disable PCH transcoder\n");
1808 1809 1810

	/* Workaround: clear timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1811
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812
	I915_WRITE(_TRANSA_CHICKEN2, val);
1813 1814
}

1815
/**
1816
 * intel_enable_pipe - enable a pipe, asserting requirements
1817 1818
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
1819
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820 1821 1822 1823 1824 1825 1826 1827 1828
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
1829 1830
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			      bool pch_port)
1831
{
1832 1833
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
D
Daniel Vetter 已提交
1834
	enum pipe pch_transcoder;
1835 1836 1837
	int reg;
	u32 val;

1838
	if (HAS_PCH_LPT(dev_priv->dev))
1839 1840 1841 1842
		pch_transcoder = TRANSCODER_A;
	else
		pch_transcoder = pipe;

1843 1844 1845 1846 1847 1848 1849
	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);
1850 1851 1852
	else {
		if (pch_port) {
			/* if driving the PCH, we need FDI enabled */
1853
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
D
Daniel Vetter 已提交
1854 1855
			assert_fdi_tx_pll_enabled(dev_priv,
						  (enum pipe) cpu_transcoder);
1856 1857 1858
		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
1859

1860
	reg = PIPECONF(cpu_transcoder);
1861
	val = I915_READ(reg);
1862 1863 1864 1865
	if (val & PIPECONF_ENABLE)
		return;

	I915_WRITE(reg, val | PIPECONF_ENABLE);
1866 1867 1868 1869
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
1870
 * intel_disable_pipe - disable a pipe, asserting requirements
1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
1884 1885
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1886 1887 1888 1889 1890 1891 1892 1893
	int reg;
	u32 val;

	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
	assert_planes_disabled(dev_priv, pipe);
1894
	assert_sprites_disabled(dev_priv, pipe);
1895 1896 1897 1898 1899

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

1900
	reg = PIPECONF(cpu_transcoder);
1901
	val = I915_READ(reg);
1902 1903 1904 1905
	if ((val & PIPECONF_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906 1907 1908
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

1909 1910 1911 1912
/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
1913
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914 1915
				      enum plane plane)
{
1916 1917 1918 1919
	if (dev_priv->info->gen >= 4)
		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
	else
		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 1921
}

1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940
/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
			       enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	/* If the pipe isn't enabled, we can't pump pixels and may hang */
	assert_pipe_enabled(dev_priv, pipe);

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1941 1942 1943 1944
	if (val & DISPLAY_PLANE_ENABLE)
		return;

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945
	intel_flush_display_plane(dev_priv, plane);
1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
				enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1965 1966 1967 1968
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969 1970 1971 1972
	intel_flush_display_plane(dev_priv, plane);
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

1973 1974 1975 1976 1977 1978 1979 1980 1981
static bool need_vtd_wa(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

1982
int
1983
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984
			   struct drm_i915_gem_object *obj,
1985
			   struct intel_ring_buffer *pipelined)
1986
{
1987
	struct drm_i915_private *dev_priv = dev->dev_private;
1988 1989 1990
	u32 alignment;
	int ret;

1991
	switch (obj->tiling_mode) {
1992
	case I915_TILING_NONE:
1993 1994
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
1995
		else if (INTEL_INFO(dev)->gen >= 4)
1996 1997 1998
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
		/* FIXME: Is this true? */
		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		return -EINVAL;
	default:
		BUG();
	}

2012 2013 2014 2015 2016 2017 2018 2019
	/* Note that the w/a also requires 64 PTE of padding following the
	 * bo. We currently fill all unused PTE with the shadow page and so
	 * we should always have valid PTE following the scanout preventing
	 * the VT-d warning.
	 */
	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		alignment = 256 * 1024;

2020
	dev_priv->mm.interruptible = false;
2021
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2022
	if (ret)
2023
		goto err_interruptible;
2024 2025 2026 2027 2028 2029

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
2030
	ret = i915_gem_object_get_fence(obj);
2031 2032
	if (ret)
		goto err_unpin;
2033

2034
	i915_gem_object_pin_fence(obj);
2035

2036
	dev_priv->mm.interruptible = true;
2037
	return 0;
2038 2039 2040

err_unpin:
	i915_gem_object_unpin(obj);
2041 2042
err_interruptible:
	dev_priv->mm.interruptible = true;
2043
	return ret;
2044 2045
}

2046 2047 2048 2049 2050 2051
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_fence(obj);
	i915_gem_object_unpin(obj);
}

2052 2053
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
 * is assumed to be a power-of-two. */
2054 2055 2056 2057
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
					     unsigned int tiling_mode,
					     unsigned int cpp,
					     unsigned int pitch)
2058
{
2059 2060
	if (tiling_mode != I915_TILING_NONE) {
		unsigned int tile_rows, tiles;
2061

2062 2063
		tile_rows = *y / 8;
		*y %= 8;
2064

2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076
		tiles = *x / (512/cpp);
		*x %= 512/cpp;

		return tile_rows * pitch * 8 + tiles * 4096;
	} else {
		unsigned int offset;

		offset = *y * pitch + *x * cpp;
		*y = 0;
		*x = (offset & 4095) / cpp;
		return offset & -4096;
	}
2077 2078
}

2079 2080
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			     int x, int y)
J
Jesse Barnes 已提交
2081 2082 2083 2084 2085
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
2086
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
2087
	int plane = intel_crtc->plane;
2088
	unsigned long linear_offset;
J
Jesse Barnes 已提交
2089
	u32 dspcntr;
2090
	u32 reg;
J
Jesse Barnes 已提交
2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

2104 2105
	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
J
Jesse Barnes 已提交
2106 2107
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108 2109
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
J
Jesse Barnes 已提交
2110 2111
		dspcntr |= DISPPLANE_8BPP;
		break;
2112 2113 2114
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		dspcntr |= DISPPLANE_BGRX555;
J
Jesse Barnes 已提交
2115
		break;
2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
		break;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
J
Jesse Barnes 已提交
2134 2135
		break;
	default:
2136
		BUG();
J
Jesse Barnes 已提交
2137
	}
2138

2139
	if (INTEL_INFO(dev)->gen >= 4) {
2140
		if (obj->tiling_mode != I915_TILING_NONE)
J
Jesse Barnes 已提交
2141 2142 2143 2144 2145
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

2146
	I915_WRITE(reg, dspcntr);
J
Jesse Barnes 已提交
2147

2148
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
J
Jesse Barnes 已提交
2149

2150 2151
	if (INTEL_INFO(dev)->gen >= 4) {
		intel_crtc->dspaddr_offset =
2152 2153 2154
			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
						       fb->bits_per_pixel / 8,
						       fb->pitches[0]);
2155 2156
		linear_offset -= intel_crtc->dspaddr_offset;
	} else {
2157
		intel_crtc->dspaddr_offset = linear_offset;
2158
	}
2159 2160 2161

	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2162
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2163
	if (INTEL_INFO(dev)->gen >= 4) {
2164 2165
		I915_MODIFY_DISPBASE(DSPSURF(plane),
				     obj->gtt_offset + intel_crtc->dspaddr_offset);
2166
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2167
		I915_WRITE(DSPLINOFF(plane), linear_offset);
2168
	} else
2169
		I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2170
	POSTING_READ(reg);
J
Jesse Barnes 已提交
2171

2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183
	return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
2184
	unsigned long linear_offset;
2185 2186 2187 2188 2189 2190
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
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	case 2:
2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205 2206
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
2207 2208
		dspcntr |= DISPPLANE_8BPP;
		break;
2209 2210
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
2211
		break;
2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
2227 2228
		break;
	default:
2229
		BUG();
2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241
	}

	if (obj->tiling_mode != I915_TILING_NONE)
		dspcntr |= DISPPLANE_TILED;
	else
		dspcntr &= ~DISPPLANE_TILED;

	/* must disable */
	dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

	I915_WRITE(reg, dspcntr);

2242
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2243
	intel_crtc->dspaddr_offset =
2244 2245 2246
		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
					       fb->bits_per_pixel / 8,
					       fb->pitches[0]);
2247
	linear_offset -= intel_crtc->dspaddr_offset;
2248

2249 2250
	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2251
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2252 2253
	I915_MODIFY_DISPBASE(DSPSURF(plane),
			     obj->gtt_offset + intel_crtc->dspaddr_offset);
2254 2255 2256 2257 2258 2259
	if (IS_HASWELL(dev)) {
		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
	} else {
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
		I915_WRITE(DSPLINOFF(plane), linear_offset);
	}
2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272
	POSTING_READ(reg);

	return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2273 2274
	if (dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);
2275
	intel_increase_pllclock(crtc);
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2277
	return dev_priv->display.update_plane(crtc, fb, x, y);
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2278 2279
}

2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317
void intel_display_handle_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;

	/*
	 * Flips in the rings have been nuked by the reset,
	 * so complete all pending flips so that user space
	 * will get its events and not get stuck.
	 *
	 * Also update the base address of all primary
	 * planes to the the last fb to make sure we're
	 * showing the correct fb after a reset.
	 *
	 * Need to make two loops over the crtcs so that we
	 * don't try to grab a crtc mutex before the
	 * pending_flip_queue really got woken up.
	 */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		enum plane plane = intel_crtc->plane;

		intel_prepare_page_flip(dev, plane);
		intel_finish_page_flip_plane(dev, plane);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

		mutex_lock(&crtc->mutex);
		if (intel_crtc->active)
			dev_priv->display.update_plane(crtc, crtc->fb,
						       crtc->x, crtc->y);
		mutex_unlock(&crtc->mutex);
	}
}

2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340
static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	bool was_interruptible = dev_priv->mm.interruptible;
	int ret;

	/* Big Hammer, we also need to ensure that any pending
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
	 * current scanout is retired before unpinning the old
	 * framebuffer.
	 *
	 * This should only fail upon a hung GPU, in which case we
	 * can safely continue.
	 */
	dev_priv->mm.interruptible = false;
	ret = i915_gem_object_finish_gpu(obj);
	dev_priv->mm.interruptible = was_interruptible;

	return ret;
}

2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367
static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (intel_crtc->pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
		break;
	default:
		break;
	}
}

2368
static int
2369
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2370
		    struct drm_framebuffer *fb)
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2371 2372
{
	struct drm_device *dev = crtc->dev;
2373
	struct drm_i915_private *dev_priv = dev->dev_private;
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2374
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375
	struct drm_framebuffer *old_fb;
2376
	int ret;
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2377 2378

	/* no fb bound */
2379
	if (!fb) {
2380
		DRM_ERROR("No FB bound\n");
2381 2382 2383
		return 0;
	}

2384
	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2385 2386
		DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
				intel_crtc->plane,
2387
				INTEL_INFO(dev)->num_pipes);
2388
		return -EINVAL;
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2389 2390
	}

2391
	mutex_lock(&dev->struct_mutex);
2392
	ret = intel_pin_and_fence_fb_obj(dev,
2393
					 to_intel_framebuffer(fb)->obj,
2394
					 NULL);
2395 2396
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
2397
		DRM_ERROR("pin & fence failed\n");
2398 2399
		return ret;
	}
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2400

2401
	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2402
	if (ret) {
2403
		intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2404
		mutex_unlock(&dev->struct_mutex);
2405
		DRM_ERROR("failed to update base address\n");
2406
		return ret;
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2407
	}
2408

2409 2410
	old_fb = crtc->fb;
	crtc->fb = fb;
2411 2412
	crtc->x = x;
	crtc->y = y;
2413

2414 2415
	if (old_fb) {
		intel_wait_for_vblank(dev, intel_crtc->pipe);
2416
		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2417
	}
2418

2419
	intel_update_fbc(dev);
2420
	mutex_unlock(&dev->struct_mutex);
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2421

2422
	intel_crtc_update_sarea_pos(crtc, x, y);
2423 2424

	return 0;
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2425 2426
}

2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437
static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2438
	if (IS_IVYBRIDGE(dev)) {
2439 2440
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2441 2442 2443
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2444
	}
2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
2461 2462 2463 2464 2465

	/* IVB wants error correction enabled */
	if (IS_IVYBRIDGE(dev))
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
			   FDI_FE_ERRC_ENABLE);
2466 2467
}

2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490
static void ivb_modeset_global_resources(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
	struct intel_crtc *pipe_C_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
	uint32_t temp;

	/* When everything is off disable fdi C so that we could enable fdi B
	 * with all lanes. XXX: This misses the case where a pipe is not using
	 * any pch resources and so doesn't need any fdi lanes. */
	if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

		temp = I915_READ(SOUTH_CHICKEN1);
		temp &= ~FDI_BC_BIFURCATION_SELECT;
		DRM_DEBUG_KMS("disabling fdi C rx\n");
		I915_WRITE(SOUTH_CHICKEN1, temp);
	}
}

2491 2492 2493 2494 2495 2496 2497
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2498
	int plane = intel_crtc->plane;
2499
	u32 reg, temp, tries;
2500

2501 2502 2503 2504
	/* FDI needs bits from pipe & plane first */
	assert_pipe_enabled(dev_priv, pipe);
	assert_plane_enabled(dev_priv, plane);

2505 2506
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2507 2508
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2509 2510
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2511 2512
	I915_WRITE(reg, temp);
	I915_READ(reg);
2513 2514
	udelay(150);

2515
	/* enable CPU FDI TX and PCH FDI RX */
2516 2517
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2518 2519
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2520 2521
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2522
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2523

2524 2525
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2526 2527
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2528 2529 2530
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2531 2532
	udelay(150);

2533
	/* Ironlake workaround, enable clock pointer after FDI enable*/
2534 2535 2536
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
		   FDI_RX_PHASE_SYNC_POINTER_EN);
2537

2538
	reg = FDI_RX_IIR(pipe);
2539
	for (tries = 0; tries < 5; tries++) {
2540
		temp = I915_READ(reg);
2541 2542 2543 2544
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
2545
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2546 2547 2548
			break;
		}
	}
2549
	if (tries == 5)
2550
		DRM_ERROR("FDI train 1 fail!\n");
2551 2552

	/* Train 2 */
2553 2554
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2555 2556
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2557
	I915_WRITE(reg, temp);
2558

2559 2560
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2561 2562
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2563
	I915_WRITE(reg, temp);
2564

2565 2566
	POSTING_READ(reg);
	udelay(150);
2567

2568
	reg = FDI_RX_IIR(pipe);
2569
	for (tries = 0; tries < 5; tries++) {
2570
		temp = I915_READ(reg);
2571 2572 2573
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2574
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575 2576 2577 2578
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
2579
	if (tries == 5)
2580
		DRM_ERROR("FDI train 2 fail!\n");
2581 2582

	DRM_DEBUG_KMS("FDI train done\n");
2583

2584 2585
}

2586
static const int snb_b_fdi_train_param[] = {
2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2600
	u32 reg, temp, i, retry;
2601

2602 2603
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2604 2605
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2606 2607
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2608 2609 2610
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2611 2612
	udelay(150);

2613
	/* enable CPU FDI TX and PCH FDI RX */
2614 2615
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2616 2617
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2618 2619 2620 2621 2622
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624

2625 2626 2627
	I915_WRITE(FDI_RX_MISC(pipe),
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

2628 2629
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2630 2631 2632 2633 2634 2635 2636
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
2637 2638 2639
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2640 2641
	udelay(150);

2642
	for (i = 0; i < 4; i++) {
2643 2644
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2645 2646
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2647 2648 2649
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2650 2651
		udelay(500);

2652 2653 2654 2655 2656 2657 2658 2659 2660 2661
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_BIT_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
				DRM_DEBUG_KMS("FDI train 1 done.\n");
				break;
			}
			udelay(50);
2662
		}
2663 2664
		if (retry < 5)
			break;
2665 2666
	}
	if (i == 4)
2667
		DRM_ERROR("FDI train 1 fail!\n");
2668 2669

	/* Train 2 */
2670 2671
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2672 2673 2674 2675 2676 2677 2678
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
2679
	I915_WRITE(reg, temp);
2680

2681 2682
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2683 2684 2685 2686 2687 2688 2689
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
2690 2691 2692
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2693 2694
	udelay(150);

2695
	for (i = 0; i < 4; i++) {
2696 2697
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2698 2699
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2700 2701 2702
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2703 2704
		udelay(500);

2705 2706 2707 2708 2709 2710 2711 2712 2713 2714
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_SYMBOL_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
				DRM_DEBUG_KMS("FDI train 2 done.\n");
				break;
			}
			udelay(50);
2715
		}
2716 2717
		if (retry < 5)
			break;
2718 2719
	}
	if (i == 4)
2720
		DRM_ERROR("FDI train 2 fail!\n");
2721 2722 2723 2724

	DRM_DEBUG_KMS("FDI train done.\n");
}

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, i;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2745 2746 2747
	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		      I915_READ(FDI_RX_IIR(pipe)));

2748 2749 2750 2751 2752 2753 2754 2755 2756
	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2757
	temp |= FDI_COMPOSITE_SYNC;
2758 2759
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

2760 2761 2762
	I915_WRITE(FDI_RX_MISC(pipe),
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

2763 2764 2765 2766 2767
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_AUTO;
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2768
	temp |= FDI_COMPOSITE_SYNC;
2769 2770 2771 2772 2773
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

2774
	for (i = 0; i < 4; i++) {
2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK ||
		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791
			DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2816
	for (i = 0; i < 4; i++) {
2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2832
			DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2833 2834 2835 2836 2837 2838 2839 2840 2841
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done.\n");
}

2842
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2843
{
2844
	struct drm_device *dev = intel_crtc->base.dev;
2845 2846
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
2847
	u32 reg, temp;
J
Jesse Barnes 已提交
2848

2849

2850
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2851 2852 2853
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~((0x7 << 19) | (0x7 << 16));
2854
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2855
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2856 2857 2858
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
2859 2860 2861
	udelay(200);

	/* Switch from Rawclk to PCDclk */
2862 2863 2864 2865
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
2866 2867
	udelay(200);

2868 2869 2870 2871 2872
	/* Enable CPU FDI TX PLL, always on for Ironlake */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2873

2874 2875
		POSTING_READ(reg);
		udelay(100);
2876
	}
2877 2878
}

2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* Switch from PCDclk to Rawclk */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);

	/* Disable CPU FDI TX PLL */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

	/* Wait for the clocks to turn off. */
	POSTING_READ(reg);
	udelay(100);
}

2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
2925
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2926 2927 2928 2929 2930 2931
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
2932 2933 2934
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	}
2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
2954
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2955 2956 2957 2958 2959 2960
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);
}

2961 2962 2963 2964
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2965
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2966 2967 2968
	unsigned long flags;
	bool pending;

2969 2970
	if (i915_reset_in_progress(&dev_priv->gpu_error) ||
	    intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2971 2972 2973 2974 2975 2976 2977 2978 2979
		return false;

	spin_lock_irqsave(&dev->event_lock, flags);
	pending = to_intel_crtc(crtc)->unpin_work != NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	return pending;
}

2980 2981
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
2982
	struct drm_device *dev = crtc->dev;
2983
	struct drm_i915_private *dev_priv = dev->dev_private;
2984 2985 2986 2987

	if (crtc->fb == NULL)
		return;

2988 2989
	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));

2990 2991 2992
	wait_event(dev_priv->pending_flip_queue,
		   !intel_crtc_has_pending_flip(crtc));

2993 2994 2995
	mutex_lock(&dev->struct_mutex);
	intel_finish_fb(crtc->fb);
	mutex_unlock(&dev->struct_mutex);
2996 2997
}

2998 2999 3000 3001 3002 3003 3004 3005
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
	u32 temp;

3006 3007
	mutex_lock(&dev_priv->dpio_lock);

3008 3009 3010 3011 3012 3013 3014
	/* It is necessary to ungate the pixclk gate prior to programming
	 * the divisors, and gate it back when it is done.
	 */
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);

	/* Disable SSCCTL */
	intel_sbi_write(dev_priv, SBI_SSCCTL6,
3015 3016 3017
			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
				SBI_SSCCTL_DISABLE,
			SBI_ICLK);
3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057

	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
	if (crtc->mode.clock == 20000) {
		auxdiv = 1;
		divsel = 0x41;
		phaseinc = 0x20;
	} else {
		/* The iCLK virtual clock root frequency is in MHz,
		 * but the crtc->mode.clock in in KHz. To get the divisors,
		 * it is necessary to divide one by another, so we
		 * convert the virtual clock precision to KHz here for higher
		 * precision.
		 */
		u32 iclk_virtual_root_freq = 172800 * 1000;
		u32 iclk_pi_range = 64;
		u32 desired_divisor, msb_divisor_value, pi_value;

		desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		msb_divisor_value = desired_divisor / iclk_pi_range;
		pi_value = desired_divisor % iclk_pi_range;

		auxdiv = 0;
		divsel = msb_divisor_value - 2;
		phaseinc = pi_value;
	}

	/* This should not happen with any sane values */
	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		~SBI_SSCDIVINTPHASE_INCVAL_MASK);

	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
			crtc->mode.clock,
			auxdiv,
			divsel,
			phasedir,
			phaseinc);

	/* Program SSCDIVINTPHASE6 */
3058
	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3059 3060 3061 3062 3063 3064
	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3065
	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3066 3067

	/* Program SSCAUXDIV */
3068
	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3069 3070
	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3071
	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3072 3073

	/* Enable modulator and associated divider */
3074
	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3075
	temp &= ~SBI_SSCCTL_DISABLE;
3076
	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3077 3078 3079 3080 3081

	/* Wait for initialization time */
	udelay(24);

	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3082 3083

	mutex_unlock(&dev_priv->dpio_lock);
3084 3085
}

3086 3087 3088 3089 3090 3091 3092 3093 3094
/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
3095 3096 3097 3098 3099
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
3100
	u32 reg, temp;
3101

3102 3103
	assert_transcoder_disabled(dev_priv, pipe);

3104 3105 3106 3107 3108
	/* Write the TU size bits before fdi link training, so that error
	 * detection works. */
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

3109
	/* For PCH output, training FDI link */
3110
	dev_priv->display.fdi_link_train(crtc);
3111

3112 3113 3114 3115 3116 3117 3118
	/* XXX: pch pll's can be enabled any time before we enable the PCH
	 * transcoder, and we actually should do this to not upset any PCH
	 * transcoder that already use the clock when we share it.
	 *
	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
	 * unconditionally resets the pll - we need that to have the right LVDS
	 * enable sequence. */
3119
	ironlake_enable_pch_pll(intel_crtc);
3120

3121
	if (HAS_PCH_CPT(dev)) {
3122
		u32 sel;
3123

3124
		temp = I915_READ(PCH_DPLL_SEL);
3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138
		switch (pipe) {
		default:
		case 0:
			temp |= TRANSA_DPLL_ENABLE;
			sel = TRANSA_DPLLB_SEL;
			break;
		case 1:
			temp |= TRANSB_DPLL_ENABLE;
			sel = TRANSB_DPLLB_SEL;
			break;
		case 2:
			temp |= TRANSC_DPLL_ENABLE;
			sel = TRANSC_DPLLB_SEL;
			break;
3139
		}
3140 3141 3142 3143
		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
			temp |= sel;
		else
			temp &= ~sel;
3144 3145
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3146

3147 3148
	/* set transcoder timing, panel must allow it */
	assert_panel_unlocked(dev_priv, pipe);
3149 3150 3151
	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3152

3153 3154 3155
	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3156
	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3157

3158
	intel_fdi_normal_train(crtc);
3159

3160 3161
	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
3162 3163
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3164
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3165 3166 3167
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
3168 3169
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
3170 3171
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
3172
		temp |= bpc << 9; /* same format but at 11:9 */
3173 3174

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3175
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3176
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3177
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3178 3179 3180

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
3181
			temp |= TRANS_DP_PORT_SEL_B;
3182 3183
			break;
		case PCH_DP_C:
3184
			temp |= TRANS_DP_PORT_SEL_C;
3185 3186
			break;
		case PCH_DP_D:
3187
			temp |= TRANS_DP_PORT_SEL_D;
3188 3189
			break;
		default:
3190
			BUG();
3191
		}
3192

3193
		I915_WRITE(reg, temp);
3194
	}
3195

3196
	ironlake_enable_pch_transcoder(dev_priv, pipe);
3197 3198
}

P
Paulo Zanoni 已提交
3199 3200 3201 3202 3203
static void lpt_pch_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3204
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
P
Paulo Zanoni 已提交
3205

3206
	assert_transcoder_disabled(dev_priv, TRANSCODER_A);
P
Paulo Zanoni 已提交
3207

3208
	lpt_program_iclkip(crtc);
P
Paulo Zanoni 已提交
3209

3210
	/* Set transcoder timing. */
3211 3212 3213
	I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
	I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
	I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
P
Paulo Zanoni 已提交
3214

3215 3216 3217 3218
	I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
	I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
P
Paulo Zanoni 已提交
3219

3220
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3221 3222
}

3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251
static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
{
	struct intel_pch_pll *pll = intel_crtc->pch_pll;

	if (pll == NULL)
		return;

	if (pll->refcount == 0) {
		WARN(1, "bad PCH PLL refcount\n");
		return;
	}

	--pll->refcount;
	intel_crtc->pch_pll = NULL;
}

static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
{
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll;
	int i;

	pll = intel_crtc->pch_pll;
	if (pll) {
		DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);
		goto prepare;
	}

3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
	if (HAS_PCH_IBX(dev_priv->dev)) {
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		i = intel_crtc->pipe;
		pll = &dev_priv->pch_plls[i];

		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);

		goto found;
	}

3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];

		/* Only want to check enabled timings first */
		if (pll->refcount == 0)
			continue;

		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		    fp == I915_READ(pll->fp0_reg)) {
			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
				      intel_crtc->base.base.id,
				      pll->pll_reg, pll->refcount, pll->active);

			goto found;
		}
	}

	/* Ok no matching timings, maybe there's a free one? */
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];
		if (pll->refcount == 0) {
			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
				      intel_crtc->base.base.id, pll->pll_reg);
			goto found;
		}
	}

	return NULL;

found:
	intel_crtc->pch_pll = pll;
	pll->refcount++;
	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
prepare: /* separate function? */
	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);

3299 3300
	/* Wait for the clocks to stabilize before rewriting the regs */
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3301 3302
	POSTING_READ(pll->pll_reg);
	udelay(150);
3303 3304 3305

	I915_WRITE(pll->fp0_reg, fp);
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3306 3307 3308 3309
	pll->on = false;
	return pll;
}

3310 3311 3312
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3313
	int dslreg = PIPEDSL(pipe);
3314 3315 3316 3317 3318 3319 3320 3321 3322 3323
	u32 temp;

	temp = I915_READ(dslreg);
	udelay(500);
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		if (wait_for(I915_READ(dslreg) != temp, 5))
			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
	}
}

3324 3325 3326 3327 3328
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329
	struct intel_encoder *encoder;
3330 3331 3332 3333
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 temp;

3334 3335
	WARN_ON(!crtc->enabled);

3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if ((temp & LVDS_PORT_EN) == 0)
			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
	}


3349
	if (intel_crtc->config.has_pch_encoder) {
3350 3351 3352
		/* Note: FDI PLL enabling _must_ be done before we enable the
		 * cpu pipes, hence this is separate from all the other fdi/pch
		 * enabling. */
3353
		ironlake_fdi_pll_enable(intel_crtc);
3354 3355 3356 3357
	} else {
		assert_fdi_tx_disabled(dev_priv, pipe);
		assert_fdi_rx_disabled(dev_priv, pipe);
	}
3358

3359 3360 3361
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);
3362 3363 3364

	/* Enable panel fitting for LVDS */
	if (dev_priv->pch_pf_size &&
3365 3366
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3367 3368 3369 3370
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
3371 3372 3373 3374 3375
		if (IS_IVYBRIDGE(dev))
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
						 PF_PIPE_SEL_IVB(pipe));
		else
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3376 3377
		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3378 3379
	}

3380 3381 3382 3383 3384 3385
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3386 3387
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3388 3389
	intel_enable_plane(dev_priv, plane, pipe);

3390
	if (intel_crtc->config.has_pch_encoder)
3391
		ironlake_pch_enable(crtc);
3392

3393
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3394
	intel_update_fbc(dev);
3395 3396
	mutex_unlock(&dev->struct_mutex);

3397
	intel_crtc_update_cursor(crtc, true);
3398

3399 3400
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3401 3402 3403

	if (HAS_PCH_CPT(dev))
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3404 3405 3406 3407 3408 3409 3410 3411 3412 3413

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
3414 3415
}

3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	WARN_ON(!crtc->enabled);

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

3433
	if (intel_crtc->config.has_pch_encoder)
3434
		dev_priv->display.fdi_link_train(crtc);
3435 3436 3437 3438 3439

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3440
	intel_ddi_enable_pipe_clock(intel_crtc);
3441

3442
	/* Enable panel fitting for eDP */
3443 3444
	if (dev_priv->pch_pf_size &&
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3445 3446 3447 3448
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
3449 3450
		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
					 PF_PIPE_SEL_IVB(pipe));
3451 3452 3453 3454 3455 3456 3457 3458 3459 3460
		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
	}

	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3461
	intel_ddi_set_pipe_settings(crtc);
3462
	intel_ddi_enable_transcoder_func(crtc);
3463

3464 3465
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3466 3467
	intel_enable_plane(dev_priv, plane, pipe);

3468
	if (intel_crtc->config.has_pch_encoder)
P
Paulo Zanoni 已提交
3469
		lpt_pch_enable(crtc);
3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	intel_crtc_update_cursor(crtc, true);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
}

3491 3492 3493 3494 3495
static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496
	struct intel_encoder *encoder;
3497 3498
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3499
	u32 reg, temp;
3500

3501

3502 3503 3504
	if (!intel_crtc->active)
		return;

3505 3506 3507
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3508
	intel_crtc_wait_for_pending_flips(crtc);
3509
	drm_vblank_off(dev, pipe);
3510
	intel_crtc_update_cursor(crtc, false);
3511

3512
	intel_disable_plane(dev_priv, plane, pipe);
3513

3514 3515
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
3516

3517
	intel_disable_pipe(dev_priv, pipe);
3518

3519
	/* Disable PF */
3520 3521
	I915_WRITE(PF_CTL(pipe), 0);
	I915_WRITE(PF_WIN_SZ(pipe), 0);
3522

3523 3524 3525
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);
3526

3527
	ironlake_fdi_disable(crtc);
3528

3529
	ironlake_disable_pch_transcoder(dev_priv, pipe);
3530

3531 3532
	if (HAS_PCH_CPT(dev)) {
		/* disable TRANS_DP_CTL */
3533 3534 3535
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3536
		temp |= TRANS_DP_PORT_SEL_NONE;
3537
		I915_WRITE(reg, temp);
3538 3539 3540

		/* disable DPLL_SEL */
		temp = I915_READ(PCH_DPLL_SEL);
3541 3542
		switch (pipe) {
		case 0:
3543
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3544 3545
			break;
		case 1:
3546
			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3547 3548
			break;
		case 2:
3549
			/* C shares PLL A or B */
3550
			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3551 3552 3553 3554
			break;
		default:
			BUG(); /* wtf */
		}
3555 3556
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3557

3558
	/* disable PCH DPLL */
3559
	intel_disable_pch_pll(intel_crtc);
3560

3561
	ironlake_fdi_pll_disable(intel_crtc);
3562

3563
	intel_crtc->active = false;
3564
	intel_update_watermarks(dev);
3565 3566

	mutex_lock(&dev->struct_mutex);
3567
	intel_update_fbc(dev);
3568
	mutex_unlock(&dev->struct_mutex);
3569
}
3570

3571
static void haswell_crtc_disable(struct drm_crtc *crtc)
3572
{
3573 3574
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3575
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576 3577 3578
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3579
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3580

3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597
	if (!intel_crtc->active)
		return;

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
	intel_crtc_update_cursor(crtc, false);

	intel_disable_plane(dev_priv, plane, pipe);

	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);

	intel_disable_pipe(dev_priv, pipe);

3598
	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3599 3600 3601 3602 3603

	/* Disable PF */
	I915_WRITE(PF_CTL(pipe), 0);
	I915_WRITE(PF_WIN_SZ(pipe), 0);

3604
	intel_ddi_disable_pipe_clock(intel_crtc);
3605 3606 3607 3608 3609

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3610
	if (intel_crtc->config.has_pch_encoder) {
3611
		lpt_disable_pch_transcoder(dev_priv);
3612
		intel_ddi_fdi_disable(crtc);
3613
	}
3614 3615 3616 3617 3618 3619 3620 3621 3622

	intel_crtc->active = false;
	intel_update_watermarks(dev);

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);
}

3623 3624 3625 3626 3627 3628
static void ironlake_crtc_off(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	intel_put_pch_pll(intel_crtc);
}

3629 3630
static void haswell_crtc_off(struct drm_crtc *crtc)
{
P
Paulo Zanoni 已提交
3631 3632 3633 3634
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
	 * start using it. */
D
Daniel Vetter 已提交
3635
	intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
P
Paulo Zanoni 已提交
3636

3637 3638 3639
	intel_ddi_put_crtc_pll(crtc);
}

3640 3641 3642
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
3643
		struct drm_device *dev = intel_crtc->base.dev;
3644
		struct drm_i915_private *dev_priv = dev->dev_private;
3645

3646
		mutex_lock(&dev->struct_mutex);
3647 3648 3649
		dev_priv->mm.interruptible = false;
		(void) intel_overlay_switch_off(intel_crtc->overlay);
		dev_priv->mm.interruptible = true;
3650
		mutex_unlock(&dev->struct_mutex);
3651 3652
	}

3653 3654 3655
	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
3656 3657
}

3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681
/**
 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
 * cursor plane briefly if not already running after enabling the display
 * plane.
 * This workaround avoids occasional blank screens when self refresh is
 * enabled.
 */
static void
g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	u32 cntl = I915_READ(CURCNTR(pipe));

	if ((cntl & CURSOR_MODE) == 0) {
		u32 fw_bcl_self = I915_READ(FW_BLC_SELF);

		I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		intel_wait_for_vblank(dev_priv->dev, pipe);
		I915_WRITE(CURCNTR(pipe), cntl);
		I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		I915_WRITE(FW_BLC_SELF, fw_bcl_self);
	}
}

3682
static void i9xx_crtc_enable(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3683 3684 3685 3686
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3687
	struct intel_encoder *encoder;
J
Jesse Barnes 已提交
3688
	int pipe = intel_crtc->pipe;
3689
	int plane = intel_crtc->plane;
J
Jesse Barnes 已提交
3690

3691 3692
	WARN_ON(!crtc->enabled);

3693 3694 3695 3696
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3697 3698
	intel_update_watermarks(dev);

3699
	intel_enable_pll(dev_priv, pipe);
3700 3701 3702 3703 3704

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3705
	intel_enable_pipe(dev_priv, pipe, false);
3706
	intel_enable_plane(dev_priv, plane, pipe);
3707 3708
	if (IS_G4X(dev))
		g4x_fixup_plane(dev_priv, pipe);
J
Jesse Barnes 已提交
3709

3710
	intel_crtc_load_lut(crtc);
C
Chris Wilson 已提交
3711
	intel_update_fbc(dev);
J
Jesse Barnes 已提交
3712

3713 3714
	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
3715
	intel_crtc_update_cursor(crtc, true);
3716

3717 3718
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3719
}
J
Jesse Barnes 已提交
3720

3721 3722 3723 3724 3725
static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726
	struct intel_encoder *encoder;
3727 3728
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3729
	u32 pctl;
3730

3731

3732 3733 3734
	if (!intel_crtc->active)
		return;

3735 3736 3737
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3738
	/* Give the overlay scaler a chance to disable if it's on this pipe */
3739 3740
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
3741
	intel_crtc_dpms_overlay(intel_crtc, false);
3742
	intel_crtc_update_cursor(crtc, false);
3743

3744 3745
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
J
Jesse Barnes 已提交
3746

3747 3748
	intel_disable_plane(dev_priv, plane, pipe);
	intel_disable_pipe(dev_priv, pipe);
3749 3750 3751 3752 3753 3754 3755

	/* Disable pannel fitter if it is on this pipe. */
	pctl = I915_READ(PFIT_CONTROL);
	if ((pctl & PFIT_ENABLE) &&
	    ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
		I915_WRITE(PFIT_CONTROL, 0);

3756
	intel_disable_pll(dev_priv, pipe);
3757

3758
	intel_crtc->active = false;
3759 3760
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
3761 3762
}

3763 3764 3765 3766
static void i9xx_crtc_off(struct drm_crtc *crtc)
{
}

3767 3768
static void intel_crtc_update_sarea(struct drm_crtc *crtc,
				    bool enabled)
3769 3770 3771 3772 3773
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
J
Jesse Barnes 已提交
3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
3792
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
J
Jesse Barnes 已提交
3793 3794 3795 3796
		break;
	}
}

3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817
/**
 * Sets the power management mode of the pipe and plane.
 */
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	bool enable = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		enable |= intel_encoder->connectors_active;

	if (enable)
		dev_priv->display.crtc_enable(crtc);
	else
		dev_priv->display.crtc_disable(crtc);

	intel_crtc_update_sarea(crtc, enable);
}

3818 3819 3820
static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
3821
	struct drm_connector *connector;
3822
	struct drm_i915_private *dev_priv = dev->dev_private;
3823
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3824

3825 3826 3827
	/* crtc should still be enabled when we disable it. */
	WARN_ON(!crtc->enabled);

3828
	intel_crtc->eld_vld = false;
3829 3830
	dev_priv->display.crtc_disable(crtc);
	intel_crtc_update_sarea(crtc, false);
3831 3832
	dev_priv->display.off(crtc);

3833 3834
	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3835 3836 3837

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
3838
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3839
		mutex_unlock(&dev->struct_mutex);
3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852
		crtc->fb = NULL;
	}

	/* Update computed state. */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		if (connector->encoder->crtc != crtc)
			continue;

		connector->dpms = DRM_MODE_DPMS_OFF;
		to_intel_encoder(connector->encoder)->connectors_active = false;
3853 3854 3855
	}
}

3856
void intel_modeset_disable(struct drm_device *dev)
J
Jesse Barnes 已提交
3857
{
3858 3859 3860 3861 3862 3863
	struct drm_crtc *crtc;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (crtc->enabled)
			intel_crtc_disable(crtc);
	}
J
Jesse Barnes 已提交
3864 3865
}

C
Chris Wilson 已提交
3866
void intel_encoder_destroy(struct drm_encoder *encoder)
3867
{
3868
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
C
Chris Wilson 已提交
3869 3870 3871

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
3872 3873
}

3874 3875 3876 3877
/* Simple dpms helper for encodres with just one connector, no cloning and only
 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
 * state of the entire output pipe. */
void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3878
{
3879 3880 3881
	if (mode == DRM_MODE_DPMS_ON) {
		encoder->connectors_active = true;

3882
		intel_crtc_update_dpms(encoder->base.crtc);
3883 3884 3885
	} else {
		encoder->connectors_active = false;

3886
		intel_crtc_update_dpms(encoder->base.crtc);
3887
	}
J
Jesse Barnes 已提交
3888 3889
}

3890 3891
/* Cross check the actual hw state with our own modeset state tracking (and it's
 * internal consistency). */
3892
static void intel_connector_check_state(struct intel_connector *connector)
J
Jesse Barnes 已提交
3893
{
3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922
	if (connector->get_hw_state(connector)) {
		struct intel_encoder *encoder = connector->encoder;
		struct drm_crtc *crtc;
		bool encoder_enabled;
		enum pipe pipe;

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base));

		WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		     "wrong connector dpms state\n");
		WARN(connector->base.encoder != &encoder->base,
		     "active connector not linked to encoder\n");
		WARN(!encoder->connectors_active,
		     "encoder->connectors_active not set\n");

		encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		WARN(!encoder_enabled, "encoder not enabled\n");
		if (WARN_ON(!encoder->base.crtc))
			return;

		crtc = encoder->base.crtc;

		WARN(!crtc->enabled, "crtc not enabled\n");
		WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		WARN(pipe != to_intel_crtc(crtc)->pipe,
		     "encoder active on the wrong pipe\n");
	}
J
Jesse Barnes 已提交
3923 3924
}

3925 3926 3927
/* Even simpler default implementation, if there's really no special case to
 * consider. */
void intel_connector_dpms(struct drm_connector *connector, int mode)
J
Jesse Barnes 已提交
3928
{
3929
	struct intel_encoder *encoder = intel_attached_encoder(connector);
3930

3931 3932 3933
	/* All the simple cases only support two dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;
3934

3935 3936 3937 3938 3939 3940 3941 3942 3943
	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	if (encoder->base.crtc)
		intel_encoder_dpms(encoder, mode);
	else
3944
		WARN_ON(encoder->connectors_active != false);
3945

3946
	intel_modeset_check_state(connector->dev);
J
Jesse Barnes 已提交
3947 3948
}

3949 3950 3951 3952
/* Simple connector->get_hw_state implementation for encoders that support only
 * one connector and no cloning and hence the encoder state determines the state
 * of the connector. */
bool intel_connector_get_hw_state(struct intel_connector *connector)
C
Chris Wilson 已提交
3953
{
3954
	enum pipe pipe = 0;
3955
	struct intel_encoder *encoder = connector->encoder;
C
Chris Wilson 已提交
3956

3957
	return encoder->get_hw_state(encoder, &pipe);
C
Chris Wilson 已提交
3958 3959
}

3960 3961
static bool intel_crtc_compute_config(struct drm_crtc *crtc,
				      struct intel_crtc_config *pipe_config)
J
Jesse Barnes 已提交
3962
{
3963
	struct drm_device *dev = crtc->dev;
3964
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3965

3966
	if (HAS_PCH_SPLIT(dev)) {
3967
		/* FDI link clock is fixed at 2.7G */
3968 3969
		if (pipe_config->requested_mode.clock * 3
		    > IRONLAKE_FDI_FREQ * 4)
J
Jesse Barnes 已提交
3970
			return false;
3971
	}
3972

3973 3974 3975
	/* All interlaced capable intel hw wants timings in frames. Note though
	 * that intel_lvds_mode_fixup does some funny tricks with the crtc
	 * timings, so we need to be careful not to clobber these.*/
3976
	if (!pipe_config->timings_set)
3977
		drm_mode_set_crtcinfo(adjusted_mode, 0);
3978

3979 3980 3981 3982 3983 3984 3985
	/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
	 * with a hsync front porch of 0.
	 */
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
		adjusted_mode->hsync_start == adjusted_mode->hdisplay)
		return false;

3986 3987 3988 3989 3990 3991 3992 3993
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
		pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
		/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		 * for lvds. */
		pipe_config->pipe_bpp = 8*3;
	}

J
Jesse Barnes 已提交
3994 3995 3996
	return true;
}

J
Jesse Barnes 已提交
3997 3998 3999 4000 4001
static int valleyview_get_display_clock_speed(struct drm_device *dev)
{
	return 400000; /* FIXME */
}

4002 4003 4004 4005
static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}
J
Jesse Barnes 已提交
4006

4007
static int i915_get_display_clock_speed(struct drm_device *dev)
J
Jesse Barnes 已提交
4008
{
4009 4010
	return 333000;
}
J
Jesse Barnes 已提交
4011

4012 4013 4014 4015
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}
J
Jesse Barnes 已提交
4016

4017 4018 4019
static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;
J
Jesse Barnes 已提交
4020

4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
J
Jesse Barnes 已提交
4032
		}
4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
J
Jesse Barnes 已提交
4054
		return 133000;
4055
	}
J
Jesse Barnes 已提交
4056

4057 4058 4059
	/* Shouldn't happen */
	return 0;
}
J
Jesse Barnes 已提交
4060

4061 4062 4063
static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
J
Jesse Barnes 已提交
4064 4065
}

4066
static void
4067
intel_reduce_ratio(uint32_t *num, uint32_t *den)
4068 4069 4070 4071 4072 4073 4074
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

4075 4076 4077 4078
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		       int pixel_clock, int link_clock,
		       struct intel_link_m_n *m_n)
4079
{
4080
	m_n->tu = 64;
4081 4082
	m_n->gmch_m = bits_per_pixel * pixel_clock;
	m_n->gmch_n = link_clock * nlanes * 8;
4083
	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4084 4085
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
4086
	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4087 4088
}

4089 4090
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
4091 4092 4093
	if (i915_panel_use_ssc >= 0)
		return i915_panel_use_ssc != 0;
	return dev_priv->lvds_use_ssc
4094
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4095 4096
}

4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118
static int vlv_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk = 27000; /* for DP & HDMI */

	return 100000; /* only one validated so far */

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if (intel_panel_use_ssc(dev_priv))
			refclk = 100000;
		else
			refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		refclk = 100000;
	}

	return refclk;
}

4119 4120 4121 4122 4123 4124
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk;

4125 4126 4127
	if (IS_VALLEYVIEW(dev)) {
		refclk = vlv_get_refclk(crtc);
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		refclk = dev_priv->lvds_ssc_freq * 1000;
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
	} else {
		refclk = 48000;
	}

	return refclk;
}

4141
static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4142
{
4143 4144 4145
	unsigned dotclock = crtc->config.adjusted_mode.clock;
	struct dpll *clock = &crtc->config.dpll;

4146 4147
	/* SDVO TV has fixed PLL values depend on its clock range,
	   this mirrors vbios setting. */
4148
	if (dotclock >= 100000 && dotclock < 140500) {
4149 4150 4151 4152 4153
		clock->p1 = 2;
		clock->p2 = 10;
		clock->n = 3;
		clock->m1 = 16;
		clock->m2 = 8;
4154
	} else if (dotclock >= 140500 && dotclock <= 200000) {
4155 4156 4157 4158 4159 4160
		clock->p1 = 1;
		clock->p2 = 10;
		clock->n = 6;
		clock->m1 = 12;
		clock->m2 = 8;
	}
4161 4162

	crtc->config.clock_set = true;
4163 4164
}

4165
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4166 4167
				     intel_clock_t *reduced_clock)
{
4168
	struct drm_device *dev = crtc->base.dev;
4169
	struct drm_i915_private *dev_priv = dev->dev_private;
4170
	int pipe = crtc->pipe;
4171
	u32 fp, fp2 = 0;
4172
	struct dpll *clock = &crtc->config.dpll;
4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187

	if (IS_PINEVIEW(dev)) {
		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = (1 << reduced_clock->n) << 16 |
				reduced_clock->m1 << 8 | reduced_clock->m2;
	} else {
		fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
				reduced_clock->m2;
	}

	I915_WRITE(FP0(pipe), fp);

4188 4189
	crtc->lowfreq_avail = false;
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4190 4191
	    reduced_clock && i915_powersave) {
		I915_WRITE(FP1(pipe), fp2);
4192
		crtc->lowfreq_avail = true;
4193 4194 4195 4196 4197
	} else {
		I915_WRITE(FP1(pipe), fp);
	}
}

4198 4199 4200 4201 4202 4203 4204 4205
static void intel_dp_set_m_n(struct intel_crtc *crtc)
{
	if (crtc->config.has_pch_encoder)
		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
	else
		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}

4206
static void vlv_update_pll(struct intel_crtc *crtc)
4207
{
4208
	struct drm_device *dev = crtc->base.dev;
4209
	struct drm_i915_private *dev_priv = dev->dev_private;
4210
	int pipe = crtc->pipe;
4211 4212
	u32 dpll, mdiv, pdiv;
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4213 4214
	bool is_sdvo;
	u32 temp;
4215

4216 4217
	mutex_lock(&dev_priv->dpio_lock);

4218 4219
	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4220

4221 4222 4223 4224 4225 4226 4227
	dpll = DPLL_VGA_MODE_DIS;
	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
	dpll |= DPLL_INTEGRATED_CLOCK_VLV;

	I915_WRITE(DPLL(pipe), dpll);
	POSTING_READ(DPLL(pipe));
4228

4229 4230 4231 4232 4233
	bestn = crtc->config.dpll.n;
	bestm1 = crtc->config.dpll.m1;
	bestm2 = crtc->config.dpll.m2;
	bestp1 = crtc->config.dpll.p1;
	bestp2 = crtc->config.dpll.p2;
4234

4235 4236 4237 4238
	/*
	 * In Valleyview PLL and program lane counter registers are exposed
	 * through DPIO interface
	 */
4239 4240 4241 4242 4243 4244 4245 4246 4247 4248
	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
	mdiv |= ((bestn << DPIO_N_SHIFT));
	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
	mdiv |= (1 << DPIO_K_SHIFT);
	mdiv |= DPIO_ENABLE_CALIBRATION;
	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);

	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);

4249
	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4250
		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4251 4252
		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
4253 4254
	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);

4255
	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4256 4257 4258 4259 4260 4261 4262

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll);
	POSTING_READ(DPLL(pipe));
	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		DRM_ERROR("DPLL %d failed to lock\n", pipe);

4263 4264
	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);

4265 4266
	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4267 4268 4269 4270 4271 4272

	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);
4273

4274 4275
	temp = 0;
	if (is_sdvo) {
4276
		temp = 0;
4277 4278
		if (crtc->config.pixel_multiplier > 1) {
			temp = (crtc->config.pixel_multiplier - 1)
4279 4280
				<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
		}
4281
	}
4282 4283
	I915_WRITE(DPLL_MD(pipe), temp);
	POSTING_READ(DPLL_MD(pipe));
4284

4285
	/* Now program lane control registers */
4286 4287
	if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
	   || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4288 4289 4290 4291 4292
		temp = 0x1000C4;
		if(pipe == 1)
			temp |= (1 << 21);
		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
	}
4293 4294

	if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4295 4296 4297 4298 4299
		temp = 0x1000C4;
		if(pipe == 1)
			temp |= (1 << 21);
		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
	}
4300 4301

	mutex_unlock(&dev_priv->dpio_lock);
4302 4303
}

4304 4305
static void i9xx_update_pll(struct intel_crtc *crtc,
			    intel_clock_t *reduced_clock,
4306 4307
			    int num_connectors)
{
4308
	struct drm_device *dev = crtc->base.dev;
4309
	struct drm_i915_private *dev_priv = dev->dev_private;
4310
	struct intel_encoder *encoder;
4311
	int pipe = crtc->pipe;
4312 4313
	u32 dpll;
	bool is_sdvo;
4314
	struct dpll *clock = &crtc->config.dpll;
4315

4316
	i9xx_update_pll_dividers(crtc, reduced_clock);
4317

4318 4319
	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4320 4321 4322

	dpll = DPLL_VGA_MODE_DIS;

4323
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4324 4325 4326
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
4327

4328
	if (is_sdvo) {
4329
		if ((crtc->config.pixel_multiplier > 1) &&
4330
		    (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4331
			dpll |= (crtc->config.pixel_multiplier - 1)
4332
				<< SDVO_MULTIPLIER_SHIFT_HIRES;
4333 4334 4335
		}
		dpll |= DPLL_DVO_HIGH_SPEED;
	}
4336
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363
		dpll |= DPLL_DVO_HIGH_SPEED;

	/* compute bitmask from p1 value */
	if (IS_PINEVIEW(dev))
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
	else {
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (IS_G4X(dev) && reduced_clock)
			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
	}
	switch (clock->p2) {
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
	}
	if (INTEL_INFO(dev)->gen >= 4)
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

4364
	if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4365
		dpll |= PLL_REF_INPUT_TVCLKINBC;
4366
	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4367 4368 4369
		/* XXX: just matching BIOS for now */
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
		dpll |= 3;
4370
	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4371 4372 4373 4374 4375 4376 4377 4378 4379 4380
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

4381
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4382 4383
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
4384

4385 4386
	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4387 4388 4389 4390 4391 4392 4393 4394 4395 4396

	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

	if (INTEL_INFO(dev)->gen >= 4) {
		u32 temp = 0;
		if (is_sdvo) {
4397
			temp = 0;
4398 4399
			if (crtc->config.pixel_multiplier > 1) {
				temp = (crtc->config.pixel_multiplier - 1)
4400 4401
					<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
			}
4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413
		}
		I915_WRITE(DPLL_MD(pipe), temp);
	} else {
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
		I915_WRITE(DPLL(pipe), dpll);
	}
}

4414
static void i8xx_update_pll(struct intel_crtc *crtc,
4415
			    struct drm_display_mode *adjusted_mode,
4416
			    intel_clock_t *reduced_clock,
4417 4418
			    int num_connectors)
{
4419
	struct drm_device *dev = crtc->base.dev;
4420
	struct drm_i915_private *dev_priv = dev->dev_private;
4421
	struct intel_encoder *encoder;
4422
	int pipe = crtc->pipe;
4423
	u32 dpll;
4424
	struct dpll *clock = &crtc->config.dpll;
4425

4426
	i9xx_update_pll_dividers(crtc, reduced_clock);
4427

4428 4429
	dpll = DPLL_VGA_MODE_DIS;

4430
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4431 4432 4433 4434 4435 4436 4437 4438 4439 4440
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
	} else {
		if (clock->p1 == 2)
			dpll |= PLL_P1_DIVIDE_BY_TWO;
		else
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (clock->p2 == 4)
			dpll |= PLL_P2_DIVIDE_BY_4;
	}

4441
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4442 4443 4444 4445 4446 4447 4448 4449 4450 4451
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

4452
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4453 4454
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
4455

4456 4457 4458 4459 4460 4461
	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

4462 4463 4464 4465 4466 4467 4468 4469
	/* The pixel multiplier can only be updated once the
	 * DPLL is enabled and the clocks are stable.
	 *
	 * So write it again.
	 */
	I915_WRITE(DPLL(pipe), dpll);
}

4470 4471 4472 4473 4474 4475 4476
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_crtc->pipe;
4477
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490
	uint32_t vsyncshift;

	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		/* the chip adds 2 halflines automatically */
		adjusted_mode->crtc_vtotal -= 1;
		adjusted_mode->crtc_vblank_end -= 1;
		vsyncshift = adjusted_mode->crtc_hsync_start
			     - adjusted_mode->crtc_htotal / 2;
	} else {
		vsyncshift = 0;
	}

	if (INTEL_INFO(dev)->gen > 3)
4491
		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4492

4493
	I915_WRITE(HTOTAL(cpu_transcoder),
4494 4495
		   (adjusted_mode->crtc_hdisplay - 1) |
		   ((adjusted_mode->crtc_htotal - 1) << 16));
4496
	I915_WRITE(HBLANK(cpu_transcoder),
4497 4498
		   (adjusted_mode->crtc_hblank_start - 1) |
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
4499
	I915_WRITE(HSYNC(cpu_transcoder),
4500 4501 4502
		   (adjusted_mode->crtc_hsync_start - 1) |
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));

4503
	I915_WRITE(VTOTAL(cpu_transcoder),
4504 4505
		   (adjusted_mode->crtc_vdisplay - 1) |
		   ((adjusted_mode->crtc_vtotal - 1) << 16));
4506
	I915_WRITE(VBLANK(cpu_transcoder),
4507 4508
		   (adjusted_mode->crtc_vblank_start - 1) |
		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
4509
	I915_WRITE(VSYNC(cpu_transcoder),
4510 4511 4512
		   (adjusted_mode->crtc_vsync_start - 1) |
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));

4513 4514 4515 4516 4517 4518 4519 4520
	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
	 * bits. */
	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
	    (pipe == PIPE_B || pipe == PIPE_C))
		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));

4521 4522 4523 4524 4525 4526 4527
	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
	 */
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
}

4528 4529
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
			      int x, int y,
4530
			      struct drm_framebuffer *fb)
J
Jesse Barnes 已提交
4531 4532 4533 4534
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4535 4536 4537
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
J
Jesse Barnes 已提交
4538
	int pipe = intel_crtc->pipe;
4539
	int plane = intel_crtc->plane;
4540
	int refclk, num_connectors = 0;
4541
	intel_clock_t clock, reduced_clock;
4542
	u32 dspcntr, pipeconf;
4543
	bool ok, has_reduced_clock = false, is_sdvo = false;
4544
	bool is_lvds = false, is_tv = false;
4545
	struct intel_encoder *encoder;
4546
	const intel_limit_t *limit;
4547
	int ret;
J
Jesse Barnes 已提交
4548

4549
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4550
		switch (encoder->type) {
J
Jesse Barnes 已提交
4551 4552 4553 4554
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
4555
		case INTEL_OUTPUT_HDMI:
J
Jesse Barnes 已提交
4556
			is_sdvo = true;
4557
			if (encoder->needs_tv_clock)
4558
				is_tv = true;
J
Jesse Barnes 已提交
4559 4560 4561 4562 4563
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		}
4564

4565
		num_connectors++;
J
Jesse Barnes 已提交
4566 4567
	}

4568
	refclk = i9xx_get_refclk(crtc, num_connectors);
J
Jesse Barnes 已提交
4569

4570 4571 4572 4573 4574
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
4575
	limit = intel_limit(crtc, refclk);
4576 4577
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			     &clock);
J
Jesse Barnes 已提交
4578 4579
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
4580
		return -EINVAL;
J
Jesse Barnes 已提交
4581 4582
	}

4583
	/* Ensure that the cursor is valid for the new mode before changing... */
4584
	intel_crtc_update_cursor(crtc, true);
4585

4586
	if (is_lvds && dev_priv->lvds_downclock_avail) {
4587 4588 4589 4590 4591 4592
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
4593
		has_reduced_clock = limit->find_pll(limit, crtc,
4594 4595
						    dev_priv->lvds_downclock,
						    refclk,
4596
						    &clock,
4597
						    &reduced_clock);
Z
Zhenyu Wang 已提交
4598
	}
4599 4600 4601 4602 4603 4604 4605 4606
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
Z
Zhenyu Wang 已提交
4607

4608
	if (is_sdvo && is_tv)
4609
		i9xx_adjust_sdvo_tv_clock(intel_crtc);
Z
Zhenyu Wang 已提交
4610

4611
	if (IS_GEN2(dev))
4612
		i8xx_update_pll(intel_crtc, adjusted_mode,
4613 4614
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4615
	else if (IS_VALLEYVIEW(dev))
4616
		vlv_update_pll(intel_crtc);
J
Jesse Barnes 已提交
4617
	else
4618
		i9xx_update_pll(intel_crtc,
4619 4620
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
J
Jesse Barnes 已提交
4621 4622

	/* setup pipeconf */
4623
	pipeconf = I915_READ(PIPECONF(pipe));
J
Jesse Barnes 已提交
4624 4625 4626 4627

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

4628 4629 4630 4631 4632 4633
	if (!IS_VALLEYVIEW(dev)) {
		if (pipe == 0)
			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		else
			dspcntr |= DISPPLANE_SEL_PIPE_B;
	}
J
Jesse Barnes 已提交
4634

4635
	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
J
Jesse Barnes 已提交
4636 4637 4638 4639 4640 4641
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
4642 4643
		if (mode->clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4644
			pipeconf |= PIPECONF_DOUBLE_WIDE;
J
Jesse Barnes 已提交
4645
		else
4646
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
J
Jesse Barnes 已提交
4647 4648
	}

4649
	/* default to 8bpc */
4650
	pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4651
	if (intel_crtc->config.has_dp_encoder) {
4652
		if (intel_crtc->config.dither) {
4653
			pipeconf |= PIPECONF_6BPC |
4654 4655 4656 4657 4658
				    PIPECONF_DITHER_EN |
				    PIPECONF_DITHER_TYPE_SP;
		}
	}

4659
	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4660
		if (intel_crtc->config.dither) {
4661
			pipeconf |= PIPECONF_6BPC |
4662 4663 4664 4665 4666
					PIPECONF_ENABLE |
					I965_PIPECONF_ACTIVE;
		}
	}

4667
	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
J
Jesse Barnes 已提交
4668 4669
	drm_mode_debug_printmodeline(mode);

4670 4671
	if (HAS_PIPE_CXSR(dev)) {
		if (intel_crtc->lowfreq_avail) {
4672
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4673
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4674
		} else {
4675
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4676 4677 4678 4679
			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		}
	}

4680
	pipeconf &= ~PIPECONF_INTERLACE_MASK;
4681
	if (!IS_GEN2(dev) &&
4682
	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4683
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4684
	else
4685
		pipeconf |= PIPECONF_PROGRESSIVE;
4686

4687
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4688 4689 4690

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
J
Jesse Barnes 已提交
4691
	 */
4692 4693 4694 4695
	I915_WRITE(DSPSIZE(plane),
		   ((mode->vdisplay - 1) << 16) |
		   (mode->hdisplay - 1));
	I915_WRITE(DSPPOS(plane), 0);
4696

4697 4698
	I915_WRITE(PIPECONF(pipe), pipeconf);
	POSTING_READ(PIPECONF(pipe));
4699
	intel_enable_pipe(dev_priv, pipe, false);
4700 4701 4702 4703 4704 4705

	intel_wait_for_vblank(dev, pipe);

	I915_WRITE(DSPCNTR(plane), dspcntr);
	POSTING_READ(DSPCNTR(plane));

4706
	ret = intel_pipe_set_base(crtc, x, y, fb);
4707 4708 4709 4710 4711 4712

	intel_update_watermarks(dev);

	return ret;
}

4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

	return true;
}

P
Paulo Zanoni 已提交
4727
static void ironlake_init_pch_refclk(struct drm_device *dev)
4728 4729 4730 4731
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
4732
	u32 val, final;
4733
	bool has_lvds = false;
4734 4735 4736
	bool has_cpu_edp = false;
	bool has_pch_edp = false;
	bool has_panel = false;
4737 4738
	bool has_ck505 = false;
	bool can_ssc = false;
4739 4740

	/* We need to take the global config into account */
4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754
	list_for_each_entry(encoder, &mode_config->encoder_list,
			    base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			has_panel = true;
			has_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_panel = true;
			if (intel_encoder_is_pch_edp(&encoder->base))
				has_pch_edp = true;
			else
				has_cpu_edp = true;
			break;
4755 4756 4757
		}
	}

4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768
	if (HAS_PCH_IBX(dev)) {
		has_ck505 = dev_priv->display_clock_mode;
		can_ssc = has_ck505;
	} else {
		has_ck505 = false;
		can_ssc = true;
	}

	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		      has_ck505);
4769 4770 4771 4772 4773 4774

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812
	val = I915_READ(PCH_DREF_CONTROL);

	/* As we must carefully and slowly disable/enable each source in turn,
	 * compute the final state we want first and check if we need to
	 * make any changes at all.
	 */
	final = val;
	final &= ~DREF_NONSPREAD_SOURCE_MASK;
	if (has_ck505)
		final |= DREF_NONSPREAD_CK505_ENABLE;
	else
		final |= DREF_NONSPREAD_SOURCE_ENABLE;

	final &= ~DREF_SSC_SOURCE_MASK;
	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
	final &= ~DREF_SSC1_ENABLE;

	if (has_panel) {
		final |= DREF_SSC_SOURCE_ENABLE;

		if (intel_panel_use_ssc(dev_priv) && can_ssc)
			final |= DREF_SSC1_ENABLE;

		if (has_cpu_edp) {
			if (intel_panel_use_ssc(dev_priv) && can_ssc)
				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
			else
				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		} else
			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	} else {
		final |= DREF_SSC_SOURCE_DISABLE;
		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	}

	if (final == val)
		return;

4813
	/* Always enable nonspread source */
4814
	val &= ~DREF_NONSPREAD_SOURCE_MASK;
4815

4816
	if (has_ck505)
4817
		val |= DREF_NONSPREAD_CK505_ENABLE;
4818
	else
4819
		val |= DREF_NONSPREAD_SOURCE_ENABLE;
4820

4821
	if (has_panel) {
4822 4823
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_ENABLE;
4824

4825
		/* SSC must be turned on before enabling the CPU output  */
4826
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4827
			DRM_DEBUG_KMS("Using SSC on panel\n");
4828
			val |= DREF_SSC1_ENABLE;
4829
		} else
4830
			val &= ~DREF_SSC1_ENABLE;
4831 4832

		/* Get SSC going before enabling the outputs */
4833
		I915_WRITE(PCH_DREF_CONTROL, val);
4834 4835 4836
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

4837
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4838 4839

		/* Enable CPU source on CPU attached eDP */
4840
		if (has_cpu_edp) {
4841
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4842
				DRM_DEBUG_KMS("Using SSC on eDP\n");
4843
				val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4844
			}
4845
			else
4846
				val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4847
		} else
4848
			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4849

4850
		I915_WRITE(PCH_DREF_CONTROL, val);
4851 4852 4853 4854 4855
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	} else {
		DRM_DEBUG_KMS("Disabling SSC entirely\n");

4856
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4857 4858

		/* Turn off CPU output */
4859
		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4860

4861
		I915_WRITE(PCH_DREF_CONTROL, val);
4862 4863 4864 4865
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		/* Turn off the SSC source */
4866 4867
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_DISABLE;
4868 4869

		/* Turn off SSC1 */
4870
		val &= ~DREF_SSC1_ENABLE;
4871

4872
		I915_WRITE(PCH_DREF_CONTROL, val);
4873 4874 4875
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	}
4876 4877

	BUG_ON(val != final);
4878 4879
}

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/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
static void lpt_init_pch_refclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	bool has_vga = false;
	bool is_sdv = false;
	u32 tmp;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_ANALOG:
			has_vga = true;
			break;
		}
	}

	if (!has_vga)
		return;

4901 4902
	mutex_lock(&dev_priv->dpio_lock);

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	/* XXX: Rip out SDV support once Haswell ships for real. */
	if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
		is_sdv = true;

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	tmp &= ~SBI_SSCCTL_DISABLE;
	tmp |= SBI_SSCCTL_PATHALT;
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	udelay(24);

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	tmp &= ~SBI_SSCCTL_PATHALT;
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	if (!is_sdv) {
		tmp = I915_READ(SOUTH_CHICKEN2);
		tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
		I915_WRITE(SOUTH_CHICKEN2, tmp);

		if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
				       FDI_MPHY_IOSFSB_RESET_STATUS, 100))
			DRM_ERROR("FDI mPHY reset assert timeout\n");

		tmp = I915_READ(SOUTH_CHICKEN2);
		tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		I915_WRITE(SOUTH_CHICKEN2, tmp);

		if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
				        FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
				       100))
			DRM_ERROR("FDI mPHY reset de-assert timeout\n");
	}

	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
	tmp &= ~(0xFF << 24);
	tmp |= (0x12 << 24);
	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);

	if (!is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
		tmp &= ~(0x3 << 6);
		tmp |= (1 << 6) | (1 << 0);
		intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
	}

	if (is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
		tmp |= 0x7FFF;
		intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);

	if (is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
		tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
		intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
		tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
		intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
		tmp |= (0x3F << 8);
		intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
		tmp |= (0x3F << 8);
		intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);

	if (!is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		tmp &= ~(7 << 13);
		tmp |= (5 << 13);
		intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		tmp &= ~(7 << 13);
		tmp |= (5 << 13);
		intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);

	if (!is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		tmp |= (1 << 27);
		intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		tmp |= (1 << 27);
		intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		tmp &= ~(0xF << 28);
		tmp |= (4 << 28);
		intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		tmp &= ~(0xF << 28);
		tmp |= (4 << 28);
		intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
	}

	/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
	tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
	tmp |= SBI_DBUFF0_ENABLE;
	intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5045 5046

	mutex_unlock(&dev_priv->dpio_lock);
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}

/*
 * Initialize reference clocks when the driver loads
 */
void intel_init_pch_refclk(struct drm_device *dev)
{
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		ironlake_init_pch_refclk(dev);
	else if (HAS_PCH_LPT(dev))
		lpt_init_pch_refclk(dev);
}

5060 5061 5062 5063 5064 5065 5066 5067 5068
static int ironlake_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_encoder *edp_encoder = NULL;
	int num_connectors = 0;
	bool is_lvds = false;

5069
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			edp_encoder = encoder;
			break;
		}
		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      dev_priv->lvds_ssc_freq);
		return dev_priv->lvds_ssc_freq * 1000;
	}

	return 120000;
}

5090
static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5091
				  struct drm_display_mode *adjusted_mode,
5092
				  bool dither)
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5093
{
5094
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5097 5098 5099 5100
	uint32_t val;

	val = I915_READ(PIPECONF(pipe));

5101
	val &= ~PIPECONF_BPC_MASK;
5102
	switch (intel_crtc->config.pipe_bpp) {
5103
	case 18:
5104
		val |= PIPECONF_6BPC;
5105 5106
		break;
	case 24:
5107
		val |= PIPECONF_8BPC;
5108 5109
		break;
	case 30:
5110
		val |= PIPECONF_10BPC;
5111 5112
		break;
	case 36:
5113
		val |= PIPECONF_12BPC;
5114 5115
		break;
	default:
5116 5117
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		BUG();
5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129
	}

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
	if (dither)
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5130
	if (intel_crtc->config.limited_color_range)
5131 5132 5133 5134
		val |= PIPECONF_COLOR_RANGE_SELECT;
	else
		val &= ~PIPECONF_COLOR_RANGE_SELECT;

5135 5136 5137 5138
	I915_WRITE(PIPECONF(pipe), val);
	POSTING_READ(PIPECONF(pipe));
}

5139 5140 5141 5142 5143 5144 5145
/*
 * Set up the pipe CSC unit.
 *
 * Currently only full range RGB to limited range RGB conversion
 * is supported, but eventually this should handle various
 * RGB<->YCbCr scenarios as well.
 */
5146
static void intel_set_pipe_csc(struct drm_crtc *crtc)
5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	uint16_t coeff = 0x7800; /* 1.0 */

	/*
	 * TODO: Check what kind of values actually come out of the pipe
	 * with these coeff/postoff values and adjust to get the best
	 * accuracy. Perhaps we even need to take the bpc value into
	 * consideration.
	 */

5161
	if (intel_crtc->config.limited_color_range)
5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */

	/*
	 * GY/GU and RY/RU should be the other way around according
	 * to BSpec, but reality doesn't agree. Just set them up in
	 * a way that results in the correct picture.
	 */
	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);

	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

	if (INTEL_INFO(dev)->gen > 6) {
		uint16_t postoff = 0;

5185
		if (intel_crtc->config.limited_color_range)
5186 5187 5188 5189 5190 5191 5192 5193 5194 5195
			postoff = (16 * (1 << 13) / 255) & 0x1fff;

		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);

		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
	} else {
		uint32_t mode = CSC_MODE_YUV_TO_RGB;

5196
		if (intel_crtc->config.limited_color_range)
5197 5198 5199 5200 5201 5202
			mode |= CSC_BLACK_SCREEN_OFFSET;

		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
	}
}

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5203 5204 5205 5206 5207 5208
static void haswell_set_pipeconf(struct drm_crtc *crtc,
				 struct drm_display_mode *adjusted_mode,
				 bool dither)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5209
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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5210 5211
	uint32_t val;

5212
	val = I915_READ(PIPECONF(cpu_transcoder));
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5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
	if (dither)
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK_HSW;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5224 5225
	I915_WRITE(PIPECONF(cpu_transcoder), val);
	POSTING_READ(PIPECONF(cpu_transcoder));
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5226 5227
}

5228 5229 5230 5231 5232 5233 5234 5235 5236 5237
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
				    struct drm_display_mode *adjusted_mode,
				    intel_clock_t *clock,
				    bool *has_reduced_clock,
				    intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	int refclk;
5238
	const intel_limit_t *limit;
5239
	bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
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5240

5241 5242
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
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5243 5244 5245 5246
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5247
		case INTEL_OUTPUT_HDMI:
J
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5248
			is_sdvo = true;
5249
			if (intel_encoder->needs_tv_clock)
5250
				is_tv = true;
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5251 5252 5253 5254 5255 5256 5257
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		}
	}

5258
	refclk = ironlake_get_refclk(crtc);
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5259

5260 5261 5262 5263 5264
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
5265
	limit = intel_limit(crtc, refclk);
5266 5267 5268 5269
	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			      clock);
	if (!ret)
		return false;
5270

5271
	if (is_lvds && dev_priv->lvds_downclock_avail) {
5272 5273 5274 5275 5276 5277
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
5278 5279 5280 5281 5282
		*has_reduced_clock = limit->find_pll(limit, crtc,
						     dev_priv->lvds_downclock,
						     refclk,
						     clock,
						     reduced_clock);
5283
	}
5284 5285

	if (is_sdvo && is_tv)
5286
		i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5287 5288 5289 5290

	return true;
}

5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t temp;

	temp = I915_READ(SOUTH_CHICKEN1);
	if (temp & FDI_BC_BIFURCATION_SELECT)
		return;

	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

	temp |= FDI_BC_BIFURCATION_SELECT;
	DRM_DEBUG_KMS("enabling fdi C rx\n");
	I915_WRITE(SOUTH_CHICKEN1, temp);
	POSTING_READ(SOUTH_CHICKEN1);
}

static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);

	DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
		      intel_crtc->pipe, intel_crtc->fdi_lanes);
	if (intel_crtc->fdi_lanes > 4) {
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
			      intel_crtc->pipe, intel_crtc->fdi_lanes);
		/* Clamp lanes to avoid programming the hw with bogus values. */
		intel_crtc->fdi_lanes = 4;

		return false;
	}

5327
	if (INTEL_INFO(dev)->num_pipes == 2)
5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372
		return true;

	switch (intel_crtc->pipe) {
	case PIPE_A:
		return true;
	case PIPE_B:
		if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		    intel_crtc->fdi_lanes > 2) {
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
				      intel_crtc->pipe, intel_crtc->fdi_lanes);
			/* Clamp lanes to avoid programming the hw with bogus values. */
			intel_crtc->fdi_lanes = 2;

			return false;
		}

		if (intel_crtc->fdi_lanes > 2)
			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		else
			cpt_enable_fdi_bc_bifurcation(dev);

		return true;
	case PIPE_C:
		if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
			if (intel_crtc->fdi_lanes > 2) {
				DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
					      intel_crtc->pipe, intel_crtc->fdi_lanes);
				/* Clamp lanes to avoid programming the hw with bogus values. */
				intel_crtc->fdi_lanes = 2;

				return false;
			}
		} else {
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
			return false;
		}

		cpt_enable_fdi_bc_bifurcation(dev);

		return true;
	default:
		BUG();
	}
}

5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
{
	/*
	 * Account for spread spectrum to avoid
	 * oversubscribing the link. Max center spread
	 * is 2.5%; use 5% for safety's sake.
	 */
	u32 bps = target_clock * bpp * 21 / 20;
	return bps / (link_bw * 8) + 1;
}

5384 5385
void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
				  struct intel_link_m_n *m_n)
J
Jesse Barnes 已提交
5386
{
5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

	I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
	I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
	I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
	I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
}

void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
				  struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
J
Jesse Barnes 已提交
5401
	struct drm_i915_private *dev_priv = dev->dev_private;
5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420
	int pipe = crtc->pipe;
	enum transcoder transcoder = crtc->cpu_transcoder;

	if (INTEL_INFO(dev)->gen >= 5) {
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
	} else {
		I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
		I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
		I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
	}
}

static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
J
Jesse Barnes 已提交
5421
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5422 5423
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
5424
	struct intel_link_m_n m_n = {0};
5425
	int target_clock, lane, link_bw;
5426

5427 5428 5429 5430 5431 5432 5433 5434
	/* FDI is a binary signal running at ~2.7GHz, encoding
	 * each output octet as 10 bits. The actual frequency
	 * is stored as a divider into a 100MHz clock, and the
	 * mode pixel clock is stored in units of 1KHz.
	 * Hence the bw of each lane in terms of the mode signal
	 * is:
	 */
	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5435

5436 5437
	if (intel_crtc->config.pixel_target_clock)
		target_clock = intel_crtc->config.pixel_target_clock;
5438 5439 5440
	else
		target_clock = adjusted_mode->clock;

5441 5442
	lane = ironlake_get_lanes_required(target_clock, link_bw,
					   intel_crtc->config.pipe_bpp);
5443

5444 5445
	intel_crtc->fdi_lanes = lane;

5446 5447
	if (intel_crtc->config.pixel_multiplier > 1)
		link_bw *= intel_crtc->config.pixel_multiplier;
5448 5449
	intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
			       link_bw, &m_n);
5450

5451
	intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5452 5453
}

5454 5455
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
				      intel_clock_t *clock, u32 fp)
J
Jesse Barnes 已提交
5456
{
5457
	struct drm_crtc *crtc = &intel_crtc->base;
J
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5458 5459
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5460 5461
	struct intel_encoder *intel_encoder;
	uint32_t dpll;
5462
	int factor, num_connectors = 0;
5463
	bool is_lvds = false, is_sdvo = false, is_tv = false;
J
Jesse Barnes 已提交
5464

5465 5466
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
Jesse Barnes 已提交
5467 5468 5469 5470
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5471
		case INTEL_OUTPUT_HDMI:
J
Jesse Barnes 已提交
5472
			is_sdvo = true;
5473
			if (intel_encoder->needs_tv_clock)
5474
				is_tv = true;
J
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5475 5476 5477 5478 5479
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		}
5480

5481
		num_connectors++;
J
Jesse Barnes 已提交
5482 5483
	}

5484
	/* Enable autotuning of the PLL clock (if permissible) */
5485 5486 5487 5488
	factor = 21;
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
		     dev_priv->lvds_ssc_freq == 100) ||
5489
		    intel_is_dual_link_lvds(dev))
5490 5491 5492
			factor = 25;
	} else if (is_sdvo && is_tv)
		factor = 20;
5493

5494
	if (clock->m < factor * clock->n)
5495
		fp |= FP_CB_TUNE;
5496

5497
	dpll = 0;
5498

5499 5500 5501 5502 5503
	if (is_lvds)
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
	if (is_sdvo) {
5504 5505 5506
		if (intel_crtc->config.pixel_multiplier > 1) {
			dpll |= (intel_crtc->config.pixel_multiplier - 1)
				<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
J
Jesse Barnes 已提交
5507
		}
5508 5509
		dpll |= DPLL_DVO_HIGH_SPEED;
	}
5510 5511
	if (intel_crtc->config.has_dp_encoder &&
	    intel_crtc->config.has_pch_encoder)
5512
		dpll |= DPLL_DVO_HIGH_SPEED;
J
Jesse Barnes 已提交
5513

5514
	/* compute bitmask from p1 value */
5515
	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5516
	/* also FPA1 */
5517
	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5518

5519
	switch (clock->p2) {
5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
J
Jesse Barnes 已提交
5532 5533
	}

5534 5535 5536
	if (is_sdvo && is_tv)
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (is_tv)
J
Jesse Barnes 已提交
5537
		/* XXX: just matching BIOS for now */
5538
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
J
Jesse Barnes 已提交
5539
		dpll |= 3;
5540
	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5541
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
J
Jesse Barnes 已提交
5542 5543 5544
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

5545 5546 5547 5548 5549 5550 5551 5552 5553 5554
	return dpll;
}

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
				  int x, int y,
				  struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5555 5556 5557
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5558 5559 5560 5561 5562
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
	intel_clock_t clock, reduced_clock;
	u32 dpll, fp = 0, fp2 = 0;
5563
	bool ok, has_reduced_clock = false;
5564
	bool is_lvds = false;
5565 5566
	struct intel_encoder *encoder;
	int ret;
5567
	bool dither, fdi_config_ok;
5568 5569 5570 5571 5572 5573 5574 5575 5576

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}

		num_connectors++;
5577
	}
J
Jesse Barnes 已提交
5578

5579 5580
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5581

5582 5583
	intel_crtc->cpu_transcoder = pipe;

5584 5585 5586 5587 5588
	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
				     &has_reduced_clock, &reduced_clock);
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
		return -EINVAL;
J
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5589
	}
5590 5591 5592 5593 5594 5595 5596 5597
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
J
Jesse Barnes 已提交
5598

5599 5600 5601 5602
	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

	/* determine panel color depth */
5603
	dither = intel_crtc->config.dither;
5604 5605 5606 5607 5608 5609 5610 5611
	if (is_lvds && dev_priv->lvds_dither)
		dither = true;

	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
	if (has_reduced_clock)
		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
			reduced_clock.m2;

5612
	dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
J
Jesse Barnes 已提交
5613

5614
	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
J
Jesse Barnes 已提交
5615 5616
	drm_mode_debug_printmodeline(mode);

5617
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5618
	if (intel_crtc->config.has_pch_encoder) {
5619
		struct intel_pch_pll *pll;
5620

5621 5622 5623 5624
		pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		if (pll == NULL) {
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
					 pipe);
5625 5626
			return -EINVAL;
		}
5627 5628
	} else
		intel_put_pch_pll(intel_crtc);
J
Jesse Barnes 已提交
5629

5630 5631
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
J
Jesse Barnes 已提交
5632

5633 5634 5635
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
J
Jesse Barnes 已提交
5636

5637 5638
	if (intel_crtc->pch_pll) {
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5639

5640
		/* Wait for the clocks to stabilize. */
5641
		POSTING_READ(intel_crtc->pch_pll->pll_reg);
5642 5643
		udelay(150);

5644 5645 5646 5647 5648
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
5649
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
J
Jesse Barnes 已提交
5650 5651
	}

5652
	intel_crtc->lowfreq_avail = false;
5653
	if (intel_crtc->pch_pll) {
5654
		if (is_lvds && has_reduced_clock && i915_powersave) {
5655
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5656 5657
			intel_crtc->lowfreq_avail = true;
		} else {
5658
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5659 5660 5661
		}
	}

5662
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5663

5664 5665
	/* Note, this also computes intel_crtc->fdi_lanes which is used below in
	 * ironlake_check_fdi_lanes. */
5666 5667 5668
	intel_crtc->fdi_lanes = 0;
	if (intel_crtc->config.has_pch_encoder)
		ironlake_fdi_set_m_n(crtc);
5669

5670
	fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5671

5672
	ironlake_set_pipeconf(crtc, adjusted_mode, dither);
J
Jesse Barnes 已提交
5673

5674
	intel_wait_for_vblank(dev, pipe);
J
Jesse Barnes 已提交
5675

5676 5677
	/* Set up the display plane register */
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5678
	POSTING_READ(DSPCNTR(plane));
J
Jesse Barnes 已提交
5679

5680
	ret = intel_pipe_set_base(crtc, x, y, fb);
5681 5682 5683

	intel_update_watermarks(dev);

5684 5685
	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);

5686
	return fdi_config_ok ? ret : -EINVAL;
J
Jesse Barnes 已提交
5687 5688
}

5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

5700 5701 5702
	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
		pipe_config->has_pch_encoder = true;

5703 5704 5705
	return true;
}

5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734
static void haswell_modeset_global_resources(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool enable = false;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		if (crtc->pipe != PIPE_A && crtc->base.enabled)
			enable = true;
		/* XXX: Should check for edp transcoder here, but thanks to init
		 * sequence that's not yet available. Just in case desktop eDP
		 * on PORT D is possible on haswell, too. */
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->type != INTEL_OUTPUT_EDP &&
		    encoder->connectors_active)
			enable = true;
	}

	/* Even the eDP panel fitter is outside the always-on well. */
	if (dev_priv->pch_pf_size)
		enable = true;

	intel_set_power_well(dev, enable);
}

P
Paulo Zanoni 已提交
5735 5736 5737 5738 5739 5740 5741
static int haswell_crtc_mode_set(struct drm_crtc *crtc,
				 int x, int y,
				 struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742 5743 5744
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
P
Paulo Zanoni 已提交
5745 5746 5747
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
5748
	bool is_cpu_edp = false;
P
Paulo Zanoni 已提交
5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763
	struct intel_encoder *encoder;
	int ret;
	bool dither;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_EDP:
			if (!intel_encoder_is_pch_edp(&encoder->base))
				is_cpu_edp = true;
			break;
		}

		num_connectors++;
	}

5764 5765 5766 5767 5768
	if (is_cpu_edp)
		intel_crtc->cpu_transcoder = TRANSCODER_EDP;
	else
		intel_crtc->cpu_transcoder = pipe;

5769 5770 5771 5772 5773 5774 5775
	/* We are not sure yet this won't happen. */
	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
	     INTEL_PCH_TYPE(dev));

	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
	     num_connectors, pipe_name(pipe));

5776
	WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5777 5778 5779 5780
		(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));

	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);

5781 5782 5783
	if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
		return -EINVAL;

P
Paulo Zanoni 已提交
5784 5785 5786 5787
	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

	/* determine panel color depth */
5788
	dither = intel_crtc->config.dither;
P
Paulo Zanoni 已提交
5789 5790 5791 5792

	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
	drm_mode_debug_printmodeline(mode);

5793 5794
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
P
Paulo Zanoni 已提交
5795 5796 5797 5798 5799

	intel_crtc->lowfreq_avail = false;

	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);

5800 5801
	if (intel_crtc->config.has_pch_encoder)
		ironlake_fdi_set_m_n(crtc);
P
Paulo Zanoni 已提交
5802

P
Paulo Zanoni 已提交
5803
	haswell_set_pipeconf(crtc, adjusted_mode, dither);
P
Paulo Zanoni 已提交
5804

5805
	intel_set_pipe_csc(crtc);
5806

P
Paulo Zanoni 已提交
5807
	/* Set up the display plane register */
5808
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
P
Paulo Zanoni 已提交
5809 5810 5811 5812 5813 5814 5815 5816
	POSTING_READ(DSPCNTR(plane));

	ret = intel_pipe_set_base(crtc, x, y, fb);

	intel_update_watermarks(dev);

	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);

5817
	return ret;
J
Jesse Barnes 已提交
5818 5819
}

5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
				    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841
	/*
	 * aswell has only FDI/PCH transcoder A. It is which is connected to
	 * DDI E. So just check whether this pipe is wired to DDI E and whether
	 * the PCH transcoder is on.
	 */
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
	    I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
		pipe_config->has_pch_encoder = true;


5842 5843 5844
	return true;
}

5845 5846
static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       int x, int y,
5847
			       struct drm_framebuffer *fb)
5848 5849 5850
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5851 5852
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct intel_encoder *encoder;
5853
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5854 5855 5856
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5857
	int pipe = intel_crtc->pipe;
5858 5859
	int ret;

5860
	drm_vblank_pre_modeset(dev, pipe);
5861

5862 5863
	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);

J
Jesse Barnes 已提交
5864
	drm_vblank_post_modeset(dev, pipe);
5865

5866 5867 5868 5869 5870 5871 5872 5873
	if (ret != 0)
		return ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
			encoder->base.base.id,
			drm_get_encoder_name(&encoder->base),
			mode->base.id, mode->name);
5874 5875 5876 5877 5878 5879
		if (encoder->mode_set) {
			encoder->mode_set(encoder);
		} else {
			encoder_funcs = encoder->base.helper_private;
			encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
		}
5880 5881 5882
	}

	return 0;
J
Jesse Barnes 已提交
5883 5884
}

5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913
static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t i;

	i = I915_READ(reg_eldv);
	i &= bits_eldv;

	if (!eld[0])
		return !i;

	if (!i)
		return false;

	i = I915_READ(reg_elda);
	i &= ~bits_elda;
	I915_WRITE(reg_elda, i);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929
static void g4x_write_eld(struct drm_connector *connector,
			  struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t len;
	uint32_t i;

	i = I915_READ(G4X_AUD_VID_DID);

	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

5930 5931 5932 5933 5934 5935
	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
			       G4X_HDMIW_HDMIEDID))
		return;

5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953
	i = I915_READ(G4X_AUD_CNTL_ST);
	i &= ~(eldv | G4X_ELD_ADDR);
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, i);

	if (!eld[0])
		return;

	len = min_t(uint8_t, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	i = I915_READ(G4X_AUD_CNTL_ST);
	i |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, i);
}

5954 5955 5956 5957 5958 5959
static void haswell_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	struct drm_device *dev = crtc->dev;
5960
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001
	uint32_t eldv;
	uint32_t i;
	int len;
	int pipe = to_intel_crtc(crtc)->pipe;
	int tmp;

	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
	int aud_config = HSW_AUD_CFG(pipe);
	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;


	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");

	/* Audio output enable */
	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Wait for 1 vertical blank */
	intel_wait_for_vblank(dev, pipe);

	/* Set ELD valid state */
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);

	/* Enable HDMI mode */
	tmp = I915_READ(aud_config);
	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
	/* clear N_programing_enable and N_value_index */
	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
	I915_WRITE(aud_config, tmp);

	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));

	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6002
	intel_crtc->eld_vld = true;
6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);

	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
	i &= ~IBX_ELD_ADDRESS;
	I915_WRITE(aud_cntl_st, i);
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
	DRM_DEBUG_DRIVER("port num:%d\n", i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);

}

6041 6042 6043 6044 6045 6046 6047 6048 6049
static void ironlake_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t i;
	int len;
	int hdmiw_hdmiedid;
6050
	int aud_config;
6051 6052
	int aud_cntl_st;
	int aud_cntrl_st2;
6053
	int pipe = to_intel_crtc(crtc)->pipe;
6054

6055
	if (HAS_PCH_IBX(connector->dev)) {
6056 6057 6058
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6059
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6060
	} else {
6061 6062 6063
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6064
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6065 6066
	}

6067
	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6068 6069

	i = I915_READ(aud_cntl_st);
6070
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
6071 6072 6073
	if (!i) {
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		/* operate blindly on all ports */
6074 6075 6076
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
6077 6078
	} else {
		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6079
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6080 6081
	}

6082 6083 6084
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
6085 6086 6087
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);
6088

6089 6090 6091 6092 6093 6094
	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

6095 6096 6097 6098 6099 6100 6101 6102
	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
6103
	i &= ~IBX_ELD_ADDRESS;
6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139
	I915_WRITE(aud_cntl_st, i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);
}

void intel_write_eld(struct drm_encoder *encoder,
		     struct drm_display_mode *mode)
{
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 drm_get_connector_name(connector),
			 connector->encoder->base.id,
			 drm_get_encoder_name(connector->encoder));

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.write_eld)
		dev_priv->display.write_eld(connector, crtc);
}

J
Jesse Barnes 已提交
6140 6141 6142 6143 6144 6145
/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146
	int palreg = PALETTE(intel_crtc->pipe);
J
Jesse Barnes 已提交
6147 6148 6149
	int i;

	/* The clocks have to be on to load the palette. */
6150
	if (!crtc->enabled || !intel_crtc->active)
J
Jesse Barnes 已提交
6151 6152
		return;

6153
	/* use legacy palette for Ironlake */
6154
	if (HAS_PCH_SPLIT(dev))
6155
		palreg = LGC_PALETTE(intel_crtc->pipe);
6156

J
Jesse Barnes 已提交
6157 6158 6159 6160 6161 6162 6163 6164
	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
}

6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

6176
	cntl = I915_READ(_CURACNTR);
6177 6178 6179 6180
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
6181
		I915_WRITE(_CURABASE, base);
6182 6183 6184 6185 6186 6187 6188 6189

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6190
	I915_WRITE(_CURACNTR, cntl);
6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
6204
		uint32_t cntl = I915_READ(CURCNTR(pipe));
6205 6206 6207 6208 6209 6210 6211 6212
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6213
		I915_WRITE(CURCNTR(pipe), cntl);
6214 6215 6216 6217

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
6218
	I915_WRITE(CURBASE(pipe), base);
6219 6220
}

J
Jesse Barnes 已提交
6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		if (base) {
			cntl &= ~CURSOR_MODE;
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6238 6239
		if (IS_HASWELL(dev))
			cntl |= CURSOR_PIPE_CSC_ENABLE;
J
Jesse Barnes 已提交
6240 6241 6242 6243 6244 6245 6246 6247
		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(CURBASE_IVB(pipe), base);
}

6248
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6249 6250
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
6251 6252 6253 6254 6255 6256 6257
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
6258
	u32 base, pos;
6259 6260 6261 6262
	bool visible;

	pos = 0;

6263
	if (on && crtc->enabled && crtc->fb) {
6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
6292
	if (!visible && !intel_crtc->cursor_visible)
6293 6294
		return;

6295
	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
J
Jesse Barnes 已提交
6296 6297 6298 6299 6300 6301 6302 6303 6304
		I915_WRITE(CURPOS_IVB(pipe), pos);
		ivb_update_cursor(crtc, base);
	} else {
		I915_WRITE(CURPOS(pipe), pos);
		if (IS_845G(dev) || IS_I865G(dev))
			i845_update_cursor(crtc, base);
		else
			i9xx_update_cursor(crtc, base);
	}
6305 6306
}

J
Jesse Barnes 已提交
6307
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6308
				 struct drm_file *file,
J
Jesse Barnes 已提交
6309 6310 6311 6312 6313 6314
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315
	struct drm_i915_gem_object *obj;
6316
	uint32_t addr;
6317
	int ret;
J
Jesse Barnes 已提交
6318 6319 6320

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
6321
		DRM_DEBUG_KMS("cursor off\n");
6322
		addr = 0;
6323
		obj = NULL;
6324
		mutex_lock(&dev->struct_mutex);
6325
		goto finish;
J
Jesse Barnes 已提交
6326 6327 6328 6329 6330 6331 6332 6333
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

6334
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6335
	if (&obj->base == NULL)
J
Jesse Barnes 已提交
6336 6337
		return -ENOENT;

6338
	if (obj->base.size < width * height * 4) {
J
Jesse Barnes 已提交
6339
		DRM_ERROR("buffer is to small\n");
6340 6341
		ret = -ENOMEM;
		goto fail;
J
Jesse Barnes 已提交
6342 6343
	}

6344
	/* we only need to pin inside GTT if cursor is non-phy */
6345
	mutex_lock(&dev->struct_mutex);
6346
	if (!dev_priv->info->cursor_needs_physical) {
6347 6348
		unsigned alignment;

6349 6350 6351 6352 6353 6354
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

6355 6356 6357 6358 6359 6360 6361 6362 6363 6364
		/* Note that the w/a also requires 2 PTE of padding following
		 * the bo. We currently fill all unused PTE with the shadow
		 * page and so we should always have valid PTE following the
		 * cursor preventing the VT-d warning.
		 */
		alignment = 0;
		if (need_vtd_wa(dev))
			alignment = 64*1024;

		ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6365 6366
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
6367
			goto fail_locked;
6368 6369
		}

6370 6371
		ret = i915_gem_object_put_fence(obj);
		if (ret) {
6372
			DRM_ERROR("failed to release fence for cursor");
6373 6374 6375
			goto fail_unpin;
		}

6376
		addr = obj->gtt_offset;
6377
	} else {
6378
		int align = IS_I830(dev) ? 16 * 1024 : 256;
6379
		ret = i915_gem_attach_phys_object(dev, obj,
6380 6381
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
6382 6383
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
6384
			goto fail_locked;
6385
		}
6386
		addr = obj->phys_obj->handle->busaddr;
6387 6388
	}

6389
	if (IS_GEN2(dev))
J
Jesse Barnes 已提交
6390 6391
		I915_WRITE(CURSIZE, (height << 12) | width);

6392 6393
 finish:
	if (intel_crtc->cursor_bo) {
6394
		if (dev_priv->info->cursor_needs_physical) {
6395
			if (intel_crtc->cursor_bo != obj)
6396 6397 6398
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
			i915_gem_object_unpin(intel_crtc->cursor_bo);
6399
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6400
	}
6401

6402
	mutex_unlock(&dev->struct_mutex);
6403 6404

	intel_crtc->cursor_addr = addr;
6405
	intel_crtc->cursor_bo = obj;
6406 6407 6408
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

6409
	intel_crtc_update_cursor(crtc, true);
6410

J
Jesse Barnes 已提交
6411
	return 0;
6412
fail_unpin:
6413
	i915_gem_object_unpin(obj);
6414
fail_locked:
6415
	mutex_unlock(&dev->struct_mutex);
6416
fail:
6417
	drm_gem_object_unreference_unlocked(&obj->base);
6418
	return ret;
J
Jesse Barnes 已提交
6419 6420 6421 6422 6423 6424
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6425 6426
	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;
6427

6428
	intel_crtc_update_cursor(crtc, true);
J
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6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

6444 6445 6446 6447 6448 6449 6450 6451 6452 6453
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

J
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6454
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
J
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6455
				 u16 *blue, uint32_t start, uint32_t size)
J
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6456
{
J
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6457
	int end = (start + size > 256) ? 256 : start + size, i;
J
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6458 6459
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

J
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6460
	for (i = start; i < end; i++) {
J
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6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

6475 6476
static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device *dev,
6477
			 struct drm_mode_fb_cmd2 *mode_cmd,
6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518
			 struct drm_i915_gem_object *obj)
{
	struct intel_framebuffer *intel_fb;
	int ret;

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return ERR_PTR(-ENOMEM);
	}

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
	return ALIGN(pitch, 64);
}

static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}

static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device *dev,
				  struct drm_display_mode *mode,
				  int depth, int bpp)
{
	struct drm_i915_gem_object *obj;
6519
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6520 6521 6522 6523 6524 6525 6526 6527

	obj = i915_gem_alloc_object(dev,
				    intel_framebuffer_size_for_mode(mode, bpp));
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);

	mode_cmd.width = mode->hdisplay;
	mode_cmd.height = mode->vdisplay;
6528 6529
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
								bpp);
6530
	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550

	return intel_framebuffer_create(dev, &mode_cmd, obj);
}

static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
		   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_framebuffer *fb;

	if (dev_priv->fbdev == NULL)
		return NULL;

	obj = dev_priv->fbdev->ifb.obj;
	if (obj == NULL)
		return NULL;

	fb = &dev_priv->fbdev->ifb.base;
6551 6552
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
							       fb->bits_per_pixel))
6553 6554
		return NULL;

6555
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
6556 6557 6558 6559 6560
		return NULL;

	return fb;
}

6561
bool intel_get_load_detect_pipe(struct drm_connector *connector,
6562
				struct drm_display_mode *mode,
6563
				struct intel_load_detect_pipe *old)
J
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6564 6565
{
	struct intel_crtc *intel_crtc;
6566 6567
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
J
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6568
	struct drm_crtc *possible_crtc;
6569
	struct drm_encoder *encoder = &intel_encoder->base;
J
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6570 6571
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
6572
	struct drm_framebuffer *fb;
J
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6573 6574
	int i = -1;

6575 6576 6577 6578
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

J
Jesse Barnes 已提交
6579 6580
	/*
	 * Algorithm gets a little messy:
6581
	 *
J
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6582 6583
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
6584
	 *
J
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6585 6586 6587 6588 6589 6590 6591
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
6592

6593 6594
		mutex_lock(&crtc->mutex);

6595
		old->dpms_mode = connector->dpms;
6596 6597 6598
		old->load_detect_temp = false;

		/* Make sure the crtc and connector are running */
6599 6600
		if (connector->dpms != DRM_MODE_DPMS_ON)
			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6601

6602
		return true;
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6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
6620 6621
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
		return false;
J
Jesse Barnes 已提交
6622 6623
	}

6624
	mutex_lock(&crtc->mutex);
6625 6626
	intel_encoder->new_crtc = to_intel_crtc(crtc);
	to_intel_connector(connector)->new_encoder = intel_encoder;
J
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6627 6628

	intel_crtc = to_intel_crtc(crtc);
6629
	old->dpms_mode = connector->dpms;
6630
	old->load_detect_temp = true;
6631
	old->release_fb = NULL;
J
Jesse Barnes 已提交
6632

6633 6634
	if (!mode)
		mode = &load_detect_mode;
J
Jesse Barnes 已提交
6635

6636 6637 6638 6639 6640 6641 6642
	/* We need a framebuffer large enough to accommodate all accesses
	 * that the plane may generate whilst we perform load detection.
	 * We can not rely on the fbcon either being present (we get called
	 * during its initialisation to detect all boot displays, or it may
	 * not even exist) or that it is large enough to satisfy the
	 * requested mode.
	 */
6643 6644
	fb = mode_fits_in_fbdev(dev, mode);
	if (fb == NULL) {
6645
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6646 6647
		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		old->release_fb = fb;
6648 6649
	} else
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6650
	if (IS_ERR(fb)) {
6651
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6652
		mutex_unlock(&crtc->mutex);
6653
		return false;
J
Jesse Barnes 已提交
6654 6655
	}

6656
	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6657
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6658 6659
		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);
6660
		mutex_unlock(&crtc->mutex);
6661
		return false;
J
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6662
	}
6663

J
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6664
	/* let the connector get through one full cycle before testing */
6665
	intel_wait_for_vblank(dev, intel_crtc->pipe);
6666
	return true;
J
Jesse Barnes 已提交
6667 6668
}

6669
void intel_release_load_detect_pipe(struct drm_connector *connector,
6670
				    struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
6671
{
6672 6673
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
6674
	struct drm_encoder *encoder = &intel_encoder->base;
6675
	struct drm_crtc *crtc = encoder->crtc;
J
Jesse Barnes 已提交
6676

6677 6678 6679 6680
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

6681
	if (old->load_detect_temp) {
6682 6683 6684
		to_intel_connector(connector)->new_encoder = NULL;
		intel_encoder->new_crtc = NULL;
		intel_set_mode(crtc, NULL, 0, 0, NULL);
6685

6686 6687 6688 6689
		if (old->release_fb) {
			drm_framebuffer_unregister_private(old->release_fb);
			drm_framebuffer_unreference(old->release_fb);
		}
6690

6691
		mutex_unlock(&crtc->mutex);
6692
		return;
J
Jesse Barnes 已提交
6693 6694
	}

6695
	/* Switch crtc and encoder back off if necessary */
6696 6697
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		connector->funcs->dpms(connector, old->dpms_mode);
6698 6699

	mutex_unlock(&crtc->mutex);
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6700 6701 6702 6703 6704 6705 6706 6707
}

/* Returns the clock of the currently programmed mode of the given pipe. */
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6708
	u32 dpll = I915_READ(DPLL(pipe));
J
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6709 6710 6711 6712
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6713
		fp = I915_READ(FP0(pipe));
J
Jesse Barnes 已提交
6714
	else
6715
		fp = I915_READ(FP1(pipe));
J
Jesse Barnes 已提交
6716 6717

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6718 6719 6720
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6721 6722 6723 6724 6725
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

6726
	if (!IS_GEN2(dev)) {
6727 6728 6729
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6730 6731
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
J
Jesse Barnes 已提交
6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
6744
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
J
Jesse Barnes 已提交
6745 6746 6747 6748 6749
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
			return 0;
		}

		/* XXX: Handle the 100Mhz refclk */
6750
		intel_clock(dev, 96000, &clock);
J
Jesse Barnes 已提交
6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
6762
				intel_clock(dev, 66000, &clock);
J
Jesse Barnes 已提交
6763
			} else
6764
				intel_clock(dev, 48000, &clock);
J
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6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

6777
			intel_clock(dev, 48000, &clock);
J
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6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792
		}
	}

	/* XXX: It would be nice to validate the clocks, but we can't reuse
	 * i830PllIsValid() because it relies on the xf86_config connector
	 * configuration being accurate, which it isn't necessarily.
	 */

	return clock.dot;
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
6793
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
6794
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6795
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
J
Jesse Barnes 已提交
6796
	struct drm_display_mode *mode;
6797 6798 6799 6800
	int htot = I915_READ(HTOTAL(cpu_transcoder));
	int hsync = I915_READ(HSYNC(cpu_transcoder));
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
	int vsync = I915_READ(VSYNC(cpu_transcoder));
J
Jesse Barnes 已提交
6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

	mode->clock = intel_crtc_clock_get(dev, crtc);
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);

	return mode;
}

6821
static void intel_increase_pllclock(struct drm_crtc *crtc)
6822 6823 6824 6825 6826
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6827 6828
	int dpll_reg = DPLL(pipe);
	int dpll;
6829

6830
	if (HAS_PCH_SPLIT(dev))
6831 6832 6833 6834 6835
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

6836
	dpll = I915_READ(dpll_reg);
6837
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6838
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
6839

6840
		assert_panel_unlocked(dev_priv, pipe);
6841 6842 6843

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6844
		intel_wait_for_vblank(dev, pipe);
6845

6846 6847
		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
6848
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6849 6850 6851 6852 6853 6854 6855 6856 6857
	}
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6858
	if (HAS_PCH_SPLIT(dev))
6859 6860 6861 6862 6863 6864 6865 6866 6867 6868
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6869 6870 6871
		int pipe = intel_crtc->pipe;
		int dpll_reg = DPLL(pipe);
		int dpll;
6872

6873
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
6874

6875
		assert_panel_unlocked(dev_priv, pipe);
6876

6877
		dpll = I915_READ(dpll_reg);
6878 6879
		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6880
		intel_wait_for_vblank(dev, pipe);
6881 6882
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6883
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6884 6885 6886 6887
	}

}

6888 6889 6890 6891 6892 6893
void intel_mark_busy(struct drm_device *dev)
{
	i915_update_gfx_val(dev->dev_private);
}

void intel_mark_idle(struct drm_device *dev)
6894 6895 6896 6897 6898 6899 6900 6901 6902 6903
{
	struct drm_crtc *crtc;

	if (!i915_powersave)
		return;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

6904
		intel_decrease_pllclock(crtc);
6905 6906 6907
	}
}

6908
void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6909
{
6910 6911
	struct drm_device *dev = obj->base.dev;
	struct drm_crtc *crtc;
6912

6913
	if (!i915_powersave)
6914 6915
		return;

6916 6917 6918 6919
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

6920
		if (to_intel_framebuffer(crtc->fb)->obj == obj)
6921
			intel_increase_pllclock(crtc);
6922 6923 6924
	}
}

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Jesse Barnes 已提交
6925 6926 6927
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}
J
Jesse Barnes 已提交
6941 6942

	drm_crtc_cleanup(crtc);
6943

J
Jesse Barnes 已提交
6944 6945 6946
	kfree(intel_crtc);
}

6947 6948 6949 6950
static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);
6951
	struct drm_device *dev = work->crtc->dev;
6952

6953
	mutex_lock(&dev->struct_mutex);
6954
	intel_unpin_fb_obj(work->old_fb_obj);
6955 6956
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);
6957

6958 6959 6960 6961 6962 6963
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);

6964 6965 6966
	kfree(work);
}

6967
static void do_intel_finish_page_flip(struct drm_device *dev,
6968
				      struct drm_crtc *crtc)
6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
6981 6982 6983 6984 6985

	/* Ensure we don't miss a work->pending update ... */
	smp_rmb();

	if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6986 6987 6988 6989
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

6990 6991 6992
	/* and that the unpin work is consistent wrt ->pending. */
	smp_rmb();

6993 6994
	intel_crtc->unpin_work = NULL;

6995 6996
	if (work->event)
		drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6997

6998 6999
	drm_vblank_put(dev, intel_crtc->pipe);

7000 7001
	spin_unlock_irqrestore(&dev->event_lock, flags);

7002
	wake_up_all(&dev_priv->pending_flip_queue);
7003 7004

	queue_work(dev_priv->wq, &work->work);
7005 7006

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7007 7008
}

7009 7010 7011 7012 7013
void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

7014
	do_intel_finish_page_flip(dev, crtc);
7015 7016 7017 7018 7019 7020 7021
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

7022
	do_intel_finish_page_flip(dev, crtc);
7023 7024
}

7025 7026 7027 7028 7029 7030 7031
void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

7032 7033 7034 7035
	/* NB: An MMIO update of the plane base pointer will also
	 * generate a page-flip completion irq, i.e. every modeset
	 * is also accompanied by a spurious intel_prepare_page_flip().
	 */
7036
	spin_lock_irqsave(&dev->event_lock, flags);
7037 7038
	if (intel_crtc->unpin_work)
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7039 7040 7041
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

7042 7043 7044 7045 7046 7047 7048 7049 7050
inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
{
	/* Ensure that the work item is consistent when activating it ... */
	smp_wmb();
	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
	/* and that it is marked active as soon as the irq could fire. */
	smp_wmb();
}

7051 7052 7053 7054 7055 7056 7057 7058
static int intel_gen2_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7059
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7060 7061
	int ret;

7062
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7063
	if (ret)
7064
		goto err;
7065

7066
	ret = intel_ring_begin(ring, 6);
7067
	if (ret)
7068
		goto err_unpin;
7069 7070 7071 7072 7073 7074 7075 7076

	/* Can't queue multiple flips, so wait for the previous
	 * one to finish before executing the next.
	 */
	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7077 7078 7079 7080 7081
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7082
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7083
	intel_ring_emit(ring, 0); /* aux display base address, unused */
7084 7085

	intel_mark_page_flip_active(intel_crtc);
7086
	intel_ring_advance(ring);
7087 7088 7089 7090 7091
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102
	return ret;
}

static int intel_gen3_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7103
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7104 7105
	int ret;

7106
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7107
	if (ret)
7108
		goto err;
7109

7110
	ret = intel_ring_begin(ring, 6);
7111
	if (ret)
7112
		goto err_unpin;
7113 7114 7115 7116 7117

	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7118 7119 7120 7121 7122
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7123
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7124 7125
	intel_ring_emit(ring, MI_NOOP);

7126
	intel_mark_page_flip_active(intel_crtc);
7127
	intel_ring_advance(ring);
7128 7129 7130 7131 7132
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143
	return ret;
}

static int intel_gen4_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
7144
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7145 7146
	int ret;

7147
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7148
	if (ret)
7149
		goto err;
7150

7151
	ret = intel_ring_begin(ring, 4);
7152
	if (ret)
7153
		goto err_unpin;
7154 7155 7156 7157 7158

	/* i965+ uses the linear or tiled offsets from the
	 * Display Registers (which do not change across a page-flip)
	 * so we need only reprogram the base address.
	 */
7159 7160 7161
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7162 7163 7164
	intel_ring_emit(ring,
			(obj->gtt_offset + intel_crtc->dspaddr_offset) |
			obj->tiling_mode);
7165 7166 7167 7168 7169 7170 7171

	/* XXX Enabling the panel-fitter across page-flip is so far
	 * untested on non-native modes, so ignore it for now.
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
	 */
	pf = 0;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7172
	intel_ring_emit(ring, pf | pipesrc);
7173 7174

	intel_mark_page_flip_active(intel_crtc);
7175
	intel_ring_advance(ring);
7176 7177 7178 7179 7180
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7181 7182 7183 7184 7185 7186 7187 7188 7189 7190
	return ret;
}

static int intel_gen6_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7191
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7192 7193 7194
	uint32_t pf, pipesrc;
	int ret;

7195
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7196
	if (ret)
7197
		goto err;
7198

7199
	ret = intel_ring_begin(ring, 4);
7200
	if (ret)
7201
		goto err_unpin;
7202

7203 7204 7205
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7206
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7207

7208 7209 7210 7211 7212 7213 7214
	/* Contrary to the suggestions in the documentation,
	 * "Enable Panel Fitter" does not seem to be required when page
	 * flipping with a non-native mode, and worse causes a normal
	 * modeset to fail.
	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
	 */
	pf = 0;
7215
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7216
	intel_ring_emit(ring, pf | pipesrc);
7217 7218

	intel_mark_page_flip_active(intel_crtc);
7219
	intel_ring_advance(ring);
7220 7221 7222 7223 7224
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7225 7226 7227
	return ret;
}

7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241
/*
 * On gen7 we currently use the blit ring because (in early silicon at least)
 * the render ring doesn't give us interrpts for page flip completion, which
 * means clients will hang after the first flip is queued.  Fortunately the
 * blit ring generates interrupts properly, so use it instead.
 */
static int intel_gen7_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7242
	uint32_t plane_bit = 0;
7243 7244 7245 7246
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
	if (ret)
7247
		goto err;
7248

7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261
	switch(intel_crtc->plane) {
	case PLANE_A:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		break;
	case PLANE_B:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		break;
	case PLANE_C:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		break;
	default:
		WARN_ONCE(1, "unknown plane in flip command\n");
		ret = -ENODEV;
7262
		goto err_unpin;
7263 7264
	}

7265 7266
	ret = intel_ring_begin(ring, 4);
	if (ret)
7267
		goto err_unpin;
7268

7269
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7270
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7271
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7272
	intel_ring_emit(ring, (MI_NOOP));
7273 7274

	intel_mark_page_flip_active(intel_crtc);
7275
	intel_ring_advance(ring);
7276 7277 7278 7279 7280
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7281 7282 7283
	return ret;
}

7284 7285 7286 7287 7288 7289 7290 7291
static int intel_default_queue_flip(struct drm_device *dev,
				    struct drm_crtc *crtc,
				    struct drm_framebuffer *fb,
				    struct drm_i915_gem_object *obj)
{
	return -ENODEV;
}

7292 7293 7294 7295 7296 7297
static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
7298 7299
	struct drm_framebuffer *old_fb = crtc->fb;
	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7300 7301
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
7302
	unsigned long flags;
7303
	int ret;
7304

7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317
	/* Can't change pixel format via MI display flips. */
	if (fb->pixel_format != crtc->fb->pixel_format)
		return -EINVAL;

	/*
	 * TILEOFF/LINOFF registers can't be changed via MI display flips.
	 * Note that pitch changes could also affect these register.
	 */
	if (INTEL_INFO(dev)->gen > 3 &&
	    (fb->offsets[0] != crtc->fb->offsets[0] ||
	     fb->pitches[0] != crtc->fb->pitches[0]))
		return -EINVAL;

7318 7319 7320 7321 7322
	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
7323
	work->crtc = crtc;
7324
	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7325 7326
	INIT_WORK(&work->work, intel_unpin_work_fn);

7327 7328 7329 7330
	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto free_work;

7331 7332 7333 7334 7335
	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);
7336
		drm_vblank_put(dev, intel_crtc->pipe);
7337 7338

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7339 7340 7341 7342 7343
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7344 7345 7346
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		flush_workqueue(dev_priv->wq);

7347 7348 7349
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto cleanup;
7350

7351
	/* Reference the objects for the scheduled work. */
7352 7353
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);
7354 7355

	crtc->fb = fb;
7356

7357 7358
	work->pending_flip_obj = obj;

7359 7360
	work->enable_stall_check = true;

7361
	atomic_inc(&intel_crtc->unpin_work_count);
7362
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7363

7364 7365 7366
	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
	if (ret)
		goto cleanup_pending;
7367

7368
	intel_disable_fbc(dev);
7369
	intel_mark_fb_busy(obj);
7370 7371
	mutex_unlock(&dev->struct_mutex);

7372 7373
	trace_i915_flip_request(intel_crtc->plane, obj);

7374
	return 0;
7375

7376
cleanup_pending:
7377
	atomic_dec(&intel_crtc->unpin_work_count);
7378
	crtc->fb = old_fb;
7379 7380
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
7381 7382
	mutex_unlock(&dev->struct_mutex);

7383
cleanup:
7384 7385 7386 7387
	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7388 7389
	drm_vblank_put(dev, intel_crtc->pipe);
free_work:
7390 7391 7392
	kfree(work);

	return ret;
7393 7394
}

7395 7396 7397 7398 7399
static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
};

7400
bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7401
{
7402 7403
	struct intel_encoder *other_encoder;
	struct drm_crtc *crtc = &encoder->new_crtc->base;
7404

7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416
	if (WARN_ON(!crtc))
		return false;

	list_for_each_entry(other_encoder,
			    &crtc->dev->mode_config.encoder_list,
			    base.head) {

		if (&other_encoder->new_crtc->base != crtc ||
		    encoder == other_encoder)
			continue;
		else
			return true;
7417 7418
	}

7419 7420
	return false;
}
7421

7422 7423 7424 7425 7426 7427
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
				  struct drm_crtc *crtc)
{
	struct drm_device *dev;
	struct drm_crtc *tmp;
	int crtc_mask = 1;
7428

7429
	WARN(!crtc, "checking null crtc?\n");
7430

7431
	dev = crtc->dev;
7432

7433 7434 7435 7436 7437
	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		if (tmp == crtc)
			break;
		crtc_mask <<= 1;
	}
7438

7439 7440 7441
	if (encoder->possible_crtcs & crtc_mask)
		return true;
	return false;
7442
}
J
Jesse Barnes 已提交
7443

7444 7445 7446 7447 7448 7449 7450
/**
 * intel_modeset_update_staged_output_state
 *
 * Updates the staged output configuration state, e.g. after we've read out the
 * current hw state.
 */
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7451
{
7452 7453
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7454

7455 7456 7457 7458 7459
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->new_encoder =
			to_intel_encoder(connector->base.encoder);
	}
7460

7461 7462 7463 7464 7465
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->new_crtc =
			to_intel_crtc(encoder->base.crtc);
	}
7466 7467
}

7468 7469 7470 7471 7472 7473 7474 7475 7476
/**
 * intel_modeset_commit_output_state
 *
 * This function copies the stage display pipe configuration to the real one.
 */
static void intel_modeset_commit_output_state(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7477

7478 7479 7480 7481
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->base.encoder = &connector->new_encoder->base;
	}
7482

7483 7484 7485 7486 7487 7488
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->base.crtc = &encoder->new_crtc->base;
	}
}

7489 7490 7491 7492 7493 7494 7495 7496 7497
static int
pipe_config_set_bpp(struct drm_crtc *crtc,
		    struct drm_framebuffer *fb,
		    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->dev;
	struct drm_connector *connector;
	int bpp;

7498 7499
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
7500 7501
		bpp = 8*3; /* since we go through a colormap */
		break;
7502 7503 7504 7505 7506 7507
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen > 3))
			return -EINVAL;
	case DRM_FORMAT_RGB565:
7508 7509
		bpp = 6*3; /* min is 18bpp */
		break;
7510 7511 7512 7513 7514 7515 7516
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
			return -EINVAL;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
7517 7518
		bpp = 8*3;
		break;
7519 7520 7521 7522 7523 7524
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7525
			return -EINVAL;
7526 7527
		bpp = 10*3;
		break;
7528
	/* TODO: gen4+ supports 16 bpc floating point, too. */
7529 7530 7531 7532 7533 7534 7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553
	default:
		DRM_DEBUG_KMS("unsupported depth\n");
		return -EINVAL;
	}

	pipe_config->pipe_bpp = bpp;

	/* Clamp display bpp to EDID value */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    head) {
		if (connector->encoder && connector->encoder->crtc != crtc)
			continue;

		/* Don't use an invalid EDID bpc value */
		if (connector->display_info.bpc &&
		    connector->display_info.bpc * 3 < bpp) {
			DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
				      bpp, connector->display_info.bpc*3);
			pipe_config->pipe_bpp = connector->display_info.bpc*3;
		}
	}

	return bpp;
}

7554 7555
static struct intel_crtc_config *
intel_modeset_pipe_config(struct drm_crtc *crtc,
7556
			  struct drm_framebuffer *fb,
7557
			  struct drm_display_mode *mode)
7558
{
7559 7560 7561
	struct drm_device *dev = crtc->dev;
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct intel_encoder *encoder;
7562
	struct intel_crtc_config *pipe_config;
7563
	int plane_bpp;
7564

7565 7566
	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
	if (!pipe_config)
7567 7568
		return ERR_PTR(-ENOMEM);

7569 7570 7571
	drm_mode_copy(&pipe_config->adjusted_mode, mode);
	drm_mode_copy(&pipe_config->requested_mode, mode);

7572 7573 7574 7575
	plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
	if (plane_bpp < 0)
		goto fail;

7576 7577 7578
	/* Pass our mode to the connectors and the CRTC to give them a chance to
	 * adjust it according to limitations or connector properties, and also
	 * a chance to reject the mode entirely.
7579
	 */
7580 7581
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
7582

7583 7584
		if (&encoder->new_crtc->base != crtc)
			continue;
7585 7586 7587 7588 7589 7590 7591 7592 7593 7594

		if (encoder->compute_config) {
			if (!(encoder->compute_config(encoder, pipe_config))) {
				DRM_DEBUG_KMS("Encoder config failure\n");
				goto fail;
			}

			continue;
		}

7595
		encoder_funcs = encoder->base.helper_private;
7596 7597 7598
		if (!(encoder_funcs->mode_fixup(&encoder->base,
						&pipe_config->requested_mode,
						&pipe_config->adjusted_mode))) {
7599 7600 7601
			DRM_DEBUG_KMS("Encoder fixup failed\n");
			goto fail;
		}
7602
	}
7603

7604
	if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7605 7606
		DRM_DEBUG_KMS("CRTC fixup failed\n");
		goto fail;
7607
	}
7608
	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7609

7610 7611 7612 7613
	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		      plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);

7614
	return pipe_config;
7615
fail:
7616
	kfree(pipe_config);
7617
	return ERR_PTR(-EINVAL);
7618
}
7619

7620 7621 7622 7623 7624
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
static void
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
			     unsigned *prepare_pipes, unsigned *disable_pipes)
J
Jesse Barnes 已提交
7625 7626
{
	struct intel_crtc *intel_crtc;
7627 7628 7629 7630
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct drm_crtc *tmp_crtc;
J
Jesse Barnes 已提交
7631

7632
	*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
J
Jesse Barnes 已提交
7633

7634 7635 7636 7637 7638 7639 7640 7641
	/* Check which crtcs have changed outputs connected to them, these need
	 * to be part of the prepare_pipes mask. We don't (yet) support global
	 * modeset across multiple crtcs, so modeset_pipes will only have one
	 * bit set at most. */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->base.encoder == &connector->new_encoder->base)
			continue;
J
Jesse Barnes 已提交
7642

7643 7644 7645 7646 7647 7648 7649 7650 7651
		if (connector->base.encoder) {
			tmp_crtc = connector->base.encoder->crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (connector->new_encoder)
			*prepare_pipes |=
				1 << connector->new_encoder->new_crtc->pipe;
J
Jesse Barnes 已提交
7652 7653
	}

7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->base.crtc == &encoder->new_crtc->base)
			continue;

		if (encoder->base.crtc) {
			tmp_crtc = encoder->base.crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (encoder->new_crtc)
			*prepare_pipes |= 1 << encoder->new_crtc->pipe;
7667 7668
	}

7669 7670 7671 7672
	/* Check for any pipes that will be fully disabled ... */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool used = false;
J
Jesse Barnes 已提交
7673

7674 7675 7676
		/* Don't try to disable disabled crtcs. */
		if (!intel_crtc->base.enabled)
			continue;
7677

7678 7679 7680 7681 7682 7683 7684 7685
		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->new_crtc == intel_crtc)
				used = true;
		}

		if (!used)
			*disable_pipes |= 1 << intel_crtc->pipe;
7686 7687
	}

7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709

	/* set_mode is also used to update properties on life display pipes. */
	intel_crtc = to_intel_crtc(crtc);
	if (crtc->enabled)
		*prepare_pipes |= 1 << intel_crtc->pipe;

	/* We only support modeset on one single crtc, hence we need to do that
	 * only for the passed in crtc iff we change anything else than just
	 * disable crtcs.
	 *
	 * This is actually not true, to be fully compatible with the old crtc
	 * helper we automatically disable _any_ output (i.e. doesn't need to be
	 * connected to the crtc we're modesetting on) if it's disconnected.
	 * Which is a rather nutty api (since changed the output configuration
	 * without userspace's explicit request can lead to confusion), but
	 * alas. Hence we currently need to modeset on all pipes we prepare. */
	if (*prepare_pipes)
		*modeset_pipes = *prepare_pipes;

	/* ... and mask these out. */
	*modeset_pipes &= ~(*disable_pipes);
	*prepare_pipes &= ~(*disable_pipes);
7710
}
J
Jesse Barnes 已提交
7711

7712
static bool intel_crtc_in_use(struct drm_crtc *crtc)
7713
{
7714
	struct drm_encoder *encoder;
7715 7716
	struct drm_device *dev = crtc->dev;

7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754 7755 7756
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			return true;

	return false;
}

static void
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
{
	struct intel_encoder *intel_encoder;
	struct intel_crtc *intel_crtc;
	struct drm_connector *connector;

	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (!intel_encoder->base.crtc)
			continue;

		intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe))
			intel_encoder->connectors_active = false;
	}

	intel_modeset_commit_output_state(dev);

	/* Update computed state. */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		intel_crtc = to_intel_crtc(connector->encoder->crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe)) {
7757 7758 7759
			struct drm_property *dpms_property =
				dev->mode_config.dpms_property;

7760
			connector->dpms = DRM_MODE_DPMS_ON;
7761
			drm_object_property_set_value(&connector->base,
7762 7763
							 dpms_property,
							 DRM_MODE_DPMS_ON);
7764 7765 7766 7767 7768 7769 7770 7771

			intel_encoder = to_intel_encoder(connector->encoder);
			intel_encoder->connectors_active = true;
		}
	}

}

7772 7773 7774 7775 7776 7777
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
	list_for_each_entry((intel_crtc), \
			    &(dev)->mode_config.crtc_list, \
			    base.head) \
		if (mask & (1 <<(intel_crtc)->pipe)) \

7778 7779 7780 7781
static bool
intel_pipe_config_compare(struct intel_crtc_config *current_config,
			  struct intel_crtc_config *pipe_config)
{
7782 7783 7784 7785 7786 7787 7788 7789
	if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
		DRM_ERROR("mismatch in has_pch_encoder "
			  "(expected %i, found %i)\n",
			  current_config->has_pch_encoder,
			  pipe_config->has_pch_encoder);
		return false;
	}

7790 7791 7792
	return true;
}

7793
void
7794 7795
intel_modeset_check_state(struct drm_device *dev)
{
7796
	drm_i915_private_t *dev_priv = dev->dev_private;
7797 7798 7799
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7800
	struct intel_crtc_config pipe_config;
7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861 7862 7863 7864 7865 7866 7867 7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* This also checks the encoder/connector hw state with the
		 * ->get_hw_state callbacks. */
		intel_connector_check_state(connector);

		WARN(&connector->new_encoder->base != connector->base.encoder,
		     "connector's staged encoder doesn't match current encoder\n");
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		bool enabled = false;
		bool active = false;
		enum pipe pipe, tracked_pipe;

		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		WARN(&encoder->new_crtc->base != encoder->base.crtc,
		     "encoder's stage crtc doesn't match current crtc\n");
		WARN(encoder->connectors_active && !encoder->base.crtc,
		     "encoder's active_connectors set, but no crtc\n");

		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->base.encoder != &encoder->base)
				continue;
			enabled = true;
			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
				active = true;
		}
		WARN(!!encoder->base.crtc != enabled,
		     "encoder's enabled state mismatch "
		     "(expected %i, found %i)\n",
		     !!encoder->base.crtc, enabled);
		WARN(active && !encoder->base.crtc,
		     "active encoder with no crtc\n");

		WARN(encoder->connectors_active != active,
		     "encoder's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, encoder->connectors_active);

		active = encoder->get_hw_state(encoder, &pipe);
		WARN(active != encoder->connectors_active,
		     "encoder's hw state doesn't match sw tracking "
		     "(expected %i, found %i)\n",
		     encoder->connectors_active, active);

		if (!encoder->base.crtc)
			continue;

		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		WARN(active && pipe != tracked_pipe,
		     "active encoder's pipe doesn't match"
		     "(expected %i, found %i)\n",
		     tracked_pipe, pipe);

	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool enabled = false;
		bool active = false;

		DRM_DEBUG_KMS("[CRTC:%d]\n",
			      crtc->base.base.id);

		WARN(crtc->active && !crtc->base.enabled,
		     "active crtc, but not enabled in sw tracking\n");

		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->base.crtc != &crtc->base)
				continue;
			enabled = true;
			if (encoder->connectors_active)
				active = true;
		}
		WARN(active != crtc->active,
		     "crtc's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, crtc->active);
		WARN(enabled != crtc->base.enabled,
		     "crtc's computed enabled state doesn't match tracked enabled state "
		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);

7889
		memset(&pipe_config, 0, sizeof(pipe_config));
7890 7891 7892 7893 7894 7895 7896 7897 7898
		active = dev_priv->display.get_pipe_config(crtc,
							   &pipe_config);
		WARN(crtc->active != active,
		     "crtc active state doesn't match with hw state "
		     "(expected %i, found %i)\n", crtc->active, active);

		WARN(active &&
		     !intel_pipe_config_compare(&crtc->config, &pipe_config),
		     "pipe state doesn't match!\n");
7899 7900 7901
	}
}

7902 7903 7904
int intel_set_mode(struct drm_crtc *crtc,
		   struct drm_display_mode *mode,
		   int x, int y, struct drm_framebuffer *fb)
7905 7906
{
	struct drm_device *dev = crtc->dev;
7907
	drm_i915_private_t *dev_priv = dev->dev_private;
7908 7909
	struct drm_display_mode *saved_mode, *saved_hwmode;
	struct intel_crtc_config *pipe_config = NULL;
7910 7911
	struct intel_crtc *intel_crtc;
	unsigned disable_pipes, prepare_pipes, modeset_pipes;
7912
	int ret = 0;
7913

7914
	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7915 7916
	if (!saved_mode)
		return -ENOMEM;
7917
	saved_hwmode = saved_mode + 1;
7918

7919
	intel_modeset_affected_pipes(crtc, &modeset_pipes,
7920 7921
				     &prepare_pipes, &disable_pipes);

7922 7923
	*saved_hwmode = crtc->hwmode;
	*saved_mode = crtc->mode;
7924

7925 7926 7927 7928 7929 7930
	/* Hack: Because we don't (yet) support global modeset on multiple
	 * crtcs, we don't keep track of the new mode for more than one crtc.
	 * Hence simply check whether any bit is set in modeset_pipes in all the
	 * pieces of code that are not yet converted to deal with mutliple crtcs
	 * changing their mode at the same time. */
	if (modeset_pipes) {
7931
		pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7932 7933 7934 7935
		if (IS_ERR(pipe_config)) {
			ret = PTR_ERR(pipe_config);
			pipe_config = NULL;

7936
			goto out;
7937 7938
		}
	}
7939

7940 7941 7942 7943 7944 7945
	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		      modeset_pipes, prepare_pipes, disable_pipes);

	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		intel_crtc_disable(&intel_crtc->base);

7946 7947 7948 7949
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		if (intel_crtc->base.enabled)
			dev_priv->display.crtc_disable(&intel_crtc->base);
	}
7950

7951 7952
	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
	 * to set it here already despite that we pass it down the callchain.
7953
	 */
7954
	if (modeset_pipes) {
7955
		crtc->mode = *mode;
7956 7957 7958 7959
		/* mode_set/enable/disable functions rely on a correct pipe
		 * config. */
		to_intel_crtc(crtc)->config = *pipe_config;
	}
7960

7961 7962 7963
	/* Only after disabling all output pipelines that will be changed can we
	 * update the the output configuration. */
	intel_modeset_update_state(dev, prepare_pipes);
7964

7965 7966 7967
	if (dev_priv->display.modeset_global_resources)
		dev_priv->display.modeset_global_resources(dev);

7968 7969
	/* Set up the DPLL and any encoders state that needs to adjust or depend
	 * on the DPLL.
7970
	 */
7971
	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7972 7973 7974 7975
		ret = intel_crtc_mode_set(&intel_crtc->base,
					  x, y, fb);
		if (ret)
			goto done;
7976 7977 7978
	}

	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7979 7980
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		dev_priv->display.crtc_enable(&intel_crtc->base);
7981

7982 7983
	if (modeset_pipes) {
		/* Store real post-adjustment hardware mode. */
7984
		crtc->hwmode = pipe_config->adjusted_mode;
7985

7986 7987 7988 7989 7990 7991
		/* Calculate and store various constants which
		 * are later needed by vblank and swap-completion
		 * timestamping. They are derived from true hwmode.
		 */
		drm_calc_timestamping_constants(crtc);
	}
7992 7993 7994

	/* FIXME: add subpixel order */
done:
7995
	if (ret && crtc->enabled) {
7996 7997
		crtc->hwmode = *saved_hwmode;
		crtc->mode = *saved_mode;
7998 7999
	} else {
		intel_modeset_check_state(dev);
8000 8001
	}

8002
out:
8003
	kfree(pipe_config);
8004
	kfree(saved_mode);
8005
	return ret;
8006 8007
}

8008 8009 8010 8011 8012
void intel_crtc_restore_mode(struct drm_crtc *crtc)
{
	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
}

8013 8014
#undef for_each_intel_crtc_masked

8015 8016 8017 8018 8019
static void intel_set_config_free(struct intel_set_config *config)
{
	if (!config)
		return;

8020 8021
	kfree(config->save_connector_encoders);
	kfree(config->save_encoder_crtcs);
8022 8023 8024
	kfree(config);
}

8025 8026 8027 8028 8029 8030 8031
static int intel_set_config_save_state(struct drm_device *dev,
				       struct intel_set_config *config)
{
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	int count;

8032 8033 8034 8035
	config->save_encoder_crtcs =
		kcalloc(dev->mode_config.num_encoder,
			sizeof(struct drm_crtc *), GFP_KERNEL);
	if (!config->save_encoder_crtcs)
8036 8037
		return -ENOMEM;

8038 8039 8040 8041
	config->save_connector_encoders =
		kcalloc(dev->mode_config.num_connector,
			sizeof(struct drm_encoder *), GFP_KERNEL);
	if (!config->save_connector_encoders)
8042 8043 8044 8045 8046 8047 8048 8049
		return -ENOMEM;

	/* Copy data. Note that driver private data is not affected.
	 * Should anything bad happen only the expected state is
	 * restored, not the drivers personal bookkeeping.
	 */
	count = 0;
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8050
		config->save_encoder_crtcs[count++] = encoder->crtc;
8051 8052 8053 8054
	}

	count = 0;
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8055
		config->save_connector_encoders[count++] = connector->encoder;
8056 8057 8058 8059 8060 8061 8062 8063
	}

	return 0;
}

static void intel_set_config_restore_state(struct drm_device *dev,
					   struct intel_set_config *config)
{
8064 8065
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8066 8067 8068
	int count;

	count = 0;
8069 8070 8071
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->new_crtc =
			to_intel_crtc(config->save_encoder_crtcs[count++]);
8072 8073 8074
	}

	count = 0;
8075 8076 8077
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		connector->new_encoder =
			to_intel_encoder(config->save_connector_encoders[count++]);
8078 8079 8080
	}
}

8081 8082 8083 8084 8085 8086 8087 8088 8089 8090 8091 8092 8093 8094
static void
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
				      struct intel_set_config *config)
{

	/* We should be able to check here if the fb has the same properties
	 * and then just flip_or_move it */
	if (set->crtc->fb != set->fb) {
		/* If we have no fb then treat it as a full mode set */
		if (set->crtc->fb == NULL) {
			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
			config->mode_changed = true;
		} else if (set->fb == NULL) {
			config->mode_changed = true;
8095 8096
		} else if (set->fb->pixel_format !=
			   set->crtc->fb->pixel_format) {
8097 8098 8099 8100 8101
			config->mode_changed = true;
		} else
			config->fb_changed = true;
	}

8102
	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8103 8104 8105 8106 8107 8108 8109 8110 8111 8112
		config->fb_changed = true;

	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		DRM_DEBUG_KMS("modes are different, full mode set\n");
		drm_mode_debug_printmodeline(&set->crtc->mode);
		drm_mode_debug_printmodeline(set->mode);
		config->mode_changed = true;
	}
}

8113
static int
8114 8115 8116
intel_modeset_stage_output_state(struct drm_device *dev,
				 struct drm_mode_set *set,
				 struct intel_set_config *config)
8117
{
8118
	struct drm_crtc *new_crtc;
8119 8120
	struct intel_connector *connector;
	struct intel_encoder *encoder;
8121
	int count, ro;
8122

8123
	/* The upper layers ensure that we either disable a crtc or have a list
8124 8125 8126 8127
	 * of connectors. For paranoia, double-check this. */
	WARN_ON(!set->fb && (set->num_connectors != 0));
	WARN_ON(set->fb && (set->num_connectors == 0));

8128
	count = 0;
8129 8130 8131 8132
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* Otherwise traverse passed in connector list and get encoders
		 * for them. */
8133
		for (ro = 0; ro < set->num_connectors; ro++) {
8134 8135
			if (set->connectors[ro] == &connector->base) {
				connector->new_encoder = connector->encoder;
8136 8137 8138 8139
				break;
			}
		}

8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154
		/* If we disable the crtc, disable all its connectors. Also, if
		 * the connector is on the changing crtc but not on the new
		 * connector list, disable it. */
		if ((!set->fb || ro == set->num_connectors) &&
		    connector->base.encoder &&
		    connector->base.encoder->crtc == set->crtc) {
			connector->new_encoder = NULL;

			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
				connector->base.base.id,
				drm_get_connector_name(&connector->base));
		}


		if (&connector->new_encoder->base != connector->base.encoder) {
8155
			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8156
			config->mode_changed = true;
8157 8158
		}
	}
8159
	/* connector->new_encoder is now updated for all connectors. */
8160

8161
	/* Update crtc of enabled connectors. */
8162
	count = 0;
8163 8164 8165
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (!connector->new_encoder)
8166 8167
			continue;

8168
		new_crtc = connector->new_encoder->base.crtc;
8169 8170

		for (ro = 0; ro < set->num_connectors; ro++) {
8171
			if (set->connectors[ro] == &connector->base)
8172 8173 8174 8175
				new_crtc = set->crtc;
		}

		/* Make sure the new CRTC will work with the encoder */
8176 8177
		if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
					   new_crtc)) {
8178
			return -EINVAL;
8179
		}
8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204
		connector->encoder->new_crtc = to_intel_crtc(new_crtc);

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
			connector->base.base.id,
			drm_get_connector_name(&connector->base),
			new_crtc->base.id);
	}

	/* Check for any encoders that needs to be disabled. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->new_encoder == encoder) {
				WARN_ON(!connector->new_encoder->new_crtc);

				goto next_encoder;
			}
		}
		encoder->new_crtc = NULL;
next_encoder:
		/* Only now check for crtc changes so we don't miss encoders
		 * that will be disabled. */
		if (&encoder->new_crtc->base != encoder->base.crtc) {
8205
			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8206
			config->mode_changed = true;
8207 8208
		}
	}
8209
	/* Now we've also updated encoder->new_crtc for all encoders. */
8210

8211 8212 8213 8214 8215 8216 8217 8218 8219 8220
	return 0;
}

static int intel_crtc_set_config(struct drm_mode_set *set)
{
	struct drm_device *dev;
	struct drm_mode_set save_set;
	struct intel_set_config *config;
	int ret;

8221 8222 8223
	BUG_ON(!set);
	BUG_ON(!set->crtc);
	BUG_ON(!set->crtc->helper_private);
8224

8225 8226 8227
	/* Enforce sane interface api - has been abused by the fb helper. */
	BUG_ON(!set->mode && set->fb);
	BUG_ON(set->fb && set->num_connectors == 0);
8228

8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259
	if (set->fb) {
		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
				set->crtc->base.id, set->fb->base.id,
				(int)set->num_connectors, set->x, set->y);
	} else {
		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
	}

	dev = set->crtc->dev;

	ret = -ENOMEM;
	config = kzalloc(sizeof(*config), GFP_KERNEL);
	if (!config)
		goto out_config;

	ret = intel_set_config_save_state(dev, config);
	if (ret)
		goto out_config;

	save_set.crtc = set->crtc;
	save_set.mode = &set->crtc->mode;
	save_set.x = set->crtc->x;
	save_set.y = set->crtc->y;
	save_set.fb = set->crtc->fb;

	/* Compute whether we need a full modeset, only an fb base update or no
	 * change at all. In the future we might also check whether only the
	 * mode changed, e.g. for LVDS where we only change the panel fitter in
	 * such cases. */
	intel_set_config_compute_mode_changes(set, config);

8260
	ret = intel_modeset_stage_output_state(dev, set, config);
8261 8262 8263
	if (ret)
		goto fail;

8264
	if (config->mode_changed) {
8265
		if (set->mode) {
8266 8267 8268
			DRM_DEBUG_KMS("attempting to set mode from"
					" userspace\n");
			drm_mode_debug_printmodeline(set->mode);
8269 8270
		}

8271 8272 8273 8274 8275
		ret = intel_set_mode(set->crtc, set->mode,
				     set->x, set->y, set->fb);
		if (ret) {
			DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
				  set->crtc->base.id, ret);
8276 8277
			goto fail;
		}
8278
	} else if (config->fb_changed) {
8279 8280
		intel_crtc_wait_for_pending_flips(set->crtc);

D
Daniel Vetter 已提交
8281
		ret = intel_pipe_set_base(set->crtc,
8282
					  set->x, set->y, set->fb);
8283 8284
	}

8285 8286
	intel_set_config_free(config);

8287 8288 8289
	return 0;

fail:
8290
	intel_set_config_restore_state(dev, config);
8291 8292

	/* Try to restore the config */
8293
	if (config->mode_changed &&
8294 8295
	    intel_set_mode(save_set.crtc, save_set.mode,
			   save_set.x, save_set.y, save_set.fb))
8296 8297
		DRM_ERROR("failed to restore config after modeset failure\n");

8298 8299
out_config:
	intel_set_config_free(config);
8300 8301
	return ret;
}
8302 8303 8304 8305 8306

static const struct drm_crtc_funcs intel_crtc_funcs = {
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
8307
	.set_config = intel_crtc_set_config,
8308 8309 8310 8311
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

P
Paulo Zanoni 已提交
8312 8313
static void intel_cpu_pll_init(struct drm_device *dev)
{
P
Paulo Zanoni 已提交
8314
	if (HAS_DDI(dev))
P
Paulo Zanoni 已提交
8315 8316 8317
		intel_ddi_pll_init(dev);
}

8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334
static void intel_pch_pll_init(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->num_pch_pll == 0) {
		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		return;
	}

	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
	}
}

8335
static void intel_crtc_init(struct drm_device *dev, int pipe)
J
Jesse Barnes 已提交
8336
{
J
Jesse Barnes 已提交
8337
	drm_i915_private_t *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
8338 8339 8340 8341 8342 8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

8354 8355 8356
	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
P
Paulo Zanoni 已提交
8357
	intel_crtc->cpu_transcoder = pipe;
8358
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8359
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8360
		intel_crtc->plane = !pipe;
8361 8362
	}

J
Jesse Barnes 已提交
8363 8364 8365 8366 8367
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

J
Jesse Barnes 已提交
8368 8369 8370
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
}

8371
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8372
				struct drm_file *file)
8373 8374
{
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8375 8376
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
8377

8378 8379
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
8380

8381 8382
	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);
8383

8384
	if (!drmmode_obj) {
8385 8386 8387 8388
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

8389 8390
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;
8391

8392
	return 0;
8393 8394
}

8395
static int intel_encoder_clones(struct intel_encoder *encoder)
J
Jesse Barnes 已提交
8396
{
8397 8398
	struct drm_device *dev = encoder->base.dev;
	struct intel_encoder *source_encoder;
J
Jesse Barnes 已提交
8399 8400 8401
	int index_mask = 0;
	int entry = 0;

8402 8403 8404 8405
	list_for_each_entry(source_encoder,
			    &dev->mode_config.encoder_list, base.head) {

		if (encoder == source_encoder)
J
Jesse Barnes 已提交
8406
			index_mask |= (1 << entry);
8407 8408 8409 8410 8411

		/* Intel hw has only one MUX where enocoders could be cloned. */
		if (encoder->cloneable && source_encoder->cloneable)
			index_mask |= (1 << entry);

J
Jesse Barnes 已提交
8412 8413
		entry++;
	}
8414

J
Jesse Barnes 已提交
8415 8416 8417
	return index_mask;
}

8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434
static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

J
Jesse Barnes 已提交
8435 8436
static void intel_setup_outputs(struct drm_device *dev)
{
8437
	struct drm_i915_private *dev_priv = dev->dev_private;
8438
	struct intel_encoder *encoder;
8439
	bool dpd_is_edp = false;
8440
	bool has_lvds;
J
Jesse Barnes 已提交
8441

8442
	has_lvds = intel_lvds_init(dev);
8443 8444 8445 8446
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		/* disable the panel fitter on everything but LVDS */
		I915_WRITE(PFIT_CONTROL, 0);
	}
J
Jesse Barnes 已提交
8447

P
Paulo Zanoni 已提交
8448
	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8449
		intel_crt_init(dev);
8450

P
Paulo Zanoni 已提交
8451
	if (HAS_DDI(dev)) {
8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470
		int found;

		/* Haswell uses DDI functions to detect digital outputs */
		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		/* DDI A only supports eDP */
		if (found)
			intel_ddi_init(dev, PORT_A);

		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		 * register */
		found = I915_READ(SFUSE_STRAP);

		if (found & SFUSE_STRAP_DDIB_DETECTED)
			intel_ddi_init(dev, PORT_B);
		if (found & SFUSE_STRAP_DDIC_DETECTED)
			intel_ddi_init(dev, PORT_C);
		if (found & SFUSE_STRAP_DDID_DETECTED)
			intel_ddi_init(dev, PORT_D);
	} else if (HAS_PCH_SPLIT(dev)) {
8471
		int found;
8472 8473 8474 8475
		dpd_is_edp = intel_dpd_is_edp(dev);

		if (has_edp_a(dev))
			intel_dp_init(dev, DP_A, PORT_A);
8476

8477
		if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8478
			/* PCH SDVOB multiplex with HDMIB */
8479
			found = intel_sdvo_init(dev, PCH_SDVOB, true);
8480
			if (!found)
8481
				intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8482
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8483
				intel_dp_init(dev, PCH_DP_B, PORT_B);
8484 8485
		}

8486
		if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8487
			intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8488

8489
		if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8490
			intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8491

8492
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
8493
			intel_dp_init(dev, PCH_DP_C, PORT_C);
8494

8495
		if (I915_READ(PCH_DP_D) & DP_DETECTED)
8496
			intel_dp_init(dev, PCH_DP_D, PORT_D);
8497
	} else if (IS_VALLEYVIEW(dev)) {
8498
		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8499 8500
		if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8501

8502
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8503 8504
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
					PORT_B);
8505 8506
			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8507
		}
8508
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8509
		bool found = false;
8510

8511
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8512
			DRM_DEBUG_KMS("probing SDVOB\n");
8513
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8514 8515
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8516
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8517
			}
8518

8519 8520
			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_B\n");
8521
				intel_dp_init(dev, DP_B, PORT_B);
8522
			}
8523
		}
8524 8525 8526

		/* Before G4X SDVOC doesn't have its own detect register */

8527
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8528
			DRM_DEBUG_KMS("probing SDVOC\n");
8529
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8530
		}
8531

8532
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8533

8534 8535
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8536
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8537 8538 8539
			}
			if (SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_C\n");
8540
				intel_dp_init(dev, DP_C, PORT_C);
8541
			}
8542
		}
8543

8544 8545 8546
		if (SUPPORTS_INTEGRATED_DP(dev) &&
		    (I915_READ(DP_D) & DP_DETECTED)) {
			DRM_DEBUG_KMS("probing DP_D\n");
8547
			intel_dp_init(dev, DP_D, PORT_D);
8548
		}
8549
	} else if (IS_GEN2(dev))
J
Jesse Barnes 已提交
8550 8551
		intel_dvo_init(dev);

8552
	if (SUPPORTS_TV(dev))
J
Jesse Barnes 已提交
8553 8554
		intel_tv_init(dev);

8555 8556 8557
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
8558
			intel_encoder_clones(encoder);
J
Jesse Barnes 已提交
8559
	}
8560

P
Paulo Zanoni 已提交
8561
	intel_init_pch_refclk(dev);
8562 8563

	drm_helper_move_panel_connectors_to_head(dev);
J
Jesse Barnes 已提交
8564 8565 8566 8567 8568 8569 8570
}

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

	drm_framebuffer_cleanup(fb);
8571
	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
J
Jesse Barnes 已提交
8572 8573 8574 8575 8576

	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8577
						struct drm_file *file,
J
Jesse Barnes 已提交
8578 8579 8580
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8581
	struct drm_i915_gem_object *obj = intel_fb->obj;
J
Jesse Barnes 已提交
8582

8583
	return drm_gem_handle_create(file, &obj->base, handle);
J
Jesse Barnes 已提交
8584 8585 8586 8587 8588 8589 8590
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

8591 8592
int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
8593
			   struct drm_mode_fb_cmd2 *mode_cmd,
8594
			   struct drm_i915_gem_object *obj)
J
Jesse Barnes 已提交
8595 8596 8597
{
	int ret;

8598 8599
	if (obj->tiling_mode == I915_TILING_Y) {
		DRM_DEBUG("hardware does not support tiling Y\n");
8600
		return -EINVAL;
8601
	}
8602

8603 8604 8605
	if (mode_cmd->pitches[0] & 63) {
		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
			  mode_cmd->pitches[0]);
8606
		return -EINVAL;
8607
	}
8608

8609
	/* FIXME <= Gen4 stride limits are bit unclear */
8610 8611 8612
	if (mode_cmd->pitches[0] > 32768) {
		DRM_DEBUG("pitch (%d) must be at less than 32768\n",
			  mode_cmd->pitches[0]);
8613
		return -EINVAL;
8614
	}
8615 8616

	if (obj->tiling_mode != I915_TILING_NONE &&
8617 8618 8619
	    mode_cmd->pitches[0] != obj->stride) {
		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
			  mode_cmd->pitches[0], obj->stride);
8620
		return -EINVAL;
8621
	}
8622

8623
	/* Reject formats not supported by any plane early. */
8624
	switch (mode_cmd->pixel_format) {
8625
	case DRM_FORMAT_C8:
V
Ville Syrjälä 已提交
8626 8627 8628
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
8629 8630 8631
		break;
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
8632 8633
		if (INTEL_INFO(dev)->gen > 3) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8634
			return -EINVAL;
8635
		}
8636 8637 8638
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
V
Ville Syrjälä 已提交
8639 8640
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
8641 8642
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
8643 8644
		if (INTEL_INFO(dev)->gen < 4) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8645
			return -EINVAL;
8646
		}
8647
		break;
V
Ville Syrjälä 已提交
8648 8649 8650 8651
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_VYUY:
8652 8653
		if (INTEL_INFO(dev)->gen < 5) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8654
			return -EINVAL;
8655
		}
8656 8657
		break;
	default:
8658
		DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8659 8660 8661
		return -EINVAL;
	}

8662 8663 8664 8665
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
	if (mode_cmd->offsets[0] != 0)
		return -EINVAL;

8666 8667 8668
	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;

J
Jesse Barnes 已提交
8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
8681
			      struct drm_mode_fb_cmd2 *mode_cmd)
J
Jesse Barnes 已提交
8682
{
8683
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
8684

8685 8686
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
						mode_cmd->handles[0]));
8687
	if (&obj->base == NULL)
8688
		return ERR_PTR(-ENOENT);
J
Jesse Barnes 已提交
8689

8690
	return intel_framebuffer_create(dev, mode_cmd, obj);
J
Jesse Barnes 已提交
8691 8692 8693 8694
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
8695
	.output_poll_changed = intel_fb_output_poll_changed,
J
Jesse Barnes 已提交
8696 8697
};

8698 8699 8700 8701 8702
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

P
Paulo Zanoni 已提交
8703
	if (HAS_DDI(dev)) {
8704
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
P
Paulo Zanoni 已提交
8705
		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8706 8707
		dev_priv->display.crtc_enable = haswell_crtc_enable;
		dev_priv->display.crtc_disable = haswell_crtc_disable;
8708
		dev_priv->display.off = haswell_crtc_off;
P
Paulo Zanoni 已提交
8709 8710
		dev_priv->display.update_plane = ironlake_update_plane;
	} else if (HAS_PCH_SPLIT(dev)) {
8711
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8712
		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8713 8714
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
8715
		dev_priv->display.off = ironlake_crtc_off;
8716
		dev_priv->display.update_plane = ironlake_update_plane;
8717
	} else {
8718
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8719
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8720 8721
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
8722
		dev_priv->display.off = i9xx_crtc_off;
8723
		dev_priv->display.update_plane = i9xx_update_plane;
8724
	}
8725 8726

	/* Returns the core display clock speed */
J
Jesse Barnes 已提交
8727 8728 8729 8730
	if (IS_VALLEYVIEW(dev))
		dev_priv->display.get_display_clock_speed =
			valleyview_get_display_clock_speed;
	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8731 8732 8733 8734 8735
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
8736
	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8737 8738 8739 8740 8741 8742 8743 8744
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
8745
	else if (IS_I85X(dev))
8746 8747 8748 8749 8750 8751
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

8752
	if (HAS_PCH_SPLIT(dev)) {
8753
		if (IS_GEN5(dev)) {
8754
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8755
			dev_priv->display.write_eld = ironlake_write_eld;
8756
		} else if (IS_GEN6(dev)) {
8757
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8758
			dev_priv->display.write_eld = ironlake_write_eld;
8759 8760 8761
		} else if (IS_IVYBRIDGE(dev)) {
			/* FIXME: detect B0+ stepping and use auto training */
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8762
			dev_priv->display.write_eld = ironlake_write_eld;
8763 8764
			dev_priv->display.modeset_global_resources =
				ivb_modeset_global_resources;
8765 8766
		} else if (IS_HASWELL(dev)) {
			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8767
			dev_priv->display.write_eld = haswell_write_eld;
8768 8769
			dev_priv->display.modeset_global_resources =
				haswell_modeset_global_resources;
8770
		}
8771
	} else if (IS_G4X(dev)) {
8772
		dev_priv->display.write_eld = g4x_write_eld;
8773
	}
8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794

	/* Default just returns -ENODEV to indicate unsupported */
	dev_priv->display.queue_flip = intel_default_queue_flip;

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
		break;

	case 3:
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
		break;

	case 4:
	case 5:
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
		break;

	case 6:
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
		break;
8795 8796 8797
	case 7:
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
		break;
8798
	}
8799 8800
}

8801 8802 8803 8804 8805
/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
8806
static void quirk_pipea_force(struct drm_device *dev)
8807 8808 8809 8810
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8811
	DRM_INFO("applying pipe a force quirk\n");
8812 8813
}

8814 8815 8816 8817 8818 8819 8820
/*
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
 */
static void quirk_ssc_force_disable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8821
	DRM_INFO("applying lvds SSC disable quirk\n");
8822 8823
}

8824
/*
8825 8826
 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
 * brightness value
8827 8828 8829 8830 8831
 */
static void quirk_invert_brightness(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8832
	DRM_INFO("applying inverted panel brightness quirk\n");
8833 8834
}

8835 8836 8837 8838 8839 8840 8841
struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

8842 8843 8844 8845 8846 8847 8848 8849 8850 8851 8852 8853 8854 8855 8856 8857 8858 8859 8860 8861 8862 8863 8864 8865 8866 8867 8868 8869
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
struct intel_dmi_quirk {
	void (*hook)(struct drm_device *dev);
	const struct dmi_system_id (*dmi_id_list)[];
};

static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
{
	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
	return 1;
}

static const struct intel_dmi_quirk intel_dmi_quirks[] = {
	{
		.dmi_id_list = &(const struct dmi_system_id[]) {
			{
				.callback = intel_dmi_reverse_brightness,
				.ident = "NCR Corporation",
				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
				},
			},
			{ }  /* terminating entry */
		},
		.hook = quirk_invert_brightness,
	},
};

8870
static struct intel_quirk intel_quirks[] = {
8871
	/* HP Mini needs pipe A force quirk (LP: #322104) */
8872
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8873 8874 8875 8876 8877 8878 8879

	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

8880
	/* 830/845 need to leave pipe A & dpll A up */
8881
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8882
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8883 8884 8885

	/* Lenovo U160 cannot use SSC on LVDS */
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8886 8887 8888

	/* Sony Vaio Y cannot use SSC on LVDS */
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8889 8890 8891

	/* Acer Aspire 5734Z must invert backlight brightness */
	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8892 8893 8894

	/* Acer/eMachines G725 */
	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8895 8896 8897

	/* Acer/eMachines e725 */
	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8898 8899 8900

	/* Acer/Packard Bell NCL20 */
	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8901 8902 8903

	/* Acer Aspire 4736Z */
	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8904 8905 8906 8907 8908 8909 8910 8911 8912 8913 8914 8915 8916 8917 8918 8919 8920
};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
8921 8922 8923 8924
	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
			intel_dmi_quirks[i].hook(dev);
	}
8925 8926
}

8927 8928 8929 8930 8931
/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
8932
	u32 vga_reg = i915_vgacntrl_reg(dev);
8933 8934

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8935
	outb(SR01, VGA_SR_INDEX);
8936 8937 8938 8939 8940 8941 8942 8943 8944
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

8945 8946
void intel_modeset_init_hw(struct drm_device *dev)
{
8947
	intel_init_power_well(dev);
8948

8949 8950
	intel_prepare_ddi(dev);

8951 8952
	intel_init_clock_gating(dev);

8953
	mutex_lock(&dev->struct_mutex);
8954
	intel_enable_gt_powersave(dev);
8955
	mutex_unlock(&dev->struct_mutex);
8956 8957
}

J
Jesse Barnes 已提交
8958 8959
void intel_modeset_init(struct drm_device *dev)
{
8960
	struct drm_i915_private *dev_priv = dev->dev_private;
8961
	int i, j, ret;
J
Jesse Barnes 已提交
8962 8963 8964 8965 8966 8967

	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

8968 8969 8970
	dev->mode_config.preferred_depth = 24;
	dev->mode_config.prefer_shadow = 1;

8971
	dev->mode_config.funcs = &intel_mode_funcs;
J
Jesse Barnes 已提交
8972

8973 8974
	intel_init_quirks(dev);

8975 8976
	intel_init_pm(dev);

8977 8978
	intel_init_display(dev);

8979 8980 8981 8982
	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
8983 8984
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
J
Jesse Barnes 已提交
8985
	} else {
8986 8987
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
J
Jesse Barnes 已提交
8988
	}
B
Ben Widawsky 已提交
8989
	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
J
Jesse Barnes 已提交
8990

8991
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
8992 8993
		      INTEL_INFO(dev)->num_pipes,
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
J
Jesse Barnes 已提交
8994

8995
	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
J
Jesse Barnes 已提交
8996
		intel_crtc_init(dev, i);
8997 8998 8999 9000 9001 9002
		for (j = 0; j < dev_priv->num_plane; j++) {
			ret = intel_plane_init(dev, i, j);
			if (ret)
				DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
					      i, j, ret);
		}
J
Jesse Barnes 已提交
9003 9004
	}

P
Paulo Zanoni 已提交
9005
	intel_cpu_pll_init(dev);
9006 9007
	intel_pch_pll_init(dev);

9008 9009
	/* Just disable it once at startup */
	i915_disable_vga(dev);
J
Jesse Barnes 已提交
9010
	intel_setup_outputs(dev);
9011 9012 9013

	/* Just in case the BIOS is doing something questionable. */
	intel_disable_fbc(dev);
9014 9015
}

9016 9017 9018 9019 9020 9021 9022 9023 9024
static void
intel_connector_break_all_links(struct intel_connector *connector)
{
	connector->base.dpms = DRM_MODE_DPMS_OFF;
	connector->base.encoder = NULL;
	connector->encoder->connectors_active = false;
	connector->encoder->base.crtc = NULL;
}

9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048
static void intel_enable_pipe_a(struct drm_device *dev)
{
	struct intel_connector *connector;
	struct drm_connector *crt = NULL;
	struct intel_load_detect_pipe load_detect_temp;

	/* We can't just switch on the pipe A, we need to set things up with a
	 * proper mode and output configuration. As a gross hack, enable pipe A
	 * by enabling the load detect pipe once. */
	list_for_each_entry(connector,
			    &dev->mode_config.connector_list,
			    base.head) {
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
			crt = &connector->base;
			break;
		}
	}

	if (!crt)
		return;

	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		intel_release_load_detect_pipe(crt, &load_detect_temp);

9049

9050 9051
}

9052 9053 9054
static bool
intel_check_plane_mapping(struct intel_crtc *crtc)
{
9055 9056
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
9057 9058
	u32 reg, val;

9059
	if (INTEL_INFO(dev)->num_pipes == 1)
9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071
		return true;

	reg = DSPCNTR(!crtc->plane);
	val = I915_READ(reg);

	if ((val & DISPLAY_PLANE_ENABLE) &&
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		return false;

	return true;
}

9072 9073 9074 9075
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
9076
	u32 reg;
9077 9078

	/* Clear any frame start delays used for debugging left by the BIOS */
9079
	reg = PIPECONF(crtc->cpu_transcoder);
9080 9081 9082
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

	/* We need to sanitize the plane -> pipe mapping first because this will
9083 9084 9085
	 * disable the crtc (and hence change the state) if it is wrong. Note
	 * that gen4+ has a fixed plane -> pipe mapping.  */
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 9110 9111 9112
		struct intel_connector *connector;
		bool plane;

		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
			      crtc->base.base.id);

		/* Pipe has the wrong plane attached and the plane is active.
		 * Temporarily change the plane mapping and disable everything
		 * ...  */
		plane = crtc->plane;
		crtc->plane = !plane;
		dev_priv->display.crtc_disable(&crtc->base);
		crtc->plane = plane;

		/* ... and break all links. */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder->base.crtc != &crtc->base)
				continue;

			intel_connector_break_all_links(connector);
		}

		WARN_ON(crtc->active);
		crtc->base.enabled = false;
	}

9113 9114 9115 9116 9117 9118 9119 9120 9121
	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
	    crtc->pipe == PIPE_A && !crtc->active) {
		/* BIOS forgot to enable pipe A, this mostly happens after
		 * resume. Force-enable the pipe to fix this, the update_dpms
		 * call below we restore the pipe to the right state, but leave
		 * the required bits on. */
		intel_enable_pipe_a(dev);
	}

9122 9123 9124 9125 9126 9127 9128 9129 9130 9131 9132 9133 9134 9135 9136 9137 9138 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 9151 9152 9153 9154 9155 9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 9178 9179 9180 9181 9182 9183 9184 9185 9186 9187 9188 9189 9190 9191 9192 9193 9194 9195
	/* Adjust the state of the output pipe according to whether we
	 * have active connectors/encoders. */
	intel_crtc_update_dpms(&crtc->base);

	if (crtc->active != crtc->base.enabled) {
		struct intel_encoder *encoder;

		/* This can happen either due to bugs in the get_hw_state
		 * functions or because the pipe is force-enabled due to the
		 * pipe A quirk. */
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
			      crtc->base.base.id,
			      crtc->base.enabled ? "enabled" : "disabled",
			      crtc->active ? "enabled" : "disabled");

		crtc->base.enabled = crtc->active;

		/* Because we only establish the connector -> encoder ->
		 * crtc links if something is active, this means the
		 * crtc is now deactivated. Break the links. connector
		 * -> encoder links are only establish when things are
		 *  actually up, hence no need to break them. */
		WARN_ON(crtc->active);

		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
			WARN_ON(encoder->connectors_active);
			encoder->base.crtc = NULL;
		}
	}
}

static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
	struct intel_connector *connector;
	struct drm_device *dev = encoder->base.dev;

	/* We need to check both for a crtc link (meaning that the
	 * encoder is active and trying to read from a pipe) and the
	 * pipe itself being active. */
	bool has_active_crtc = encoder->base.crtc &&
		to_intel_crtc(encoder->base.crtc)->active;

	if (encoder->connectors_active && !has_active_crtc) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		/* Connector is active, but has no active pipe. This is
		 * fallout from our resume register restoring. Disable
		 * the encoder manually again. */
		if (encoder->base.crtc) {
			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
				      encoder->base.base.id,
				      drm_get_encoder_name(&encoder->base));
			encoder->disable(encoder);
		}

		/* Inconsistent output/port/pipe state happens presumably due to
		 * a bug in one of the get_hw_state functions. Or someplace else
		 * in our code, like the register restore mess on resume. Clamp
		 * things to off as a safer default. */
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder != encoder)
				continue;

			intel_connector_break_all_links(connector);
		}
	}
	/* Enabled encoders without active connectors will be fixed in
	 * the crtc fixup. */
}

9196
void i915_redisable_vga(struct drm_device *dev)
9197 9198
{
	struct drm_i915_private *dev_priv = dev->dev_private;
9199
	u32 vga_reg = i915_vgacntrl_reg(dev);
9200 9201 9202

	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9203
		i915_disable_vga(dev);
9204 9205 9206
	}
}

9207 9208
/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
 * and i915 state tracking structures. */
9209 9210
void intel_modeset_setup_hw_state(struct drm_device *dev,
				  bool force_restore)
9211 9212 9213 9214
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	u32 tmp;
9215
	struct drm_plane *plane;
9216 9217 9218 9219
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;

P
Paulo Zanoni 已提交
9220
	if (HAS_DDI(dev)) {
9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));

		if (tmp & TRANS_DDI_FUNC_ENABLE) {
			switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
			case TRANS_DDI_EDP_INPUT_A_ON:
			case TRANS_DDI_EDP_INPUT_A_ONOFF:
				pipe = PIPE_A;
				break;
			case TRANS_DDI_EDP_INPUT_B_ONOFF:
				pipe = PIPE_B;
				break;
			case TRANS_DDI_EDP_INPUT_C_ONOFF:
				pipe = PIPE_C;
				break;
9235 9236 9237 9238 9239 9240 9241
			default:
				/* A bogus value has been programmed, disable
				 * the transcoder */
				WARN(1, "Bogus eDP source %08x\n", tmp);
				intel_ddi_disable_transcoder_func(dev_priv,
						TRANSCODER_EDP);
				goto setup_pipes;
9242 9243 9244 9245 9246 9247 9248 9249 9250 9251
			}

			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
			crtc->cpu_transcoder = TRANSCODER_EDP;

			DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
				      pipe_name(pipe));
		}
	}

9252
setup_pipes:
9253 9254
	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
9255
		memset(&crtc->config, 0, sizeof(crtc->config));
9256 9257
		crtc->active = dev_priv->display.get_pipe_config(crtc,
								 &crtc->config);
9258 9259 9260 9261 9262 9263 9264 9265

		crtc->base.enabled = crtc->active;

		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
			      crtc->base.base.id,
			      crtc->active ? "enabled" : "disabled");
	}

P
Paulo Zanoni 已提交
9266
	if (HAS_DDI(dev))
9267 9268
		intel_ddi_setup_hw_pll_state(dev);

9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289 9290 9291 9292 9293 9294 9295 9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		pipe = 0;

		if (encoder->get_hw_state(encoder, &pipe)) {
			encoder->base.crtc =
				dev_priv->pipe_to_crtc_mapping[pipe];
		} else {
			encoder->base.crtc = NULL;
		}

		encoder->connectors_active = false;
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base),
			      encoder->base.crtc ? "enabled" : "disabled",
			      pipe);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->get_hw_state(connector)) {
			connector->base.dpms = DRM_MODE_DPMS_ON;
			connector->encoder->connectors_active = true;
			connector->base.encoder = &connector->encoder->base;
		} else {
			connector->base.dpms = DRM_MODE_DPMS_OFF;
			connector->base.encoder = NULL;
		}
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base),
			      connector->base.encoder ? "enabled" : "disabled");
	}

	/* HW state is read out, now we need to sanitize this mess. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		intel_sanitize_encoder(encoder);
	}

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		intel_sanitize_crtc(crtc);
	}
9314

9315 9316
	if (force_restore) {
		for_each_pipe(pipe) {
9317 9318 9319
			struct drm_crtc *crtc =
				dev_priv->pipe_to_crtc_mapping[pipe];
			intel_crtc_restore_mode(crtc);
9320
		}
9321 9322
		list_for_each_entry(plane, &dev->mode_config.plane_list, head)
			intel_plane_restore(plane);
9323 9324

		i915_redisable_vga(dev);
9325 9326 9327
	} else {
		intel_modeset_update_staged_output_state(dev);
	}
9328 9329

	intel_modeset_check_state(dev);
9330 9331

	drm_mode_config_reset(dev);
9332 9333 9334 9335
}

void intel_modeset_gem_init(struct drm_device *dev)
{
9336
	intel_modeset_init_hw(dev);
9337 9338

	intel_setup_overlay(dev);
9339

9340
	intel_modeset_setup_hw_state(dev, false);
J
Jesse Barnes 已提交
9341 9342 9343 9344
}

void intel_modeset_cleanup(struct drm_device *dev)
{
9345 9346 9347 9348
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

9349
	drm_kms_helper_poll_fini(dev);
9350 9351
	mutex_lock(&dev->struct_mutex);

J
Jesse Barnes 已提交
9352 9353 9354
	intel_unregister_dsm_handler();


9355 9356 9357 9358 9359 9360
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
9361
		intel_increase_pllclock(crtc);
9362 9363
	}

9364
	intel_disable_fbc(dev);
9365

9366
	intel_disable_gt_powersave(dev);
9367

9368 9369
	ironlake_teardown_rc6(dev);

J
Jesse Barnes 已提交
9370 9371 9372
	if (IS_VALLEYVIEW(dev))
		vlv_init_dpio(dev);

9373 9374
	mutex_unlock(&dev->struct_mutex);

9375 9376 9377 9378
	/* Disable the irq before mode object teardown, for the irq might
	 * enqueue unpin/hotplug work. */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);
9379
	cancel_work_sync(&dev_priv->rps.work);
9380

9381 9382 9383
	/* flush any delayed tasks or pending work */
	flush_scheduled_work();

J
Jesse Barnes 已提交
9384
	drm_mode_config_cleanup(dev);
9385 9386

	intel_cleanup_overlay(dev);
J
Jesse Barnes 已提交
9387 9388
}

9389 9390 9391
/*
 * Return which encoder is currently attached for connector.
 */
9392
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
J
Jesse Barnes 已提交
9393
{
9394 9395
	return &intel_attached_encoder(connector)->base;
}
9396

9397 9398 9399 9400 9401 9402
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
J
Jesse Barnes 已提交
9403
}
9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420

/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}
9421 9422 9423 9424 9425 9426 9427 9428 9429 9430

#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

struct intel_display_error_state {
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
9431
	} cursor[I915_MAX_PIPES];
9432 9433 9434 9435 9436 9437 9438 9439 9440 9441 9442

	struct intel_pipe_error_state {
		u32 conf;
		u32 source;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
9443
	} pipe[I915_MAX_PIPES];
9444 9445 9446 9447 9448 9449 9450 9451 9452

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
9453
	} plane[I915_MAX_PIPES];
9454 9455 9456 9457 9458
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
9459
	drm_i915_private_t *dev_priv = dev->dev_private;
9460
	struct intel_display_error_state *error;
9461
	enum transcoder cpu_transcoder;
9462 9463 9464 9465 9466 9467
	int i;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

9468
	for_each_pipe(i) {
9469 9470
		cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);

9471 9472 9473 9474 9475 9476 9477 9478 9479
		if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
			error->cursor[i].control = I915_READ(CURCNTR(i));
			error->cursor[i].position = I915_READ(CURPOS(i));
			error->cursor[i].base = I915_READ(CURBASE(i));
		} else {
			error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
			error->cursor[i].position = I915_READ(CURPOS_IVB(i));
			error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		}
9480 9481 9482

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9483
		if (INTEL_INFO(dev)->gen <= 3) {
9484
			error->plane[i].size = I915_READ(DSPSIZE(i));
9485 9486
			error->plane[i].pos = I915_READ(DSPPOS(i));
		}
9487 9488
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
			error->plane[i].addr = I915_READ(DSPADDR(i));
9489 9490 9491 9492 9493
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

9494
		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9495
		error->pipe[i].source = I915_READ(PIPESRC(i));
9496 9497 9498 9499 9500 9501
		error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9502 9503 9504 9505 9506 9507 9508 9509 9510 9511 9512 9513
	}

	return error;
}

void
intel_display_print_error_state(struct seq_file *m,
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
	int i;

9514
	seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9515
	for_each_pipe(i) {
9516 9517 9518 9519 9520 9521 9522 9523 9524 9525 9526 9527 9528
		seq_printf(m, "Pipe [%d]:\n", i);
		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);

		seq_printf(m, "Plane [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9529
		if (INTEL_INFO(dev)->gen <= 3) {
9530
			seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9531 9532
			seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
		}
P
Paulo Zanoni 已提交
9533
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9534
			seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9535 9536 9537 9538 9539 9540 9541 9542 9543 9544 9545 9546
		if (INTEL_INFO(dev)->gen >= 4) {
			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
		}

		seq_printf(m, "Cursor [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
		seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
	}
}
#endif