omap_hsmmc.c 61.2 KB
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/*
 * drivers/mmc/host/omap_hsmmc.c
 *
 * Driver for OMAP2430/3430 MMC controller.
 *
 * Copyright (C) 2007 Texas Instruments.
 *
 * Authors:
 *	Syed Mohammed Khasim	<x0khasim@ti.com>
 *	Madhusudhan		<madhu.cr@ti.com>
 *	Mohit Jalori		<mjalori@ti.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/debugfs.h>
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#include <linux/dmaengine.h>
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#include <linux/seq_file.h>
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#include <linux/sizes.h>
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#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/timer.h>
#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
#include <linux/of_device.h>
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#include <linux/omap-dmaengine.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/mmc.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_data/hsmmc-omap.h>
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/* OMAP HSMMC Host Controller Registers */
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#define OMAP_HSMMC_SYSSTATUS	0x0014
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#define OMAP_HSMMC_CON		0x002C
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#define OMAP_HSMMC_SDMASA	0x0100
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#define OMAP_HSMMC_BLK		0x0104
#define OMAP_HSMMC_ARG		0x0108
#define OMAP_HSMMC_CMD		0x010C
#define OMAP_HSMMC_RSP10	0x0110
#define OMAP_HSMMC_RSP32	0x0114
#define OMAP_HSMMC_RSP54	0x0118
#define OMAP_HSMMC_RSP76	0x011C
#define OMAP_HSMMC_DATA		0x0120
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#define OMAP_HSMMC_PSTATE	0x0124
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#define OMAP_HSMMC_HCTL		0x0128
#define OMAP_HSMMC_SYSCTL	0x012C
#define OMAP_HSMMC_STAT		0x0130
#define OMAP_HSMMC_IE		0x0134
#define OMAP_HSMMC_ISE		0x0138
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#define OMAP_HSMMC_AC12		0x013C
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#define OMAP_HSMMC_CAPA		0x0140

#define VS18			(1 << 26)
#define VS30			(1 << 25)
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#define HSS			(1 << 21)
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#define SDVS18			(0x5 << 9)
#define SDVS30			(0x6 << 9)
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#define SDVS33			(0x7 << 9)
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#define SDVS_MASK		0x00000E00
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#define SDVSCLR			0xFFFFF1FF
#define SDVSDET			0x00000400
#define AUTOIDLE		0x1
#define SDBP			(1 << 8)
#define DTO			0xe
#define ICE			0x1
#define ICS			0x2
#define CEN			(1 << 2)
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#define CLKD_MAX		0x3FF		/* max clock divisor: 1023 */
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#define CLKD_MASK		0x0000FFC0
#define CLKD_SHIFT		6
#define DTO_MASK		0x000F0000
#define DTO_SHIFT		16
#define INIT_STREAM		(1 << 1)
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#define ACEN_ACMD23		(2 << 2)
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#define DP_SELECT		(1 << 21)
#define DDIR			(1 << 4)
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#define DMAE			0x1
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#define MSBS			(1 << 5)
#define BCE			(1 << 1)
#define FOUR_BIT		(1 << 1)
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#define HSPE			(1 << 2)
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#define IWE			(1 << 24)
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#define DDR			(1 << 19)
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#define CLKEXTFREE		(1 << 16)
#define CTPL			(1 << 11)
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#define DW8			(1 << 5)
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#define OD			0x1
#define STAT_CLEAR		0xFFFFFFFF
#define INIT_STREAM_CMD		0x00000000
#define DUAL_VOLT_OCR_BIT	7
#define SRC			(1 << 25)
#define SRD			(1 << 26)
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#define SOFTRESET		(1 << 1)
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/* PSTATE */
#define DLEV_DAT(x)		(1 << (20 + (x)))

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/* Interrupt masks for IE and ISE register */
#define CC_EN			(1 << 0)
#define TC_EN			(1 << 1)
#define BWR_EN			(1 << 4)
#define BRR_EN			(1 << 5)
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#define CIRQ_EN			(1 << 8)
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#define ERR_EN			(1 << 15)
#define CTO_EN			(1 << 16)
#define CCRC_EN			(1 << 17)
#define CEB_EN			(1 << 18)
#define CIE_EN			(1 << 19)
#define DTO_EN			(1 << 20)
#define DCRC_EN			(1 << 21)
#define DEB_EN			(1 << 22)
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#define ACE_EN			(1 << 24)
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#define CERR_EN			(1 << 28)
#define BADA_EN			(1 << 29)

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#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
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		DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
		BRR_EN | BWR_EN | TC_EN | CC_EN)

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#define CNI	(1 << 7)
#define ACIE	(1 << 4)
#define ACEB	(1 << 3)
#define ACCE	(1 << 2)
#define ACTO	(1 << 1)
#define ACNE	(1 << 0)

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#define MMC_AUTOSUSPEND_DELAY	100
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#define MMC_TIMEOUT_MS		20		/* 20 mSec */
#define MMC_TIMEOUT_US		20000		/* 20000 micro Sec */
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#define OMAP_MMC_MIN_CLOCK	400000
#define OMAP_MMC_MAX_CLOCK	52000000
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#define DRIVER_NAME		"omap_hsmmc"
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#define VDD_1V8			1800000		/* 180000 uV */
#define VDD_3V0			3000000		/* 300000 uV */
#define VDD_165_195		(ffs(MMC_VDD_165_195) - 1)

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/*
 * One controller can have multiple slots, like on some omap boards using
 * omap.c controller driver. Luckily this is not currently done on any known
 * omap_hsmmc.c device.
 */
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#define mmc_pdata(host)		host->pdata
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/*
 * MMC Host controller read/write API's
 */
#define OMAP_HSMMC_READ(base, reg)	\
	__raw_readl((base) + OMAP_HSMMC_##reg)

#define OMAP_HSMMC_WRITE(base, reg, val) \
	__raw_writel((val), (base) + OMAP_HSMMC_##reg)

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struct omap_hsmmc_next {
	unsigned int	dma_len;
	s32		cookie;
};

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struct omap_hsmmc_host {
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	struct	device		*dev;
	struct	mmc_host	*mmc;
	struct	mmc_request	*mrq;
	struct	mmc_command	*cmd;
	struct	mmc_data	*data;
	struct	clk		*fclk;
	struct	clk		*dbclk;
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	/*
	 * vcc == configured supply
	 * vcc_aux == optional
	 *   -	MMC1, supply for DAT4..DAT7
	 *   -	MMC2/MMC2, external level shifter voltage supply, for
	 *	chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
	 */
	struct	regulator	*vcc;
	struct	regulator	*vcc_aux;
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	struct	regulator	*pbias;
	bool			pbias_enabled;
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	void	__iomem		*base;
	resource_size_t		mapbase;
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	spinlock_t		irq_lock; /* Prevent races with irq handler */
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	unsigned int		dma_len;
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	unsigned int		dma_sg_idx;
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	unsigned char		bus_mode;
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	unsigned char		power_mode;
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	int			suspended;
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	u32			con;
	u32			hctl;
	u32			sysctl;
	u32			capa;
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	int			irq;
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	int			wake_irq;
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	int			use_dma, dma_ch;
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	struct dma_chan		*tx_chan;
	struct dma_chan		*rx_chan;
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	int			response_busy;
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	int			context_loss;
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	int			protect_card;
	int			reqs_blocked;
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	int			use_reg;
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	int			req_in_progress;
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	unsigned long		clk_rate;
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	unsigned int		flags;
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#define AUTO_CMD23		(1 << 0)        /* Auto CMD23 support */
#define HSMMC_SDIO_IRQ_ENABLED	(1 << 1)        /* SDIO irq enabled */
#define HSMMC_WAKE_IRQ_ENABLED	(1 << 2)
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	struct omap_hsmmc_next	next_data;
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	struct	omap_hsmmc_platform_data	*pdata;
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	/* To handle board related suspend/resume functionality for MMC */
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	int (*suspend)(struct device *dev);
	int (*resume)(struct device *dev);
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	/* return MMC cover switch state, can be NULL if not supported.
	 *
	 * possible return values:
	 *   0 - closed
	 *   1 - open
	 */
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	int (*get_cover_state)(struct device *dev);
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	/* Card detection IRQs */
	int card_detect_irq;

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	int (*card_detect)(struct device *dev);
	int (*get_ro)(struct device *dev);
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};

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struct omap_mmc_of_data {
	u32 reg_offset;
	u8 controller_flags;
};

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static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);

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static int omap_hsmmc_card_detect(struct device *dev)
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{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
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	struct omap_hsmmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes card detect signal is active-low */
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	return !gpio_get_value_cansleep(mmc->switch_pin);
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}

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static int omap_hsmmc_get_wp(struct device *dev)
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{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
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	struct omap_hsmmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes write protect signal is active-high */
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	return gpio_get_value_cansleep(mmc->gpio_wp);
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}

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static int omap_hsmmc_get_cover_state(struct device *dev)
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{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
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	struct omap_hsmmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes card detect signal is active-low */
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	return !gpio_get_value_cansleep(mmc->switch_pin);
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}

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#ifdef CONFIG_REGULATOR

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static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
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{
	struct omap_hsmmc_host *host =
		platform_get_drvdata(to_platform_device(dev));
	int ret = 0;

	/*
	 * If we don't see a Vcc regulator, assume it's a fixed
	 * voltage always-on regulator.
	 */
	if (!host->vcc)
		return 0;

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	if (mmc_pdata(host)->before_set_reg)
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		mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
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	if (host->pbias) {
		if (host->pbias_enabled == 1) {
			ret = regulator_disable(host->pbias);
			if (!ret)
				host->pbias_enabled = 0;
		}
		regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
	}

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	/*
	 * Assume Vcc regulator is used only to power the card ... OMAP
	 * VDDS is used to power the pins, optionally with a transceiver to
	 * support cards using voltages other than VDDS (1.8V nominal).  When a
	 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
	 *
	 * In some cases this regulator won't support enable/disable;
	 * e.g. it's a fixed rail for a WLAN chip.
	 *
	 * In other cases vcc_aux switches interface power.  Example, for
	 * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
	 * chips/cards need an interface voltage rail too.
	 */
	if (power_on) {
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		if (host->vcc)
			ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
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		/* Enable interface voltage rail, if needed */
		if (ret == 0 && host->vcc_aux) {
			ret = regulator_enable(host->vcc_aux);
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			if (ret < 0 && host->vcc)
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				ret = mmc_regulator_set_ocr(host->mmc,
							host->vcc, 0);
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		}
	} else {
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		/* Shut down the rail */
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		if (host->vcc_aux)
			ret = regulator_disable(host->vcc_aux);
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		if (host->vcc) {
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			/* Then proceed to shut down the local regulator */
			ret = mmc_regulator_set_ocr(host->mmc,
						host->vcc, 0);
		}
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	}

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	if (host->pbias) {
		if (vdd <= VDD_165_195)
			ret = regulator_set_voltage(host->pbias, VDD_1V8,
								VDD_1V8);
		else
			ret = regulator_set_voltage(host->pbias, VDD_3V0,
								VDD_3V0);
		if (ret < 0)
			goto error_set_power;

		if (host->pbias_enabled == 0) {
			ret = regulator_enable(host->pbias);
			if (!ret)
				host->pbias_enabled = 1;
		}
	}

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	if (mmc_pdata(host)->after_set_reg)
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		mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
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error_set_power:
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	return ret;
}

static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
{
	struct regulator *reg;
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	int ocr_value = 0;
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	reg = devm_regulator_get(host->dev, "vmmc");
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	if (IS_ERR(reg)) {
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		dev_err(host->dev, "unable to get vmmc regulator %ld\n",
			PTR_ERR(reg));
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		return PTR_ERR(reg);
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	} else {
		host->vcc = reg;
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		ocr_value = mmc_regulator_get_ocrmask(reg);
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		if (!mmc_pdata(host)->ocr_mask) {
			mmc_pdata(host)->ocr_mask = ocr_value;
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		} else {
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			if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
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				dev_err(host->dev, "ocrmask %x is not supported\n",
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					mmc_pdata(host)->ocr_mask);
				mmc_pdata(host)->ocr_mask = 0;
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				return -EINVAL;
			}
		}
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	}
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	mmc_pdata(host)->set_power = omap_hsmmc_set_power;
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	/* Allow an aux regulator */
	reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
	host->vcc_aux = IS_ERR(reg) ? NULL : reg;

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	reg = devm_regulator_get_optional(host->dev, "pbias");
	host->pbias = IS_ERR(reg) ? NULL : reg;

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	/* For eMMC do not power off when not in sleep state */
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	if (mmc_pdata(host)->no_regulator_off_init)
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		return 0;
	/*
	 * To disable boot_on regulator, enable regulator
	 * to increase usecount and then disable it.
	 */
	if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
	    (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
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		int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
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		mmc_pdata(host)->set_power(host->dev, 1, vdd);
		mmc_pdata(host)->set_power(host->dev, 0, 0);
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	}

	return 0;
}

static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
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	mmc_pdata(host)->set_power = NULL;
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}

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static inline int omap_hsmmc_have_reg(void)
{
	return 1;
}

#else

static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
{
	return -EINVAL;
}

static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
}

static inline int omap_hsmmc_have_reg(void)
{
	return 0;
}

#endif

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static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host,
				struct omap_hsmmc_platform_data *pdata)
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{
	int ret;

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	if (gpio_is_valid(pdata->switch_pin)) {
		if (pdata->cover)
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			host->get_cover_state =
				omap_hsmmc_get_cover_state;
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		else
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			host->card_detect = omap_hsmmc_card_detect;
		host->card_detect_irq =
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				gpio_to_irq(pdata->switch_pin);
		ret = gpio_request(pdata->switch_pin, "mmc_cd");
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		if (ret)
			return ret;
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		ret = gpio_direction_input(pdata->switch_pin);
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		if (ret)
			goto err_free_sp;
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	} else {
		pdata->switch_pin = -EINVAL;
	}
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	if (gpio_is_valid(pdata->gpio_wp)) {
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		host->get_ro = omap_hsmmc_get_wp;
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		ret = gpio_request(pdata->gpio_wp, "mmc_wp");
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		if (ret)
			goto err_free_cd;
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		ret = gpio_direction_input(pdata->gpio_wp);
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		if (ret)
			goto err_free_wp;
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	} else {
		pdata->gpio_wp = -EINVAL;
	}
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	return 0;

err_free_wp:
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	gpio_free(pdata->gpio_wp);
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err_free_cd:
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	if (gpio_is_valid(pdata->switch_pin))
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err_free_sp:
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		gpio_free(pdata->switch_pin);
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	return ret;
}

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static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host,
				 struct omap_hsmmc_platform_data *pdata)
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{
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	if (gpio_is_valid(pdata->gpio_wp))
		gpio_free(pdata->gpio_wp);
	if (gpio_is_valid(pdata->switch_pin))
		gpio_free(pdata->switch_pin);
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}

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/*
 * Start clock to the card
 */
static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
{
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
}

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/*
 * Stop clock to the card
 */
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static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
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{
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
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		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
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}

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static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
				  struct mmc_command *cmd)
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{
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	u32 irq_mask = INT_EN_MASK;
	unsigned long flags;
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	if (host->use_dma)
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		irq_mask &= ~(BRR_EN | BWR_EN);
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	/* Disable timeout for erases */
	if (cmd->opcode == MMC_ERASE)
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		irq_mask &= ~DTO_EN;
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	spin_lock_irqsave(&host->irq_lock, flags);
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	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
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	/* latch pending CIRQ, but don't signal MMC core */
	if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
		irq_mask |= CIRQ_EN;
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	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
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	spin_unlock_irqrestore(&host->irq_lock, flags);
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}

static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
{
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	u32 irq_mask = 0;
	unsigned long flags;

	spin_lock_irqsave(&host->irq_lock, flags);
	/* no transfer running but need to keep cirq if enabled */
	if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
		irq_mask |= CIRQ_EN;
	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
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	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
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	spin_unlock_irqrestore(&host->irq_lock, flags);
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}

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/* Calculate divisor for the given clock frequency */
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static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
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{
	u16 dsor = 0;

	if (ios->clock) {
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		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
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		if (dsor > CLKD_MAX)
			dsor = CLKD_MAX;
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	}

	return dsor;
}

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static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	unsigned long regval;
	unsigned long timeout;
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	unsigned long clkdiv;
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	dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
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	omap_hsmmc_stop_clock(host);

	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
	regval = regval & ~(CLKD_MASK | DTO_MASK);
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	clkdiv = calc_divisor(host, ios);
	regval = regval | (clkdiv << 6) | (DTO << 16);
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	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);

	/* Wait till the ICS bit is set */
	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
		&& time_before(jiffies, timeout))
		cpu_relax();

595 596 597 598 599 600 601 602 603
	/*
	 * Enable High-Speed Support
	 * Pre-Requisites
	 *	- Controller should support High-Speed-Enable Bit
	 *	- Controller should not be using DDR Mode
	 *	- Controller should advertise that it supports High Speed
	 *	  in capabilities register
	 *	- MMC/SD clock coming out of controller > 25MHz
	 */
604
	if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
605
	    (ios->timing != MMC_TIMING_MMC_DDR52) &&
606
	    (ios->timing != MMC_TIMING_UHS_DDR50) &&
607 608 609 610 611 612 613 614 615 616
	    ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
		regval = OMAP_HSMMC_READ(host->base, HCTL);
		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
			regval |= HSPE;
		else
			regval &= ~HSPE;

		OMAP_HSMMC_WRITE(host->base, HCTL, regval);
	}

617 618 619
	omap_hsmmc_start_clock(host);
}

620 621 622 623 624 625
static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	u32 con;

	con = OMAP_HSMMC_READ(host->base, CON);
626 627
	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
	    ios->timing == MMC_TIMING_UHS_DDR50)
B
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628 629 630
		con |= DDR;	/* configure in DDR mode */
	else
		con &= ~DDR;
631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659
	switch (ios->bus_width) {
	case MMC_BUS_WIDTH_8:
		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
		break;
	case MMC_BUS_WIDTH_4:
		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
		OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
		break;
	case MMC_BUS_WIDTH_1:
		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
		OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
		break;
	}
}

static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	u32 con;

	con = OMAP_HSMMC_READ(host->base, CON);
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
	else
		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
}

660 661 662 663 664 665
#ifdef CONFIG_PM

/*
 * Restore the MMC host context, if it was lost as result of a
 * power state change.
 */
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static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
667 668
{
	struct mmc_ios *ios = &host->mmc->ios;
669
	u32 hctl, capa;
670 671
	unsigned long timeout;

672 673 674 675 676 677 678 679
	if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
	    host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
	    host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
	    host->capa == OMAP_HSMMC_READ(host->base, CAPA))
		return 0;

	host->context_loss++;

680
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
681 682 683 684 685 686 687 688 689 690 691
		if (host->power_mode != MMC_POWER_OFF &&
		    (1 << ios->vdd) <= MMC_VDD_23_24)
			hctl = SDVS18;
		else
			hctl = SDVS30;
		capa = VS30 | VS18;
	} else {
		hctl = SDVS18;
		capa = VS18;
	}

692 693 694
	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
		hctl |= IWE;

695 696 697 698 699 700 701 702 703 704 705 706 707 708
	OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | hctl);

	OMAP_HSMMC_WRITE(host->base, CAPA,
			OMAP_HSMMC_READ(host->base, CAPA) | capa);

	OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);

	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
		&& time_before(jiffies, timeout))
		;

709 710 711
	OMAP_HSMMC_WRITE(host->base, ISE, 0);
	OMAP_HSMMC_WRITE(host->base, IE, 0);
	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
712 713 714 715 716

	/* Do not initialize card-specific things if the power is off */
	if (host->power_mode == MMC_POWER_OFF)
		goto out;

717
	omap_hsmmc_set_bus_width(host);
718

719
	omap_hsmmc_set_clock(host);
720

721 722
	omap_hsmmc_set_bus_mode(host);

723
out:
724 725
	dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
		host->context_loss);
726 727 728 729 730 731
	return 0;
}

/*
 * Save the MMC host context (store the number of power state changes so far).
 */
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static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
733
{
734 735 736 737
	host->con =  OMAP_HSMMC_READ(host->base, CON);
	host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
	host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
	host->capa = OMAP_HSMMC_READ(host->base, CAPA);
738 739 740 741
}

#else

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742
static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
743 744 745 746
{
	return 0;
}

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747
static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
748 749 750 751 752
{
}

#endif

753 754 755 756
/*
 * Send init stream sequence to card
 * before sending IDLE command
 */
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static void send_init_stream(struct omap_hsmmc_host *host)
758 759 760 761
{
	int reg = 0;
	unsigned long timeout;

762 763 764
	if (host->protect_card)
		return;

765
	disable_irq(host->irq);
766 767

	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
768 769 770 771 772
	OMAP_HSMMC_WRITE(host->base, CON,
		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);

	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
773 774
	while ((reg != CC_EN) && time_before(jiffies, timeout))
		reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
775 776 777

	OMAP_HSMMC_WRITE(host->base, CON,
		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
778 779 780 781

	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	OMAP_HSMMC_READ(host->base, STAT);

782 783 784 785
	enable_irq(host->irq);
}

static inline
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786
int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
787 788 789
{
	int r = 1;

790
	if (host->get_cover_state)
791
		r = host->get_cover_state(host->dev);
792 793 794 795
	return r;
}

static ssize_t
D
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796
omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
797 798 799
			   char *buf)
{
	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
D
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800
	struct omap_hsmmc_host *host = mmc_priv(mmc);
801

D
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802 803
	return sprintf(buf, "%s\n",
			omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
804 805
}

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806
static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
807 808

static ssize_t
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809
omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
810 811 812
			char *buf)
{
	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
D
Denis Karpov 已提交
813
	struct omap_hsmmc_host *host = mmc_priv(mmc);
814

815
	return sprintf(buf, "%s\n", mmc_pdata(host)->name);
816 817
}

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818
static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
819 820 821 822 823

/*
 * Configure the response type and send the cmd.
 */
static void
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824
omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
825 826 827 828
	struct mmc_data *data)
{
	int cmdreg = 0, resptype = 0, cmdtype = 0;

829
	dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
830 831 832
		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
	host->cmd = cmd;

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833
	omap_hsmmc_enable_irq(host, cmd);
834

835
	host->response_busy = 0;
836 837 838
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			resptype = 1;
839 840 841 842
		else if (cmd->flags & MMC_RSP_BUSY) {
			resptype = 3;
			host->response_busy = 1;
		} else
843 844 845 846 847 848 849 850 851 852 853 854 855
			resptype = 2;
	}

	/*
	 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
	 * a val of 0x3, rest 0x0.
	 */
	if (cmd == host->mrq->stop)
		cmdtype = 0x3;

	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);

856 857 858 859 860
	if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
	    host->mrq->sbc) {
		cmdreg |= ACEN_ACMD23;
		OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
	}
861 862 863 864 865 866 867 868 869
	if (data) {
		cmdreg |= DP_SELECT | MSBS | BCE;
		if (data->flags & MMC_DATA_READ)
			cmdreg |= DDIR;
		else
			cmdreg &= ~(DDIR);
	}

	if (host->use_dma)
870
		cmdreg |= DMAE;
871

872
	host->req_in_progress = 1;
873

874 875 876 877
	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
}

878
static int
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879
omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
880 881 882 883 884 885 886
{
	if (data->flags & MMC_DATA_WRITE)
		return DMA_TO_DEVICE;
	else
		return DMA_FROM_DEVICE;
}

887 888 889 890 891 892
static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
	struct mmc_data *data)
{
	return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
}

893 894 895
static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
{
	int dma_ch;
896
	unsigned long flags;
897

898
	spin_lock_irqsave(&host->irq_lock, flags);
899 900
	host->req_in_progress = 0;
	dma_ch = host->dma_ch;
901
	spin_unlock_irqrestore(&host->irq_lock, flags);
902 903 904 905 906 907 908 909 910

	omap_hsmmc_disable_irq(host);
	/* Do not complete the request if DMA is still in progress */
	if (mrq->data && host->use_dma && dma_ch != -1)
		return;
	host->mrq = NULL;
	mmc_request_done(host->mmc, mrq);
}

911 912 913 914
/*
 * Notify the transfer complete to MMC core
 */
static void
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915
omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
916
{
917 918 919
	if (!data) {
		struct mmc_request *mrq = host->mrq;

920 921 922 923 924 925 926
		/* TC before CC from CMD6 - don't know why, but it happens */
		if (host->cmd && host->cmd->opcode == 6 &&
		    host->response_busy) {
			host->response_busy = 0;
			return;
		}

927
		omap_hsmmc_request_done(host, mrq);
928 929 930
		return;
	}

931 932 933 934 935 936 937
	host->data = NULL;

	if (!data->error)
		data->bytes_xfered += data->blocks * (data->blksz);
	else
		data->bytes_xfered = 0;

B
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938 939 940
	if (data->stop && (data->error || !host->mrq->sbc))
		omap_hsmmc_start_command(host, data->stop, NULL);
	else
941
		omap_hsmmc_request_done(host, data->mrq);
942 943 944 945 946 947
}

/*
 * Notify the core about command completion
 */
static void
D
Denis Karpov 已提交
948
omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
949
{
B
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950
	if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
951
	    !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
952
		host->cmd = NULL;
B
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953 954 955 956 957 958
		omap_hsmmc_start_dma_transfer(host);
		omap_hsmmc_start_command(host, host->mrq->cmd,
						host->mrq->data);
		return;
	}

959 960
	host->cmd = NULL;

961 962 963 964 965 966 967 968 969 970 971 972
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136) {
			/* response type 2 */
			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
		} else {
			/* response types 1, 1b, 3, 4, 5, 6 */
			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
		}
	}
973
	if ((host->data == NULL && !host->response_busy) || cmd->error)
974
		omap_hsmmc_request_done(host, host->mrq);
975 976 977 978 979
}

/*
 * DMA clean up for command errors
 */
D
Denis Karpov 已提交
980
static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
981
{
982
	int dma_ch;
983
	unsigned long flags;
984

985
	host->data->error = errno;
986

987
	spin_lock_irqsave(&host->irq_lock, flags);
988 989
	dma_ch = host->dma_ch;
	host->dma_ch = -1;
990
	spin_unlock_irqrestore(&host->irq_lock, flags);
991 992

	if (host->use_dma && dma_ch != -1) {
993 994 995 996 997
		struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);

		dmaengine_terminate_all(chan);
		dma_unmap_sg(chan->device->dev,
			host->data->sg, host->data->sg_len,
D
Denis Karpov 已提交
998
			omap_hsmmc_get_dma_dir(host, host->data));
999

1000
		host->data->host_cookie = 0;
1001 1002 1003 1004 1005 1006 1007 1008
	}
	host->data = NULL;
}

/*
 * Readable error output
 */
#ifdef CONFIG_MMC_DEBUG
1009
static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1010 1011
{
	/* --- means reserved bit without definition at documentation */
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1012
	static const char *omap_hsmmc_status_bits[] = {
1013 1014 1015 1016
		"CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
		"CIRQ",	"OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
		"CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
		"ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1017 1018 1019 1020 1021 1022 1023 1024
	};
	char res[256];
	char *buf = res;
	int len, i;

	len = sprintf(buf, "MMC IRQ 0x%x :", status);
	buf += len;

D
Denis Karpov 已提交
1025
	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1026
		if (status & (1 << i)) {
D
Denis Karpov 已提交
1027
			len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1028 1029 1030
			buf += len;
		}

1031
	dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1032
}
1033 1034 1035 1036 1037
#else
static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
					     u32 status)
{
}
1038 1039
#endif  /* CONFIG_MMC_DEBUG */

1040 1041 1042 1043 1044 1045 1046
/*
 * MMC controller internal state machines reset
 *
 * Used to reset command or data internal state machines, using respectively
 *  SRC or SRD bit of SYSCTL register
 * Can be called from interrupt context
 */
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1047 1048
static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
						   unsigned long bit)
1049 1050
{
	unsigned long i = 0;
1051
	unsigned long limit = MMC_TIMEOUT_US;
1052 1053 1054 1055

	OMAP_HSMMC_WRITE(host->base, SYSCTL,
			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);

1056 1057 1058 1059
	/*
	 * OMAP4 ES2 and greater has an updated reset logic.
	 * Monitor a 0->1 transition first
	 */
1060
	if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1061
		while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1062
					&& (i++ < limit))
1063
			udelay(1);
1064 1065 1066
	}
	i = 0;

1067 1068
	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
		(i++ < limit))
1069
		udelay(1);
1070 1071 1072 1073 1074 1075

	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
		dev_err(mmc_dev(host->mmc),
			"Timeout waiting on controller reset in %s\n",
			__func__);
}
1076

1077 1078
static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
					int err, int end_cmd)
1079
{
1080
	if (end_cmd) {
1081
		omap_hsmmc_reset_controller_fsm(host, SRC);
1082 1083 1084
		if (host->cmd)
			host->cmd->error = err;
	}
1085 1086 1087 1088

	if (host->data) {
		omap_hsmmc_reset_controller_fsm(host, SRD);
		omap_hsmmc_dma_cleanup(host, err);
1089 1090
	} else if (host->mrq && host->mrq->cmd)
		host->mrq->cmd->error = err;
1091 1092
}

1093
static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1094 1095
{
	struct mmc_data *data;
1096
	int end_cmd = 0, end_trans = 0;
1097
	int error = 0;
1098

1099
	data = host->data;
1100
	dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1101

1102
	if (status & ERR_EN) {
1103
		omap_hsmmc_dbg_report_irq(host, status);
1104

1105
		if (status & (CTO_EN | CCRC_EN))
1106
			end_cmd = 1;
1107
		if (status & (CTO_EN | DTO_EN))
1108
			hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1109
		else if (status & (CCRC_EN | DCRC_EN))
1110
			hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1111

1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
		if (status & ACE_EN) {
			u32 ac12;
			ac12 = OMAP_HSMMC_READ(host->base, AC12);
			if (!(ac12 & ACNE) && host->mrq->sbc) {
				end_cmd = 1;
				if (ac12 & ACTO)
					error =  -ETIMEDOUT;
				else if (ac12 & (ACCE | ACEB | ACIE))
					error = -EILSEQ;
				host->mrq->sbc->error = error;
				hsmmc_command_incomplete(host, error, end_cmd);
			}
			dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
		}
1126
		if (host->data || host->response_busy) {
1127
			end_trans = !end_cmd;
1128
			host->response_busy = 0;
1129 1130 1131
		}
	}

1132
	OMAP_HSMMC_WRITE(host->base, STAT, status);
1133
	if (end_cmd || ((status & CC_EN) && host->cmd))
D
Denis Karpov 已提交
1134
		omap_hsmmc_cmd_done(host, host->cmd);
1135
	if ((end_trans || (status & TC_EN)) && host->mrq)
D
Denis Karpov 已提交
1136
		omap_hsmmc_xfer_done(host, data);
1137
}
1138

1139 1140 1141 1142 1143 1144 1145 1146 1147
/*
 * MMC controller IRQ handler
 */
static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
{
	struct omap_hsmmc_host *host = dev_id;
	int status;

	status = OMAP_HSMMC_READ(host->base, STAT);
1148 1149 1150 1151 1152 1153
	while (status & (INT_EN_MASK | CIRQ_EN)) {
		if (host->req_in_progress)
			omap_hsmmc_do_irq(host, status);

		if (status & CIRQ_EN)
			mmc_signal_sdio_irq(host->mmc);
1154

1155 1156
		/* Flush posted write */
		status = OMAP_HSMMC_READ(host->base, STAT);
1157
	}
1158

1159 1160 1161
	return IRQ_HANDLED;
}

1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177
static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
{
	struct omap_hsmmc_host *host = dev_id;

	/* cirq is level triggered, disable to avoid infinite loop */
	spin_lock(&host->irq_lock);
	if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
		disable_irq_nosync(host->wake_irq);
		host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
	}
	spin_unlock(&host->irq_lock);
	pm_request_resume(host->dev); /* no use counter */

	return IRQ_HANDLED;
}

D
Denis Karpov 已提交
1178
static void set_sd_bus_power(struct omap_hsmmc_host *host)
A
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1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
{
	unsigned long i;

	OMAP_HSMMC_WRITE(host->base, HCTL,
			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
	for (i = 0; i < loops_per_jiffy; i++) {
		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
			break;
		cpu_relax();
	}
}

1191
/*
1192 1193 1194 1195 1196
 * Switch MMC interface voltage ... only relevant for MMC1.
 *
 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 * Some chips, like eMMC ones, use internal transceivers.
1197
 */
D
Denis Karpov 已提交
1198
static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1199 1200 1201 1202 1203
{
	u32 reg_val = 0;
	int ret;

	/* Disable the clocks */
1204
	pm_runtime_put_sync(host->dev);
1205
	if (host->dbclk)
1206
		clk_disable_unprepare(host->dbclk);
1207 1208

	/* Turn the power off */
1209
	ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1210 1211

	/* Turn the power ON with given VDD 1.8 or 3.0v */
1212
	if (!ret)
1213
		ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1214
	pm_runtime_get_sync(host->dev);
1215
	if (host->dbclk)
1216
		clk_prepare_enable(host->dbclk);
1217

1218 1219 1220 1221 1222 1223
	if (ret != 0)
		goto err;

	OMAP_HSMMC_WRITE(host->base, HCTL,
		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1224

1225 1226 1227
	/*
	 * If a MMC dual voltage card is detected, the set_ios fn calls
	 * this fn with VDD bit set for 1.8V. Upon card removal from the
D
Denis Karpov 已提交
1228
	 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1229
	 *
1230 1231 1232 1233 1234 1235 1236 1237 1238
	 * Cope with a bit of slop in the range ... per data sheets:
	 *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
	 *    but recommended values are 1.71V to 1.89V
	 *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
	 *    but recommended values are 2.7V to 3.3V
	 *
	 * Board setup code shouldn't permit anything very out-of-range.
	 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
	 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1239
	 */
1240
	if ((1 << vdd) <= MMC_VDD_23_24)
1241
		reg_val |= SDVS18;
1242 1243
	else
		reg_val |= SDVS30;
1244 1245

	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
A
Adrian Hunter 已提交
1246
	set_sd_bus_power(host);
1247 1248 1249

	return 0;
err:
1250
	dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1251 1252 1253
	return ret;
}

1254 1255 1256
/* Protect the card while the cover is open */
static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
{
1257
	if (!host->get_cover_state)
1258 1259 1260
		return;

	host->reqs_blocked = 0;
1261
	if (host->get_cover_state(host->dev)) {
1262
		if (host->protect_card) {
1263
			dev_info(host->dev, "%s: cover is closed, "
1264 1265 1266 1267 1268 1269
					 "card is now accessible\n",
					 mmc_hostname(host->mmc));
			host->protect_card = 0;
		}
	} else {
		if (!host->protect_card) {
1270
			dev_info(host->dev, "%s: cover is open, "
1271 1272 1273 1274 1275 1276 1277
					 "card is now inaccessible\n",
					 mmc_hostname(host->mmc));
			host->protect_card = 1;
		}
	}
}

1278
/*
1279
 * irq handler to notify the core about card insertion/removal
1280
 */
1281
static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1282
{
1283
	struct omap_hsmmc_host *host = dev_id;
1284 1285 1286
	int carddetect;

	sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1287

1288
	if (host->card_detect)
1289
		carddetect = host->card_detect(host->dev);
1290 1291
	else {
		omap_hsmmc_protect_card(host);
1292
		carddetect = -ENOSYS;
1293
	}
1294

1295
	if (carddetect)
1296
		mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1297
	else
1298 1299 1300 1301
		mmc_detect_change(host->mmc, (HZ * 50) / 1000);
	return IRQ_HANDLED;
}

1302
static void omap_hsmmc_dma_callback(void *param)
1303
{
1304 1305
	struct omap_hsmmc_host *host = param;
	struct dma_chan *chan;
1306
	struct mmc_data *data;
1307
	int req_in_progress;
1308

1309
	spin_lock_irq(&host->irq_lock);
1310
	if (host->dma_ch < 0) {
1311
		spin_unlock_irq(&host->irq_lock);
1312
		return;
1313
	}
1314

1315
	data = host->mrq->data;
1316
	chan = omap_hsmmc_get_dma_chan(host, data);
1317
	if (!data->host_cookie)
1318 1319
		dma_unmap_sg(chan->device->dev,
			     data->sg, data->sg_len,
1320
			     omap_hsmmc_get_dma_dir(host, data));
1321 1322

	req_in_progress = host->req_in_progress;
1323
	host->dma_ch = -1;
1324
	spin_unlock_irq(&host->irq_lock);
1325 1326 1327 1328 1329 1330 1331 1332

	/* If DMA has finished after TC, complete the request */
	if (!req_in_progress) {
		struct mmc_request *mrq = host->mrq;

		host->mrq = NULL;
		mmc_request_done(host->mmc, mrq);
	}
1333 1334
}

1335 1336
static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
				       struct mmc_data *data,
1337
				       struct omap_hsmmc_next *next,
1338
				       struct dma_chan *chan)
1339 1340 1341 1342 1343
{
	int dma_len;

	if (!next && data->host_cookie &&
	    data->host_cookie != host->next_data.cookie) {
1344
		dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1345 1346 1347 1348 1349 1350
		       " host->next_data.cookie %d\n",
		       __func__, data->host_cookie, host->next_data.cookie);
		data->host_cookie = 0;
	}

	/* Check if next job is already prepared */
1351
	if (next || data->host_cookie != host->next_data.cookie) {
1352
		dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
				     omap_hsmmc_get_dma_dir(host, data));

	} else {
		dma_len = host->next_data.dma_len;
		host->next_data.dma_len = 0;
	}


	if (dma_len == 0)
		return -EINVAL;

	if (next) {
		next->dma_len = dma_len;
		data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
	} else
		host->dma_len = dma_len;

	return 0;
}

1373 1374 1375
/*
 * Routine to configure and start DMA for the MMC card
 */
B
Balaji T K 已提交
1376
static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
D
Denis Karpov 已提交
1377
					struct mmc_request *req)
1378
{
1379 1380 1381
	struct dma_slave_config cfg;
	struct dma_async_tx_descriptor *tx;
	int ret = 0, i;
1382
	struct mmc_data *data = req->data;
1383
	struct dma_chan *chan;
1384

1385
	/* Sanity check: all the SG entries must be aligned by block size. */
1386
	for (i = 0; i < data->sg_len; i++) {
1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398
		struct scatterlist *sgl;

		sgl = data->sg + i;
		if (sgl->length % data->blksz)
			return -EINVAL;
	}
	if ((data->blksz % 4) != 0)
		/* REVISIT: The MMC buffer increments only when MSB is written.
		 * Return error for blksz which is non multiple of four.
		 */
		return -EINVAL;

1399
	BUG_ON(host->dma_ch != -1);
1400

1401 1402
	chan = omap_hsmmc_get_dma_chan(host, data);

1403 1404 1405 1406 1407 1408
	cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
	cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	cfg.src_maxburst = data->blksz / 4;
	cfg.dst_maxburst = data->blksz / 4;
1409

1410 1411
	ret = dmaengine_slave_config(chan, &cfg);
	if (ret)
1412
		return ret;
1413

1414
	ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1415 1416
	if (ret)
		return ret;
1417

1418 1419 1420 1421 1422 1423 1424 1425
	tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
		data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
		DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!tx) {
		dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
		/* FIXME: cleanup */
		return -1;
	}
1426

1427 1428
	tx->callback = omap_hsmmc_dma_callback;
	tx->callback_param = host;
1429

1430 1431
	/* Does not fail */
	dmaengine_submit(tx);
1432

1433
	host->dma_ch = 1;
1434

1435 1436 1437
	return 0;
}

D
Denis Karpov 已提交
1438
static void set_data_timeout(struct omap_hsmmc_host *host,
1439 1440
			     unsigned int timeout_ns,
			     unsigned int timeout_clks)
1441 1442 1443 1444 1445 1446 1447 1448 1449
{
	unsigned int timeout, cycle_ns;
	uint32_t reg, clkd, dto = 0;

	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
	if (clkd == 0)
		clkd = 1;

1450
	cycle_ns = 1000000000 / (host->clk_rate / clkd);
1451 1452
	timeout = timeout_ns / cycle_ns;
	timeout += timeout_clks;
1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
	if (timeout) {
		while ((timeout & 0x80000000) == 0) {
			dto += 1;
			timeout <<= 1;
		}
		dto = 31 - dto;
		timeout <<= 1;
		if (timeout && dto)
			dto += 1;
		if (dto >= 13)
			dto -= 13;
		else
			dto = 0;
		if (dto > 14)
			dto = 14;
	}

	reg &= ~DTO_MASK;
	reg |= dto << DTO_SHIFT;
	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
}

B
Balaji T K 已提交
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
{
	struct mmc_request *req = host->mrq;
	struct dma_chan *chan;

	if (!req->data)
		return;
	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
				| (req->data->blocks << 16));
	set_data_timeout(host, req->data->timeout_ns,
				req->data->timeout_clks);
	chan = omap_hsmmc_get_dma_chan(host, req->data);
	dma_async_issue_pending(chan);
}

1490 1491 1492 1493
/*
 * Configure block length for MMC/SD cards and initiate the transfer.
 */
static int
D
Denis Karpov 已提交
1494
omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1495 1496 1497 1498 1499 1500
{
	int ret;
	host->data = req->data;

	if (req->data == NULL) {
		OMAP_HSMMC_WRITE(host->base, BLK, 0);
1501 1502 1503 1504 1505 1506
		/*
		 * Set an arbitrary 100ms data timeout for commands with
		 * busy signal.
		 */
		if (req->cmd->flags & MMC_RSP_BUSY)
			set_data_timeout(host, 100000000U, 0);
1507 1508 1509 1510
		return 0;
	}

	if (host->use_dma) {
B
Balaji T K 已提交
1511
		ret = omap_hsmmc_setup_dma_transfer(host, req);
1512
		if (ret != 0) {
1513
			dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1514 1515 1516 1517 1518 1519
			return ret;
		}
	}
	return 0;
}

1520 1521 1522 1523 1524 1525
static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
				int err)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;

1526
	if (host->use_dma && data->host_cookie) {
1527 1528
		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);

1529 1530
		dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
			     omap_hsmmc_get_dma_dir(host, data));
1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
		data->host_cookie = 0;
	}
}

static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
			       bool is_first_req)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);

	if (mrq->data->host_cookie) {
		mrq->data->host_cookie = 0;
		return ;
	}

1545 1546 1547
	if (host->use_dma) {
		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);

1548
		if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1549
						&host->next_data, c))
1550
			mrq->data->host_cookie = 0;
1551
	}
1552 1553
}

1554 1555 1556
/*
 * Request function. for read/write operation
 */
D
Denis Karpov 已提交
1557
static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1558
{
D
Denis Karpov 已提交
1559
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1560
	int err;
1561

1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582
	BUG_ON(host->req_in_progress);
	BUG_ON(host->dma_ch != -1);
	if (host->protect_card) {
		if (host->reqs_blocked < 3) {
			/*
			 * Ensure the controller is left in a consistent
			 * state by resetting the command and data state
			 * machines.
			 */
			omap_hsmmc_reset_controller_fsm(host, SRD);
			omap_hsmmc_reset_controller_fsm(host, SRC);
			host->reqs_blocked += 1;
		}
		req->cmd->error = -EBADF;
		if (req->data)
			req->data->error = -EBADF;
		req->cmd->retries = 0;
		mmc_request_done(mmc, req);
		return;
	} else if (host->reqs_blocked)
		host->reqs_blocked = 0;
1583 1584
	WARN_ON(host->mrq != NULL);
	host->mrq = req;
1585
	host->clk_rate = clk_get_rate(host->fclk);
D
Denis Karpov 已提交
1586
	err = omap_hsmmc_prepare_data(host, req);
1587 1588 1589 1590 1591 1592 1593 1594
	if (err) {
		req->cmd->error = err;
		if (req->data)
			req->data->error = err;
		host->mrq = NULL;
		mmc_request_done(mmc, req);
		return;
	}
1595
	if (req->sbc && !(host->flags & AUTO_CMD23)) {
B
Balaji T K 已提交
1596 1597 1598
		omap_hsmmc_start_command(host, req->sbc, NULL);
		return;
	}
1599

B
Balaji T K 已提交
1600
	omap_hsmmc_start_dma_transfer(host);
D
Denis Karpov 已提交
1601
	omap_hsmmc_start_command(host, req->cmd, req->data);
1602 1603 1604
}

/* Routine to configure clock values. Exposed API to core */
D
Denis Karpov 已提交
1605
static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1606
{
D
Denis Karpov 已提交
1607
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1608
	int do_send_init_stream = 0;
1609

1610
	pm_runtime_get_sync(host->dev);
1611

1612 1613 1614
	if (ios->power_mode != host->power_mode) {
		switch (ios->power_mode) {
		case MMC_POWER_OFF:
1615
			mmc_pdata(host)->set_power(host->dev, 0, 0);
1616 1617
			break;
		case MMC_POWER_UP:
1618
			mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1619 1620 1621 1622 1623 1624
			break;
		case MMC_POWER_ON:
			do_send_init_stream = 1;
			break;
		}
		host->power_mode = ios->power_mode;
1625 1626
	}

1627 1628
	/* FIXME: set registers based only on changes to ios */

1629
	omap_hsmmc_set_bus_width(host);
1630

1631
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1632 1633 1634
		/* Only MMC1 can interface at 3V without some flavor
		 * of external transceiver; but they all handle 1.8V.
		 */
1635
		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1636
			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
1637 1638 1639 1640 1641 1642
				/*
				 * The mmc_select_voltage fn of the core does
				 * not seem to set the power_mode to
				 * MMC_POWER_UP upon recalculating the voltage.
				 * vdd 1.8v.
				 */
D
Denis Karpov 已提交
1643 1644
			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
				dev_dbg(mmc_dev(host->mmc),
1645 1646 1647 1648
						"Switch operation failed\n");
		}
	}

1649
	omap_hsmmc_set_clock(host);
1650

1651
	if (do_send_init_stream)
1652 1653
		send_init_stream(host);

1654
	omap_hsmmc_set_bus_mode(host);
1655

1656
	pm_runtime_put_autosuspend(host->dev);
1657 1658 1659 1660
}

static int omap_hsmmc_get_cd(struct mmc_host *mmc)
{
D
Denis Karpov 已提交
1661
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1662

1663
	if (!host->card_detect)
1664
		return -ENOSYS;
1665
	return host->card_detect(host->dev);
1666 1667 1668 1669
}

static int omap_hsmmc_get_ro(struct mmc_host *mmc)
{
D
Denis Karpov 已提交
1670
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1671

1672
	if (!host->get_ro)
1673
		return -ENOSYS;
1674
	return host->get_ro(host->dev);
1675 1676
}

1677 1678 1679 1680
static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);

1681 1682
	if (mmc_pdata(host)->init_card)
		mmc_pdata(host)->init_card(card);
1683 1684
}

1685 1686 1687
static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1688
	u32 irq_mask, con;
1689 1690 1691 1692
	unsigned long flags;

	spin_lock_irqsave(&host->irq_lock, flags);

1693
	con = OMAP_HSMMC_READ(host->base, CON);
1694 1695 1696 1697
	irq_mask = OMAP_HSMMC_READ(host->base, ISE);
	if (enable) {
		host->flags |= HSMMC_SDIO_IRQ_ENABLED;
		irq_mask |= CIRQ_EN;
1698
		con |= CTPL | CLKEXTFREE;
1699 1700 1701
	} else {
		host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
		irq_mask &= ~CIRQ_EN;
1702
		con &= ~(CTPL | CLKEXTFREE);
1703
	}
1704
	OMAP_HSMMC_WRITE(host->base, CON, con);
1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748
	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);

	/*
	 * if enable, piggy back detection on current request
	 * but always disable immediately
	 */
	if (!host->req_in_progress || !enable)
		OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);

	/* flush posted write */
	OMAP_HSMMC_READ(host->base, IE);

	spin_unlock_irqrestore(&host->irq_lock, flags);
}

static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
{
	struct mmc_host *mmc = host->mmc;
	int ret;

	/*
	 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
	 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
	 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
	 * with functional clock disabled.
	 */
	if (!host->dev->of_node || !host->wake_irq)
		return -ENODEV;

	/* Prevent auto-enabling of IRQ */
	irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
	ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
			       IRQF_TRIGGER_LOW | IRQF_ONESHOT,
			       mmc_hostname(mmc), host);
	if (ret) {
		dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
		goto err;
	}

	/*
	 * Some omaps don't have wake-up path from deeper idle states
	 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
	 */
	if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767
		struct pinctrl *p = devm_pinctrl_get(host->dev);
		if (!p) {
			ret = -ENODEV;
			goto err_free_irq;
		}
		if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
			dev_info(host->dev, "missing default pinctrl state\n");
			devm_pinctrl_put(p);
			ret = -EINVAL;
			goto err_free_irq;
		}

		if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
			dev_info(host->dev, "missing idle pinctrl state\n");
			devm_pinctrl_put(p);
			ret = -EINVAL;
			goto err_free_irq;
		}
		devm_pinctrl_put(p);
1768 1769
	}

1770 1771
	OMAP_HSMMC_WRITE(host->base, HCTL,
			 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1772 1773
	return 0;

1774 1775
err_free_irq:
	devm_free_irq(host->dev, host->wake_irq, host);
1776 1777 1778 1779 1780 1781
err:
	dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
	host->wake_irq = 0;
	return ret;
}

D
Denis Karpov 已提交
1782
static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1783 1784 1785 1786
{
	u32 hctl, capa, value;

	/* Only MMC1 supports 3.0V */
1787
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
		hctl = SDVS30;
		capa = VS30 | VS18;
	} else {
		hctl = SDVS18;
		capa = VS18;
	}

	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);

	value = OMAP_HSMMC_READ(host->base, CAPA);
	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);

	/* Set SD bus power bit */
A
Adrian Hunter 已提交
1802
	set_sd_bus_power(host);
1803 1804
}

D
Denis Karpov 已提交
1805
static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1806
{
D
Denis Karpov 已提交
1807
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1808

1809 1810
	pm_runtime_get_sync(host->dev);

1811 1812 1813
	return 0;
}

1814
static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1815
{
D
Denis Karpov 已提交
1816
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1817

1818 1819 1820
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);

1821 1822 1823
	return 0;
}

1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834
static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
				     unsigned int direction, int blk_size)
{
	/* This controller can't do multiblock reads due to hw bugs */
	if (direction == MMC_DATA_READ)
		return 1;

	return blk_size;
}

static struct mmc_host_ops omap_hsmmc_ops = {
D
Denis Karpov 已提交
1835 1836
	.enable = omap_hsmmc_enable_fclk,
	.disable = omap_hsmmc_disable_fclk,
1837 1838
	.post_req = omap_hsmmc_post_req,
	.pre_req = omap_hsmmc_pre_req,
D
Denis Karpov 已提交
1839 1840
	.request = omap_hsmmc_request,
	.set_ios = omap_hsmmc_set_ios,
1841 1842
	.get_cd = omap_hsmmc_get_cd,
	.get_ro = omap_hsmmc_get_ro,
1843
	.init_card = omap_hsmmc_init_card,
1844
	.enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1845 1846
};

1847 1848
#ifdef CONFIG_DEBUG_FS

D
Denis Karpov 已提交
1849
static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1850 1851
{
	struct mmc_host *mmc = s->private;
D
Denis Karpov 已提交
1852
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1853

1854 1855 1856
	seq_printf(s, "mmc%d:\n", mmc->index);
	seq_printf(s, "sdio irq mode\t%s\n",
		   (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1857

1858 1859 1860 1861 1862 1863
	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
		seq_printf(s, "sdio irq \t%s\n",
			   (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
			   : "disabled");
	}
	seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1864

1865 1866
	pm_runtime_get_sync(host->dev);
	seq_puts(s, "\nregs:\n");
1867 1868
	seq_printf(s, "CON:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, CON));
1869 1870
	seq_printf(s, "PSTATE:\t\t0x%08x\n",
		   OMAP_HSMMC_READ(host->base, PSTATE));
1871 1872 1873 1874 1875 1876 1877 1878 1879 1880
	seq_printf(s, "HCTL:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, HCTL));
	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, SYSCTL));
	seq_printf(s, "IE:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, IE));
	seq_printf(s, "ISE:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, ISE));
	seq_printf(s, "CAPA:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, CAPA));
1881

1882 1883
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
1884

1885 1886 1887
	return 0;
}

D
Denis Karpov 已提交
1888
static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1889
{
D
Denis Karpov 已提交
1890
	return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1891 1892 1893
}

static const struct file_operations mmc_regs_fops = {
D
Denis Karpov 已提交
1894
	.open           = omap_hsmmc_regs_open,
1895 1896 1897 1898 1899
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

D
Denis Karpov 已提交
1900
static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1901 1902 1903 1904 1905 1906 1907 1908
{
	if (mmc->debugfs_root)
		debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
			mmc, &mmc_regs_fops);
}

#else

D
Denis Karpov 已提交
1909
static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1910 1911 1912 1913 1914
{
}

#endif

1915
#ifdef CONFIG_OF
1916 1917 1918 1919 1920 1921 1922 1923
static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
	/* See 35xx errata 2.1.1.128 in SPRZ278F */
	.controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
};

static const struct omap_mmc_of_data omap4_mmc_of_data = {
	.reg_offset = 0x100,
};
1924 1925 1926 1927
static const struct omap_mmc_of_data am33xx_mmc_of_data = {
	.reg_offset = 0x100,
	.controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
};
1928 1929 1930 1931 1932

static const struct of_device_id omap_mmc_of_match[] = {
	{
		.compatible = "ti,omap2-hsmmc",
	},
1933 1934 1935 1936
	{
		.compatible = "ti,omap3-pre-es3-hsmmc",
		.data = &omap3_pre_es3_mmc_of_data,
	},
1937 1938 1939 1940 1941
	{
		.compatible = "ti,omap3-hsmmc",
	},
	{
		.compatible = "ti,omap4-hsmmc",
1942
		.data = &omap4_mmc_of_data,
1943
	},
1944 1945 1946 1947
	{
		.compatible = "ti,am33xx-hsmmc",
		.data = &am33xx_mmc_of_data,
	},
1948
	{},
1949
};
1950 1951
MODULE_DEVICE_TABLE(of, omap_mmc_of_match);

1952
static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1953
{
1954
	struct omap_hsmmc_platform_data *pdata;
1955
	struct device_node *np = dev->of_node;
1956
	u32 bus_width, max_freq;
1957 1958 1959 1960 1961 1962
	int cd_gpio, wp_gpio;

	cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
	wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
	if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
		return ERR_PTR(-EPROBE_DEFER);
1963 1964 1965

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
1966
		return ERR_PTR(-ENOMEM); /* out of memory */
1967 1968 1969 1970

	if (of_find_property(np, "ti,dual-volt", NULL))
		pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;

1971 1972
	pdata->switch_pin = cd_gpio;
	pdata->gpio_wp = wp_gpio;
1973 1974

	if (of_find_property(np, "ti,non-removable", NULL)) {
1975 1976
		pdata->nonremovable = true;
		pdata->no_regulator_off_init = true;
1977
	}
A
Arnd Bergmann 已提交
1978
	of_property_read_u32(np, "bus-width", &bus_width);
1979
	if (bus_width == 4)
1980
		pdata->caps |= MMC_CAP_4_BIT_DATA;
1981
	else if (bus_width == 8)
1982
		pdata->caps |= MMC_CAP_8_BIT_DATA;
1983 1984

	if (of_find_property(np, "ti,needs-special-reset", NULL))
1985
		pdata->features |= HSMMC_HAS_UPDATED_RESET;
1986

1987 1988 1989
	if (!of_property_read_u32(np, "max-frequency", &max_freq))
		pdata->max_freq = max_freq;

1990
	if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1991
		pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1992

1993
	if (of_find_property(np, "keep-power-in-suspend", NULL))
1994
		pdata->pm_caps |= MMC_PM_KEEP_POWER;
1995 1996

	if (of_find_property(np, "enable-sdio-wakeup", NULL))
1997
		pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1998

1999 2000 2001
	return pdata;
}
#else
2002
static inline struct omap_hsmmc_platform_data
2003 2004
			*of_get_hsmmc_pdata(struct device *dev)
{
2005
	return ERR_PTR(-EINVAL);
2006 2007 2008
}
#endif

B
Bill Pemberton 已提交
2009
static int omap_hsmmc_probe(struct platform_device *pdev)
2010
{
2011
	struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2012
	struct mmc_host *mmc;
D
Denis Karpov 已提交
2013
	struct omap_hsmmc_host *host = NULL;
2014
	struct resource *res;
2015
	int ret, irq;
2016
	const struct of_device_id *match;
2017 2018
	dma_cap_mask_t mask;
	unsigned tx_req, rx_req;
2019
	const struct omap_mmc_of_data *data;
2020
	void __iomem *base;
2021 2022 2023 2024

	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
	if (match) {
		pdata = of_get_hsmmc_pdata(&pdev->dev);
2025 2026 2027 2028

		if (IS_ERR(pdata))
			return PTR_ERR(pdata);

2029
		if (match->data) {
2030 2031 2032
			data = match->data;
			pdata->reg_offset = data->reg_offset;
			pdata->controller_flags |= data->controller_flags;
2033 2034
		}
	}
2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045

	if (pdata == NULL) {
		dev_err(&pdev->dev, "Platform Data is missing\n");
		return -ENXIO;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (res == NULL || irq < 0)
		return -ENXIO;

2046 2047 2048
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);
2049

D
Denis Karpov 已提交
2050
	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2051 2052
	if (!mmc) {
		ret = -ENOMEM;
2053
		goto err;
2054 2055 2056 2057 2058 2059 2060 2061 2062
	}

	host		= mmc_priv(mmc);
	host->mmc	= mmc;
	host->pdata	= pdata;
	host->dev	= &pdev->dev;
	host->use_dma	= 1;
	host->dma_ch	= -1;
	host->irq	= irq;
2063
	host->mapbase	= res->start + pdata->reg_offset;
2064
	host->base	= base + pdata->reg_offset;
2065
	host->power_mode = MMC_POWER_OFF;
2066
	host->next_data.cookie = 1;
2067
	host->pbias_enabled = 0;
2068

2069 2070 2071 2072
	ret = omap_hsmmc_gpio_init(host, pdata);
	if (ret)
		goto err_gpio;

2073 2074
	platform_set_drvdata(pdev, host);

2075 2076 2077
	if (pdev->dev.of_node)
		host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);

2078
	mmc->ops	= &omap_hsmmc_ops;
2079

2080 2081 2082 2083 2084 2085
	mmc->f_min = OMAP_MMC_MIN_CLOCK;

	if (pdata->max_freq > 0)
		mmc->f_max = pdata->max_freq;
	else
		mmc->f_max = OMAP_MMC_MAX_CLOCK;
2086

2087
	spin_lock_init(&host->irq_lock);
2088

B
Balaji T K 已提交
2089
	host->fclk = devm_clk_get(&pdev->dev, "fck");
2090 2091 2092 2093 2094 2095
	if (IS_ERR(host->fclk)) {
		ret = PTR_ERR(host->fclk);
		host->fclk = NULL;
		goto err1;
	}

2096 2097
	if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2098
		omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2099
	}
2100

2101 2102 2103 2104
	pm_runtime_enable(host->dev);
	pm_runtime_get_sync(host->dev);
	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
	pm_runtime_use_autosuspend(host->dev);
2105

2106 2107
	omap_hsmmc_context_save(host);

B
Balaji T K 已提交
2108
	host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2109 2110 2111 2112 2113
	/*
	 * MMC can still work without debounce clock.
	 */
	if (IS_ERR(host->dbclk)) {
		host->dbclk = NULL;
2114
	} else if (clk_prepare_enable(host->dbclk) != 0) {
2115 2116
		dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
		host->dbclk = NULL;
2117
	}
2118

2119 2120
	/* Since we do only SG emulation, we can have as many segs
	 * as we want. */
2121
	mmc->max_segs = 1024;
2122

2123 2124 2125 2126 2127
	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
	mmc->max_seg_size = mmc->max_req_size;

2128
	mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
A
Adrian Hunter 已提交
2129
		     MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2130

2131
	mmc->caps |= mmc_pdata(host)->caps;
2132
	if (mmc->caps & MMC_CAP_8_BIT_DATA)
2133 2134
		mmc->caps |= MMC_CAP_4_BIT_DATA;

2135
	if (mmc_pdata(host)->nonremovable)
2136 2137
		mmc->caps |= MMC_CAP_NONREMOVABLE;

2138
	mmc->pm_caps = mmc_pdata(host)->pm_caps;
E
Eliad Peller 已提交
2139

D
Denis Karpov 已提交
2140
	omap_hsmmc_conf_bus_power(host);
2141

2142 2143 2144 2145 2146 2147 2148 2149
	if (!pdev->dev.of_node) {
		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
		if (!res) {
			dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
			ret = -ENXIO;
			goto err_irq;
		}
		tx_req = res->start;
2150

2151 2152 2153 2154 2155 2156 2157
		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
		if (!res) {
			dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
			ret = -ENXIO;
			goto err_irq;
		}
		rx_req = res->start;
G
Grazvydas Ignotas 已提交
2158
	}
2159

2160 2161 2162
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

2163 2164 2165 2166
	host->rx_chan =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &rx_req, &pdev->dev, "rx");

2167 2168
	if (!host->rx_chan) {
		dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2169
		ret = -ENXIO;
2170 2171 2172
		goto err_irq;
	}

2173 2174 2175 2176
	host->tx_chan =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &tx_req, &pdev->dev, "tx");

2177 2178
	if (!host->tx_chan) {
		dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2179
		ret = -ENXIO;
2180
		goto err_irq;
2181
	}
2182 2183

	/* Request IRQ for MMC operations */
2184
	ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2185 2186
			mmc_hostname(mmc), host);
	if (ret) {
2187
		dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2188 2189 2190
		goto err_irq;
	}

2191
	if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2192 2193
		ret = omap_hsmmc_reg_get(host);
		if (ret)
2194
			goto err_irq;
2195 2196 2197
		host->use_reg = 1;
	}

2198
	mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2199 2200

	/* Request IRQ for card detect */
2201
	if (host->card_detect_irq) {
2202
		ret = devm_request_threaded_irq(&pdev->dev,
2203
						host->card_detect_irq,
2204
						NULL, omap_hsmmc_detect,
2205
					   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2206
					   mmc_hostname(mmc), host);
2207
		if (ret) {
2208
			dev_err(mmc_dev(host->mmc),
2209 2210 2211 2212 2213
				"Unable to grab MMC CD IRQ\n");
			goto err_irq_cd;
		}
	}

2214
	omap_hsmmc_disable_irq(host);
2215

2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227
	/*
	 * For now, only support SDIO interrupt if we have a separate
	 * wake-up interrupt configured from device tree. This is because
	 * the wake-up interrupt is needed for idle state and some
	 * platforms need special quirks. And we don't want to add new
	 * legacy mux platform init code callbacks any longer as we
	 * are moving to DT based booting anyways.
	 */
	ret = omap_hsmmc_configure_wake_irq(host);
	if (!ret)
		mmc->caps |= MMC_CAP_SDIO_IRQ;

2228 2229
	omap_hsmmc_protect_card(host);

2230 2231
	mmc_add_host(mmc);

2232
	if (mmc_pdata(host)->name != NULL) {
2233 2234 2235 2236
		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
		if (ret < 0)
			goto err_slot_name;
	}
2237
	if (host->card_detect_irq && host->get_cover_state) {
2238 2239 2240
		ret = device_create_file(&mmc->class_dev,
					&dev_attr_cover_switch);
		if (ret < 0)
2241
			goto err_slot_name;
2242 2243
	}

D
Denis Karpov 已提交
2244
	omap_hsmmc_debugfs(mmc);
2245 2246
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
2247

2248 2249 2250 2251
	return 0;

err_slot_name:
	mmc_remove_host(mmc);
2252 2253 2254
err_irq_cd:
	if (host->use_reg)
		omap_hsmmc_reg_put(host);
2255
err_irq:
2256 2257 2258 2259
	if (host->tx_chan)
		dma_release_channel(host->tx_chan);
	if (host->rx_chan)
		dma_release_channel(host->rx_chan);
2260
	pm_runtime_put_sync(host->dev);
2261
	pm_runtime_disable(host->dev);
B
Balaji T K 已提交
2262
	if (host->dbclk)
2263
		clk_disable_unprepare(host->dbclk);
2264
err1:
2265 2266
	omap_hsmmc_gpio_free(host, pdata);
err_gpio:
2267
	mmc_free_host(mmc);
2268 2269 2270 2271
err:
	return ret;
}

B
Bill Pemberton 已提交
2272
static int omap_hsmmc_remove(struct platform_device *pdev)
2273
{
D
Denis Karpov 已提交
2274
	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2275

F
Felipe Balbi 已提交
2276 2277 2278 2279
	pm_runtime_get_sync(host->dev);
	mmc_remove_host(host->mmc);
	if (host->use_reg)
		omap_hsmmc_reg_put(host);
2280

2281 2282 2283 2284 2285
	if (host->tx_chan)
		dma_release_channel(host->tx_chan);
	if (host->rx_chan)
		dma_release_channel(host->rx_chan);

F
Felipe Balbi 已提交
2286 2287
	pm_runtime_put_sync(host->dev);
	pm_runtime_disable(host->dev);
B
Balaji T K 已提交
2288
	if (host->dbclk)
2289
		clk_disable_unprepare(host->dbclk);
2290

2291
	omap_hsmmc_gpio_free(host, host->pdata);
2292
	mmc_free_host(host->mmc);
F
Felipe Balbi 已提交
2293

2294 2295 2296 2297
	return 0;
}

#ifdef CONFIG_PM
2298
static int omap_hsmmc_suspend(struct device *dev)
2299
{
F
Felipe Balbi 已提交
2300
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2301

F
Felipe Balbi 已提交
2302
	if (!host)
2303 2304
		return 0;

F
Felipe Balbi 已提交
2305
	pm_runtime_get_sync(host->dev);
2306

F
Felipe Balbi 已提交
2307
	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2308 2309 2310
		OMAP_HSMMC_WRITE(host->base, ISE, 0);
		OMAP_HSMMC_WRITE(host->base, IE, 0);
		OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
F
Felipe Balbi 已提交
2311 2312
		OMAP_HSMMC_WRITE(host->base, HCTL,
				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2313
	}
F
Felipe Balbi 已提交
2314

2315 2316 2317 2318 2319
	/* do not wake up due to sdio irq */
	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	    !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
		disable_irq(host->wake_irq);

2320
	if (host->dbclk)
2321
		clk_disable_unprepare(host->dbclk);
2322

2323
	pm_runtime_put_sync(host->dev);
2324
	return 0;
2325 2326 2327
}

/* Routine to resume the MMC device */
2328
static int omap_hsmmc_resume(struct device *dev)
2329
{
F
Felipe Balbi 已提交
2330 2331 2332 2333
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);

	if (!host)
		return 0;
2334

F
Felipe Balbi 已提交
2335
	pm_runtime_get_sync(host->dev);
2336

2337
	if (host->dbclk)
2338
		clk_prepare_enable(host->dbclk);
2339

F
Felipe Balbi 已提交
2340 2341
	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
		omap_hsmmc_conf_bus_power(host);
2342

F
Felipe Balbi 已提交
2343
	omap_hsmmc_protect_card(host);
2344

2345 2346 2347 2348
	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	    !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
		enable_irq(host->wake_irq);

F
Felipe Balbi 已提交
2349 2350
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
2351
	return 0;
2352 2353 2354
}

#else
D
Denis Karpov 已提交
2355
#define omap_hsmmc_suspend	NULL
2356
#define omap_hsmmc_resume	NULL
2357 2358
#endif

2359 2360 2361
static int omap_hsmmc_runtime_suspend(struct device *dev)
{
	struct omap_hsmmc_host *host;
2362
	unsigned long flags;
2363
	int ret = 0;
2364 2365 2366

	host = platform_get_drvdata(to_platform_device(dev));
	omap_hsmmc_context_save(host);
F
Felipe Balbi 已提交
2367
	dev_dbg(dev, "disabled\n");
2368

2369 2370 2371 2372 2373 2374
	spin_lock_irqsave(&host->irq_lock, flags);
	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	    (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
		/* disable sdio irq handling to prevent race */
		OMAP_HSMMC_WRITE(host->base, ISE, 0);
		OMAP_HSMMC_WRITE(host->base, IE, 0);
2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389

		if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
			/*
			 * dat1 line low, pending sdio irq
			 * race condition: possible irq handler running on
			 * multi-core, abort
			 */
			dev_dbg(dev, "pending sdio irq, abort suspend\n");
			OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
			OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
			OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
			pm_runtime_mark_last_busy(dev);
			ret = -EBUSY;
			goto abort;
		}
2390

2391 2392
		pinctrl_pm_select_idle_state(dev);

2393 2394 2395
		WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
		enable_irq(host->wake_irq);
		host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2396 2397
	} else {
		pinctrl_pm_select_idle_state(dev);
2398
	}
2399

2400
abort:
2401
	spin_unlock_irqrestore(&host->irq_lock, flags);
2402
	return ret;
2403 2404 2405 2406 2407
}

static int omap_hsmmc_runtime_resume(struct device *dev)
{
	struct omap_hsmmc_host *host;
2408
	unsigned long flags;
2409 2410 2411

	host = platform_get_drvdata(to_platform_device(dev));
	omap_hsmmc_context_restore(host);
F
Felipe Balbi 已提交
2412
	dev_dbg(dev, "enabled\n");
2413

2414 2415 2416 2417 2418 2419 2420 2421 2422
	spin_lock_irqsave(&host->irq_lock, flags);
	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
	    (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
		/* sdio irq flag can't change while in runtime suspend */
		if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
			disable_irq_nosync(host->wake_irq);
			host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
		}

2423 2424 2425
		pinctrl_pm_select_default_state(host->dev);

		/* irq lost, if pinmux incorrect */
2426 2427 2428
		OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
		OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
		OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2429 2430
	} else {
		pinctrl_pm_select_default_state(host->dev);
2431 2432
	}
	spin_unlock_irqrestore(&host->irq_lock, flags);
2433 2434 2435
	return 0;
}

2436
static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
D
Denis Karpov 已提交
2437 2438
	.suspend	= omap_hsmmc_suspend,
	.resume		= omap_hsmmc_resume,
2439 2440
	.runtime_suspend = omap_hsmmc_runtime_suspend,
	.runtime_resume = omap_hsmmc_runtime_resume,
2441 2442 2443
};

static struct platform_driver omap_hsmmc_driver = {
2444
	.probe		= omap_hsmmc_probe,
B
Bill Pemberton 已提交
2445
	.remove		= omap_hsmmc_remove,
2446 2447
	.driver		= {
		.name = DRIVER_NAME,
2448
		.pm = &omap_hsmmc_dev_pm_ops,
2449
		.of_match_table = of_match_ptr(omap_mmc_of_match),
2450 2451 2452
	},
};

2453
module_platform_driver(omap_hsmmc_driver);
2454 2455 2456 2457
MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Texas Instruments Inc");