apic.c 61.1 KB
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/*
 *	Local APIC handling, local APIC timers
 *
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 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

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#include <linux/perf_event.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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#include <linux/delay.h>
#include <linux/timex.h>
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#include <linux/i8253.h>
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#include <linux/dmar.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
#include <linux/smp.h>
#include <linux/mm.h>
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#include <asm/trace/irq_vectors.h>
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#include <asm/irq_remapping.h>
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#include <asm/perf_event.h>
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
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#include <linux/atomic.h>
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#include <asm/mpspec.h>
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/idle.h>
#include <asm/mtrr.h>
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#include <asm/time.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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#include <asm/tsc.h>
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#include <asm/hypervisor.h>
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unsigned int num_processors;
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unsigned disabled_cpus;
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/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
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EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
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/*
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 * The highest APIC ID seen during enumeration.
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 */
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static unsigned int max_physical_apicid;
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/*
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 * Bitmask of physically existing CPUs:
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 */
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physid_mask_t phys_cpu_present_map;

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/*
 * Processor to be disabled specified by kernel parameter
 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
 * avoid undefined behaviour caused by sending INIT from AP to BSP.
 */
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static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
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/*
 * Map cpu index to physical APIC ID
 */
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DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
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EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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#ifdef CONFIG_X86_32
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/*
 * On x86_32, the mapping between cpu and logical apicid may vary
 * depending on apic in use.  The following early percpu variable is
 * used for the mapping.  This is where the behaviors of x86_64 and 32
 * actually diverge.  Let's keep it ugly for now.
 */
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DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
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static inline void imcr_pic_to_apic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

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static inline void imcr_apic_to_pic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
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#endif

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/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
static int force_enable_local_apic __initdata;
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/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
	if (config_enabled(CONFIG_X86_32) && !arg)
		force_enable_local_apic = 1;
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	else if (arg && !strncmp(arg, "notscdeadline", 13))
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		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
	return 0;
}
early_param("lapic", parse_lapic);

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#ifdef CONFIG_X86_64
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static int apic_calibrate_pmtmr __initdata;
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static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
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static int disable_apic_timer __initdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

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int first_system_vector = FIRST_SYSTEM_VECTOR;
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/*
 * Debug level, exported for io_apic.c
 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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unsigned int lapic_timer_frequency = 0;
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static void apic_pm_activate(void);
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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
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	return 1;
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#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
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}

/*
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 * Check, whether this is a modern or a first generation APIC
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 */
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static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
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 * right after this call apic become NOOP driven
 * so apic->write/read doesn't do anything
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 */
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static void __init apic_disable(void)
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{
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	pr_info("APIC: switched to apic NOOP\n");
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	apic = &apic_noop;
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}

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void native_apic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 native_safe_apic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
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		inc_irq_stat(icr_read_retry_count);
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		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void native_apic_icr_write(u32 low, u32 id)
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{
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	unsigned long flags;

	local_irq_save(flags);
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
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	apic_write(APIC_ICR, low);
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	local_irq_restore(flags);
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}

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u64 native_apic_icr_read(void)
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{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

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	return icr1 | ((u64)icr2 << 32);
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}

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#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
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int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
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	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#define APIC_DIVISOR 16
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#define TSC_DIVISOR  32
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;

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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
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	apic_write(APIC_LVTT, lvtt_value);
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	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
		return;
	}

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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
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 * Setup extended LVT, AMD specific
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 *
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 * Software should use the LVT offsets the BIOS provides.  The offsets
 * are determined by the subsystems using it like those for MCE
 * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
 * are supported. Beginning with family 10h at least 4 offsets are
 * available.
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 *
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 * Since the offsets must be consistent for all cores, we keep track
 * of the LVT offsets in software and reserve the offset for the same
 * vector also to be used on other cores. An offset is freed by
 * setting the entry to APIC_EILVT_MASKED.
 *
 * If the BIOS is right, there should be no conflicts. Otherwise a
 * "[Firmware Bug]: ..." error message is generated. However, if
 * software does not properly determines the offsets, it is not
 * necessarily a BIOS bug.
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 */
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static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];

static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
{
	return (old & APIC_EILVT_MASKED)
		|| (new == APIC_EILVT_MASKED)
		|| ((new & ~APIC_EILVT_MASKED) == old);
}

static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
{
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	unsigned int rsvd, vector;
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	if (offset >= APIC_EILVT_NR_MAX)
		return ~0;

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	rsvd = atomic_read(&eilvt_offsets[offset]);
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	do {
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		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
		if (vector && !eilvt_entry_is_changeable(vector, new))
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			/* may not change if vectors are different */
			return rsvd;
		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
	} while (rsvd != new);

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	rsvd &= ~APIC_EILVT_MASKED;
	if (rsvd && rsvd != vector)
		pr_info("LVT offset %d assigned for vector 0x%02x\n",
			offset, rsvd);

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	return new;
}

/*
 * If mask=1, the LVT entry does not generate interrupts while mask=0
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 * enables the vector. See also the BKDGs. Must be called with
 * preemption disabled.
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 */

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int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
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{
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	unsigned long reg = APIC_EILVTn(offset);
	unsigned int new, old, reserved;

	new = (mask << 16) | (msg_type << 8) | vector;
	old = apic_read(reg);
	reserved = reserve_eilvt_offset(offset, new);

	if (reserved != new) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on another cpu\n",
		       smp_processor_id(), reg, offset, new, reserved);
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		return -EINVAL;
	}

	if (!eilvt_entry_is_changeable(old, new)) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on this cpu\n",
		       smp_processor_id(), reg, offset, new, old);
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		return -EBUSY;
	}

	apic_write(reg, new);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
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{
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	apic_write(APIC_TMICT, delta);
	return 0;
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}

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static int lapic_next_deadline(unsigned long delta,
			       struct clock_event_device *evt)
{
	u64 tsc;

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	tsc = native_read_tsc();
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	wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
	return 0;
}

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/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
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{
	unsigned long flags;
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return;

	local_irq_save(flags);

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	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
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		__setup_APIC_LVTT(lapic_timer_frequency,
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				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, v);
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		apic_write(APIC_TMICT, 0);
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		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
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	local_irq_restore(flags);
}

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/*
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 * Local APIC timer broadcast function
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 */
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static void lapic_timer_broadcast(const struct cpumask *mask)
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{
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#ifdef CONFIG_SMP
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	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
}
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

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/*
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 * Setup the local APIC timer for this CPU. Copy the initialized values
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 * of the boot CPU and register the clock event in the framework.
 */
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static void setup_APIC_timer(void)
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{
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	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
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	if (this_cpu_has(X86_FEATURE_ARAT)) {
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		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

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	memcpy(levt, &lapic_clockevent, sizeof(*levt));
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	levt->cpumask = cpumask_of(smp_processor_id());
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	if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
		levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
				    CLOCK_EVT_FEAT_DUMMY);
		levt->set_next_event = lapic_next_deadline;
		clockevents_config_and_register(levt,
						(tsc_khz / TSC_DIVISOR) * 1000,
						0xF, ~0UL);
	} else
		clockevents_register_device(levt);
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}
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/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

	if (cpu_has_tsc)
595
		tsc = native_read_tsc();
596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

616 617
static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
618 619 620 621 622 623 624 625 626 627
{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

Y
Yasuaki Ishimatsu 已提交
628
	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
629 630 631 632 633 634 635 636 637

	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
Y
Yasuaki Ishimatsu 已提交
638
		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
639 640 641 642 643 644
		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
Y
Yasuaki Ishimatsu 已提交
645
		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
646 647 648 649 650 651 652 653 654 655 656

	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
	if (cpu_has_tsc) {
		res = (((u64)(*deltatsc)) * pm_100ms);
657
		do_div(res, deltapm);
658
		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
659
					  "PM-Timer: %lu (%ld)\n",
660 661
					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
662 663 664 665 666
	}

	return 0;
}

667 668
static int __init calibrate_APIC_clock(void)
{
669
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
670 671
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
672
	long delta, deltatsc;
673 674
	int pm_referenced = 0;

675 676 677 678 679 680
	/**
	 * check if lapic timer has already been calibrated by platform
	 * specific routine, such as tsc calibration code. if so, we just fill
	 * in the clockevent structure and return.
	 */

681 682 683
	if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
		return 0;
	} else if (lapic_timer_frequency) {
684 685 686 687 688 689 690 691 692 693 694 695
		apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
				lapic_timer_frequency);
		lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
					TICK_NSEC, lapic_clockevent.shift);
		lapic_clockevent.max_delta_ns =
			clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
		lapic_clockevent.min_delta_ns =
			clockevent_delta2ns(0xF, &lapic_clockevent);
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
		return 0;
	}

696 697 698
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

699 700 701 702 703 704 705
	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
706
	 * Setup the APIC counter to maximum. There is no way the lapic
707 708
	 * can underflow in the 100ms detection time frame
	 */
C
Cyrill Gorcunov 已提交
709
	__setup_APIC_LVTT(0xffffffff, 0, 0);
710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

726 727
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

728 729
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
730
					&delta, &deltatsc);
731 732 733 734 735

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
736
		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
737 738 739
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

740
	lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
741 742

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
743
	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
744
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
745
		    lapic_timer_frequency);
746 747 748 749

	if (cpu_has_tsc) {
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
750 751
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
752 753 754 755
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
756 757
		    lapic_timer_frequency / (1000000 / HZ),
		    lapic_timer_frequency % (1000000 / HZ));
758 759 760 761

	/*
	 * Do a sanity check on the APIC calibration result
	 */
762
	if (lapic_timer_frequency < (1000000 / HZ)) {
763
		local_irq_enable();
764
		pr_warning("APIC frequency too slow, disabling apic timer\n");
765 766 767 768 769
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

770 771 772 773
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
	} else
		local_irq_enable();

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
806
		pr_warning("APIC timer disabled due to verification failure\n");
807 808 809 810 811 812
			return -1;
	}

	return 0;
}

H
Hiroshi Shimamoto 已提交
813 814 815 816 817
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
818 819 820
void __init setup_boot_APIC_clock(void)
{
	/*
821 822 823 824
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
825 826
	 */
	if (disable_apic_timer) {
827
		pr_info("Disabling APIC timer\n");
828
		/* No broadcast on UP ! */
829 830
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
831
			setup_APIC_timer();
832
		}
833 834 835
		return;
	}

836
	if (calibrate_APIC_clock()) {
837 838 839 840 841 842
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

843 844 845 846 847
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
848
	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
849

850
	/* Setup the lapic or request the broadcast */
851 852 853
	setup_APIC_timer();
}

854
void setup_secondary_APIC_clock(void)
855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
{
	setup_APIC_timer();
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
879
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
880 881 882 883 884 885 886 887
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
888
	inc_irq_stat(apic_timer_irqs);
889 890 891 892 893 894 895 896 897 898 899 900

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
901
__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
902 903 904 905 906 907
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
908
	 *
909 910 911 912
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
913
	entering_ack_irq();
914
	local_apic_timer_interrupt();
915
	exiting_irq();
916

917 918 919
	set_irq_regs(old_regs);
}

920
__visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
921 922 923
{
	struct pt_regs *old_regs = set_irq_regs(regs);

924
	/*
925 926 927
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 *
928 929 930 931
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
932 933
	entering_ack_irq();
	trace_local_timer_entry(LOCAL_TIMER_VECTOR);
934
	local_apic_timer_interrupt();
935 936
	trace_local_timer_exit(LOCAL_TIMER_VECTOR);
	exiting_irq();
937

938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
959
	int maxlvt;
960 961
	u32 v;

962
	/* APIC hasn't been mapped yet */
963
	if (!x2apic_mode && !apic_phys)
964 965 966
		return;

	maxlvt = lapic_get_maxlvt();
967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

990
	/* lets not touch this if we didn't frob it */
991
#ifdef CONFIG_X86_THERMAL_VECTOR
992 993 994 995 996
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
997 998 999 1000 1001 1002 1003 1004
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

1005 1006 1007 1008 1009 1010 1011 1012 1013 1014
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1015 1016 1017 1018 1019 1020 1021 1022

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
1023 1024 1025 1026 1027 1028 1029 1030 1031
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

1032
	/* APIC hasn't been mapped yet */
1033
	if (!x2apic_mode && !apic_phys)
1034 1035
		return;

1036 1037 1038 1039 1040 1041 1042 1043 1044
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
1059 1060
}

1061 1062 1063 1064 1065 1066
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
1067 1068 1069 1070
void lapic_shutdown(void)
{
	unsigned long flags;

1071
	if (!cpu_has_apic && !apic_from_smp_config())
1072 1073 1074 1075
		return;

	local_irq_save(flags);

1076 1077 1078 1079 1080 1081 1082
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

1083 1084 1085 1086 1087 1088 1089

	local_irq_restore(flags);
}

/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
1090 1091
void __init sync_Arb_IDs(void)
{
C
Cyrill Gorcunov 已提交
1092 1093 1094 1095 1096
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
Linus Torvalds 已提交
1097 1098 1099 1100 1101 1102 1103 1104
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1105 1106
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
L
Linus Torvalds 已提交
1107 1108 1109 1110 1111 1112 1113
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1114
	unsigned int value;
L
Linus Torvalds 已提交
1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1134 1135 1136 1137 1138 1139 1140 1141 1142

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
L
Linus Torvalds 已提交
1143
	value |= SPURIOUS_APIC_VECTOR;
1144
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1145 1146 1147 1148

	/*
	 * Set up the virtual wire mode.
	 */
1149
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1150
	value = APIC_DM_NMI;
1151 1152
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1153
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1154 1155
}

1156
static void lapic_setup_esr(void)
1157
{
1158 1159 1160
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1161
		pr_info("No ESR for 82489DX.\n");
1162 1163
		return;
	}
1164

1165
	if (apic->disable_esr) {
1166
		/*
1167 1168 1169 1170
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1171
		 */
1172
		pr_info("Leaving ESR disabled.\n");
1173
		return;
1174
	}
1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1195 1196
}

1197 1198
/**
 * setup_local_APIC - setup the local APIC
1199 1200 1201
 *
 * Used to setup local APIC while initializing BSP or bringin up APs.
 * Always called with preemption disabled.
1202
 */
1203
void setup_local_APIC(void)
L
Linus Torvalds 已提交
1204
{
1205
	int cpu = smp_processor_id();
1206 1207 1208
	unsigned int value, queued;
	int i, j, acked = 0;
	unsigned long long tsc = 0, ntsc;
1209
	long long max_loops = cpu_khz ? cpu_khz : 1000000;
1210 1211

	if (cpu_has_tsc)
1212
		tsc = native_read_tsc();
L
Linus Torvalds 已提交
1213

J
Jan Beulich 已提交
1214
	if (disable_apic) {
1215
		disable_ioapic_support();
J
Jan Beulich 已提交
1216 1217 1218
		return;
	}

1219 1220
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1221
	if (lapic_is_integrated() && apic->disable_esr) {
1222 1223 1224 1225 1226 1227
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1228
	perf_events_lapic_init();
1229

L
Linus Torvalds 已提交
1230 1231 1232 1233
	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1234
	BUG_ON(!apic->apic_id_registered());
L
Linus Torvalds 已提交
1235 1236 1237 1238 1239 1240

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1241
	apic->init_apic_ldr();
L
Linus Torvalds 已提交
1242

1243 1244
#ifdef CONFIG_X86_32
	/*
1245 1246 1247
	 * APIC LDR is initialized.  If logical_apicid mapping was
	 * initialized during get_smp_config(), make sure it matches the
	 * actual value.
1248
	 */
1249 1250 1251
	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
	/* always use the value from LDR */
1252 1253 1254 1255
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		logical_smp_processor_id();
#endif

L
Linus Torvalds 已提交
1256 1257 1258 1259 1260 1261
	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1262
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
1263

1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
	do {
		queued = 0;
		for (i = APIC_ISR_NR - 1; i >= 0; i--)
			queued |= apic_read(APIC_IRR + i*0x10);

		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
			value = apic_read(APIC_ISR + i*0x10);
			for (j = 31; j >= 0; j--) {
				if (value & (1<<j)) {
					ack_APIC_irq();
					acked++;
				}
			}
1288
		}
1289 1290 1291 1292 1293
		if (acked > 256) {
			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
			       acked);
			break;
		}
1294
		if (queued) {
1295
			if (cpu_has_tsc && cpu_khz) {
1296
				ntsc = native_read_tsc();
1297 1298 1299 1300
				max_loops = (cpu_khz << 10) - (ntsc - tsc);
			} else
				max_loops--;
		}
1301 1302
	} while (queued && max_loops > 0);
	WARN_ON(max_loops <= 0);
1303

L
Linus Torvalds 已提交
1304 1305 1306 1307 1308 1309 1310 1311 1312 1313
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 * See also the comment in end_level_ioapic_irq().  --macro
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1342

L
Linus Torvalds 已提交
1343 1344 1345 1346
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1347
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1360
	if (!cpu && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1361
		value = APIC_DM_EXTINT;
1362
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1363 1364
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1365
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1366
	}
1367
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1368 1369 1370 1371

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
1372
	if (!cpu)
L
Linus Torvalds 已提交
1373 1374 1375
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1376 1377
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1378
	apic_write(APIC_LVT1, value);
1379

1380 1381
#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
1382
	if (!cpu)
1383 1384
		cmci_recheck();
#endif
1385
}
L
Linus Torvalds 已提交
1386

1387
static void end_local_APIC_setup(void)
1388 1389
{
	lapic_setup_esr();
1390 1391

#ifdef CONFIG_X86_32
1392 1393 1394 1395 1396 1397 1398
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1399 1400
#endif

1401
	apic_pm_activate();
1402 1403
}

1404 1405 1406 1407
/*
 * APIC setup function for application processors. Called from smpboot.c
 */
void apic_ap_setup(void)
1408
{
1409
	setup_local_APIC();
1410
	end_local_APIC_setup();
L
Linus Torvalds 已提交
1411 1412
}

Y
Yinghai Lu 已提交
1413
#ifdef CONFIG_X86_X2APIC
1414
int x2apic_mode;
1415 1416 1417 1418 1419 1420 1421 1422

enum {
	X2APIC_OFF,
	X2APIC_ON,
	X2APIC_DISABLED,
};
static int x2apic_state;

1423 1424 1425 1426
static inline void __x2apic_disable(void)
{
	u64 msr;

1427 1428 1429
	if (cpu_has_apic)
		return;

1430 1431 1432 1433 1434 1435 1436 1437 1438
	rdmsrl(MSR_IA32_APICBASE, msr);
	if (!(msr & X2APIC_ENABLE))
		return;
	/* Disable xapic and x2apic first and then reenable xapic mode */
	wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
	wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic disabled\n");
}

1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449
static inline void __x2apic_enable(void)
{
	u64 msr;

	rdmsrl(MSR_IA32_APICBASE, msr);
	if (msr & X2APIC_ENABLE)
		return;
	wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic enabled\n");
}

1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
static int __init setup_nox2apic(char *str)
{
	if (x2apic_enabled()) {
		int apicid = native_apic_msr_read(APIC_ID);

		if (apicid >= 255) {
			pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
				   apicid);
			return 0;
		}
1460 1461 1462 1463
		pr_warning("x2apic already enabled.\n");
		__x2apic_disable();
	}
	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1464
	x2apic_state = X2APIC_DISABLED;
1465
	x2apic_mode = 0;
1466 1467 1468 1469
	return 0;
}
early_param("nox2apic", setup_nox2apic);

1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
/* Called from cpu_init() to enable x2apic on (secondary) cpus */
void x2apic_setup(void)
{
	/*
	 * If x2apic is not in ON state, disable it if already enabled
	 * from BIOS.
	 */
	if (x2apic_state != X2APIC_ON) {
		__x2apic_disable();
		return;
	}
	__x2apic_enable();
}

1484
static __init void x2apic_disable(void)
1485
{
1486
	u32 x2apic_id;
1487

1488 1489
	if (x2apic_state != X2APIC_ON)
		goto out;
1490

1491 1492 1493
	x2apic_id = read_apic_id();
	if (x2apic_id >= 255)
		panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1494

1495 1496 1497
	__x2apic_disable();
	register_lapic_address(mp_lapic_addr);
out:
1498
	x2apic_state = X2APIC_DISABLED;
1499
	x2apic_mode = 0;
1500 1501
}

1502
static __init void x2apic_enable(void)
1503
{
1504
	if (x2apic_state != X2APIC_OFF)
Y
Yinghai Lu 已提交
1505 1506
		return;

1507
	x2apic_mode = 1;
1508
	x2apic_state = X2APIC_ON;
1509
	__x2apic_enable();
1510
}
T
Thomas Gleixner 已提交
1511

1512
static __init void try_to_enable_x2apic(int remap_mode)
1513
{
1514
	if (x2apic_state == X2APIC_DISABLED)
1515 1516
		return;

1517
	if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1518 1519 1520 1521
		/* IR is required if there is APIC ID > 255 even when running
		 * under KVM
		 */
		if (max_physical_apicid > 255 ||
1522
		    !hypervisor_x2apic_available()) {
1523
			pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1524
			x2apic_disable();
1525 1526 1527 1528 1529 1530 1531
			return;
		}

		/*
		 * without IR all CPUs can be addressed by IOAPIC/MSI
		 * only in physical mode
		 */
1532
		x2apic_phys = 1;
1533
	}
1534
	x2apic_enable();
1535 1536 1537 1538 1539 1540 1541
}

void __init check_x2apic(void)
{
	if (x2apic_enabled()) {
		pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
		x2apic_mode = 1;
1542 1543 1544
		x2apic_state = X2APIC_ON;
	} else if (!cpu_has_x2apic) {
		x2apic_state = X2APIC_DISABLED;
1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558
	}
}
#else /* CONFIG_X86_X2APIC */
static int __init validate_x2apic(void)
{
	if (!apic_is_x2apic_enabled())
		return 0;
	/*
	 * Checkme: Can we simply turn off x2apic here instead of panic?
	 */
	panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
}
early_initcall(validate_x2apic);

1559
static inline void try_to_enable_x2apic(int remap_mode) { }
1560
static inline void __x2apic_enable(void) { }
1561 1562 1563 1564 1565 1566 1567 1568 1569
#endif /* !CONFIG_X86_X2APIC */

static int __init try_to_enable_IR(void)
{
#ifdef CONFIG_X86_IO_APIC
	if (!x2apic_enabled() && skip_ioapic_setup) {
		pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
		return -1;
	}
1570
#endif
1571
	return irq_remapping_enable();
1572 1573 1574 1575 1576
}

void __init enable_IR_x2apic(void)
{
	unsigned long flags;
1577
	int ret, ir_stat;
1578

1579 1580
	ir_stat = irq_remapping_prepare();
	if (ir_stat < 0 && !x2apic_supported())
Y
Yinghai Lu 已提交
1581
		return;
1582

1583
	ret = save_ioapic_entries();
1584
	if (ret) {
1585
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1586
		return;
1587
	}
1588

1589
	local_irq_save(flags);
1590
	legacy_pic->mask_all();
1591
	mask_ioapic_entries();
1592

1593 1594 1595 1596 1597
	/* If irq_remapping_prepare() succeded, try to enable it */
	if (ir_stat >= 0)
		ir_stat = try_to_enable_IR();
	/* ir_stat contains the remap mode or an error code */
	try_to_enable_x2apic(ir_stat);
1598

1599
	if (ir_stat < 0)
1600
		restore_ioapic_entries();
1601
	legacy_pic->restore_mask();
1602 1603
	local_irq_restore(flags);
}
1604

1605
#ifdef CONFIG_X86_64
L
Linus Torvalds 已提交
1606 1607 1608 1609
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1610
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1611
 */
1612
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1613 1614
{
	if (!cpu_has_apic) {
1615
		pr_info("No local APIC present\n");
L
Linus Torvalds 已提交
1616 1617 1618 1619 1620 1621
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1622
#else
1623

1624
static int __init apic_verify(void)
1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640
{
	u32 features, h, l;

	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
		pr_warning("Could not enable APIC!\n");
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
1641 1642 1643 1644 1645
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (l & MSR_IA32_APICBASE_ENABLE)
			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
	}
1646 1647 1648 1649 1650

	pr_info("Found and enabled local APIC!\n");
	return 0;
}

1651
int __init apic_force_enable(unsigned long addr)
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662
{
	u32 h, l;

	if (disable_apic)
		return -1;

	/*
	 * Some BIOSes disable the local APIC in the APIC_BASE
	 * MSR. This can only be done in software for Intel P6 or later
	 * and AMD K7 (Model > 1) or later.
	 */
1663 1664 1665 1666 1667 1668 1669 1670 1671
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
1672 1673 1674 1675
	}
	return apic_verify();
}

1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1688
		    (boot_cpu_data.x86 >= 15))
1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

	if (!cpu_has_apic) {
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1706 1707
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1708 1709
			return -1;
		}
1710
		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1711 1712 1713 1714
			return -1;
	} else {
		if (apic_verify())
			return -1;
1715 1716 1717 1718 1719 1720 1721
	}

	apic_pm_activate();

	return 0;

no_apic:
1722
	pr_info("No local APIC present or hardware disabled\n");
1723 1724 1725
	return -1;
}
#endif
L
Linus Torvalds 已提交
1726

1727 1728 1729
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
1730 1731
void __init init_apic_mappings(void)
{
1732 1733
	unsigned int new_apicid;

1734
	if (x2apic_mode) {
1735
		boot_cpu_physical_apicid = read_apic_id();
1736 1737 1738
		return;
	}

1739
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1740
	if (!smp_found_config && detect_init_APIC()) {
1741 1742 1743 1744
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1745 1746
		apic_phys = mp_lapic_addr;

1747 1748 1749 1750
		/*
		 * acpi lapic path already maps that address in
		 * acpi_register_lapic_address()
		 */
1751
		if (!acpi_lapic && !smp_found_config)
1752
			register_lapic_address(apic_phys);
1753
	}
L
Linus Torvalds 已提交
1754 1755 1756 1757 1758

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1759 1760 1761
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1762 1763 1764 1765 1766 1767 1768
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1769 1770
		apic_version[new_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
1771
	}
L
Linus Torvalds 已提交
1772 1773
}

1774 1775 1776 1777
void __init register_lapic_address(unsigned long address)
{
	mp_lapic_addr = address;

1778 1779 1780 1781 1782
	if (!x2apic_mode) {
		set_fixmap_nocache(FIX_APIC_BASE, address);
		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
			    APIC_BASE, mp_lapic_addr);
	}
1783 1784 1785 1786 1787 1788 1789
	if (boot_cpu_physical_apicid == -1U) {
		boot_cpu_physical_apicid  = read_apic_id();
		apic_version[boot_cpu_physical_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
	}
}

1790
int apic_version[MAX_LOCAL_APIC];
1791

L
Linus Torvalds 已提交
1792
/*
1793
 * Local APIC interrupts
L
Linus Torvalds 已提交
1794 1795
 */

1796 1797 1798
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1799
static inline void __smp_spurious_interrupt(u8 vector)
L
Linus Torvalds 已提交
1800
{
1801 1802
	u32 v;

L
Linus Torvalds 已提交
1803
	/*
1804 1805 1806
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1807
	 */
1808 1809
	v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
	if (v & (1 << (vector & 0x1f)))
1810
		ack_APIC_irq();
1811

1812 1813
	inc_irq_stat(irq_spurious_count);

1814
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1815 1816
	pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
		"should never happen.\n", vector, smp_processor_id());
1817 1818
}

1819
__visible void smp_spurious_interrupt(struct pt_regs *regs)
1820 1821
{
	entering_irq();
1822
	__smp_spurious_interrupt(~regs->orig_ax);
1823
	exiting_irq();
1824
}
L
Linus Torvalds 已提交
1825

1826
__visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1827
{
1828 1829
	u8 vector = ~regs->orig_ax;

1830
	entering_irq();
1831 1832 1833
	trace_spurious_apic_entry(vector);
	__smp_spurious_interrupt(vector);
	trace_spurious_apic_exit(vector);
1834
	exiting_irq();
1835
}
L
Linus Torvalds 已提交
1836

1837 1838 1839
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1840
static inline void __smp_error_interrupt(struct pt_regs *regs)
1841
{
1842
	u32 v;
1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853
	u32 i = 0;
	static const char * const error_interrupt_reason[] = {
		"Send CS error",		/* APIC Error Bit 0 */
		"Receive CS error",		/* APIC Error Bit 1 */
		"Send accept error",		/* APIC Error Bit 2 */
		"Receive accept error",		/* APIC Error Bit 3 */
		"Redirectable IPI",		/* APIC Error Bit 4 */
		"Send illegal vector",		/* APIC Error Bit 5 */
		"Received illegal vector",	/* APIC Error Bit 6 */
		"Illegal register address",	/* APIC Error Bit 7 */
	};
L
Linus Torvalds 已提交
1854

1855
	/* First tickle the hardware, only then report what went on. -- REW */
1856 1857
	if (lapic_get_maxlvt() > 3)	/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
1858
	v = apic_read(APIC_ESR);
1859 1860
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
1861

1862 1863
	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
		    smp_processor_id(), v);
1864

1865 1866 1867
	v &= 0xff;
	while (v) {
		if (v & 0x1)
1868 1869
			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
		i++;
1870
		v >>= 1;
1871
	}
1872 1873 1874

	apic_printk(APIC_DEBUG, KERN_CONT "\n");

1875 1876
}

1877
__visible void smp_error_interrupt(struct pt_regs *regs)
1878 1879 1880 1881
{
	entering_irq();
	__smp_error_interrupt(regs);
	exiting_irq();
L
Linus Torvalds 已提交
1882 1883
}

1884
__visible void smp_trace_error_interrupt(struct pt_regs *regs)
1885 1886 1887 1888 1889 1890
{
	entering_irq();
	trace_error_apic_entry(ERROR_APIC_VECTOR);
	__smp_error_interrupt(regs);
	trace_error_apic_exit(ERROR_APIC_VECTOR);
	exiting_irq();
L
Linus Torvalds 已提交
1891 1892
}

1893
/**
1894 1895
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
1896
static void __init connect_bsp_APIC(void)
1897
{
1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
1910
		imcr_pic_to_apic();
1911 1912
	}
#endif
1913 1914
}

1915 1916 1917 1918 1919 1920 1921
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
1922
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1923
{
1924 1925
	unsigned int value;

1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
1936
		imcr_apic_to_pic();
1937 1938 1939 1940
		return;
	}
#endif

1941
	/* Go back to Virtual Wire compatibility mode */
L
Linus Torvalds 已提交
1942

1943 1944 1945 1946 1947 1948
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
1949

1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
1966

1967 1968 1969 1970
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
1971 1972 1973 1974 1975 1976 1977
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1978 1979
}

1980
int generic_processor_info(int apicid, int version)
1981
{
1982 1983 1984 1985
	int cpu, max = nr_cpu_ids;
	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
				phys_cpu_present_map);

1986 1987 1988 1989
	/*
	 * boot_cpu_physical_apicid is designed to have the apicid
	 * returned by read_apic_id(), i.e, the apicid of the
	 * currently booting-up processor. However, on some platforms,
1990
	 * it is temporarily modified by the apicid reported as BSP
1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
	 * through MP table. Concretely:
	 *
	 * - arch/x86/kernel/mpparse.c: MP_processor_info()
	 * - arch/x86/mm/amdtopology.c: amd_numa_init()
	 *
	 * This function is executed with the modified
	 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
	 * parameter doesn't work to disable APs on kdump 2nd kernel.
	 *
	 * Since fixing handling of boot_cpu_physical_apicid requires
	 * another discussion and tests on each platform, we leave it
	 * for now and here we use read_apic_id() directly in this
	 * function, generic_processor_info().
	 */
	if (disabled_cpu_apicid != BAD_APICID &&
	    disabled_cpu_apicid != read_apic_id() &&
	    disabled_cpu_apicid == apicid) {
		int thiscpu = num_processors + disabled_cpus;

2010
		pr_warning("APIC: Disabling requested cpu."
2011 2012 2013 2014 2015 2016 2017
			   " Processor %d/0x%x ignored.\n",
			   thiscpu, apicid);

		disabled_cpus++;
		return -ENODEV;
	}

2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031
	/*
	 * If boot cpu has not been detected yet, then only allow upto
	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
	 */
	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
	    apicid != boot_cpu_physical_apicid) {
		int thiscpu = max + disabled_cpus - 1;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i almost"
			" reached. Keeping one slot for boot cpu."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
2032
		return -ENODEV;
2033
	}
2034

2035 2036 2037 2038 2039 2040 2041 2042
	if (num_processors >= nr_cpu_ids) {
		int thiscpu = max + disabled_cpus;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i reached."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
2043
		return -EINVAL;
2044 2045 2046 2047 2048 2049 2050 2051
	}

	num_processors++;
	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
2052 2053
		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
		 * for BSP.
2054 2055
		 */
		cpu = 0;
2056 2057 2058 2059 2060 2061 2062 2063 2064 2065
	} else
		cpu = cpumask_next_zero(-1, cpu_present_mask);

	/*
	 * Validate version
	 */
	if (version == 0x0) {
		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
			   cpu, apicid);
		version = 0x10;
2066
	}
2067 2068 2069 2070 2071 2072 2073 2074
	apic_version[apicid] = version;

	if (version != apic_version[boot_cpu_physical_apicid]) {
		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
			apic_version[boot_cpu_physical_apicid], cpu, version);
	}

	physid_set(apicid, phys_cpu_present_map);
2075 2076 2077
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

2078
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2079 2080
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2081
#endif
2082 2083 2084 2085
#ifdef CONFIG_X86_32
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		apic->x86_32_early_logical_apicid(cpu);
#endif
2086 2087
	set_cpu_possible(cpu, true);
	set_cpu_present(cpu, true);
2088 2089

	return cpu;
2090 2091
}

2092 2093 2094 2095
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

2107 2108 2109
int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
				   const struct cpumask *andmask,
				   unsigned int *apicid)
2110
{
2111
	unsigned int cpu;
2112 2113 2114 2115 2116

	for_each_cpu_and(cpu, cpumask, andmask) {
		if (cpumask_test_cpu(cpu, cpu_online_mask))
			break;
	}
2117

2118
	if (likely(cpu < nr_cpu_ids)) {
2119 2120 2121
		*apicid = per_cpu(x86_cpu_to_apicid, cpu);
		return 0;
	}
2122 2123

	return -EINVAL;
2124 2125
}

2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142
/*
 * Override the generic EOI implementation with an optimized version.
 * Only called during early boot when only one CPU is active and with
 * interrupts disabled, so we know this does not race with actual APIC driver
 * use.
 */
void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
{
	struct apic **drv;

	for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
		/* Should happen once for each apic */
		WARN_ON((*drv)->eoi_write == eoi_write);
		(*drv)->eoi_write = eoi_write;
	}
}

2143
static void __init apic_bsp_up_setup(void)
2144
{
2145 2146 2147
#ifdef CONFIG_X86_64
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
#else
2148
	/*
2149 2150 2151
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
2152
	 */
2153 2154 2155 2156 2157
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2158 2159 2160 2161
}

/**
 * apic_bsp_setup - Setup function for local apic and io-apic
2162
 * @upmode:		Force UP mode (for APIC_init_uniprocessor)
2163 2164 2165 2166
 *
 * Returns:
 * apic_id of BSP APIC
 */
2167
int __init apic_bsp_setup(bool upmode)
2168 2169 2170 2171
{
	int id;

	connect_bsp_APIC();
2172 2173
	if (upmode)
		apic_bsp_up_setup();
2174 2175 2176 2177 2178 2179 2180 2181
	setup_local_APIC();

	if (x2apic_mode)
		id = apic_read(APIC_LDR);
	else
		id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));

	enable_IO_APIC();
2182 2183
	end_local_APIC_setup();
	irq_remap_enable_fault_handling();
2184
	setup_IO_APIC();
2185 2186
	/* Setup local timer */
	x86_init.timers.setup_percpu_clockev();
2187 2188 2189
	return id;
}

2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220
/*
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
 */
int __init APIC_init_uniprocessor(void)
{
	if (disable_apic) {
		pr_info("Apic disabled\n");
		return -1;
	}
#ifdef CONFIG_X86_64
	if (!cpu_has_apic) {
		disable_apic = 1;
		pr_info("Apic disabled by BIOS\n");
		return -1;
	}
#else
	if (!smp_found_config && !cpu_has_apic)
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
	if (!cpu_has_apic &&
	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
		return -1;
	}
#endif

2221 2222
	if (!smp_found_config)
		disable_ioapic_support();
2223

2224 2225
	default_setup_apic_routing();
	apic_bsp_setup(true);
2226 2227 2228
	return 0;
}

T
Thomas Gleixner 已提交
2229 2230 2231 2232 2233 2234 2235
#ifdef CONFIG_UP_LATE_INIT
void __init up_late_init(void)
{
	APIC_init_uniprocessor();
}
#endif

2236
/*
2237
 * Power management
2238
 */
2239 2240 2241
#ifdef CONFIG_PM

static struct {
2242 2243 2244 2245 2246
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

2264
static int lapic_suspend(void)
2265 2266 2267
{
	unsigned long flags;
	int maxlvt;
2268

2269 2270
	if (!apic_pm_state.active)
		return 0;
2271

2272
	maxlvt = lapic_get_maxlvt();
2273

2274
	apic_pm_state.apic_id = apic_read(APIC_ID);
2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2287
#ifdef CONFIG_X86_THERMAL_VECTOR
2288 2289 2290
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
2291

2292 2293
	local_irq_save(flags);
	disable_local_APIC();
2294

2295
	irq_remapping_disable();
2296

2297 2298
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
2299 2300
}

2301
static void lapic_resume(void)
L
Linus Torvalds 已提交
2302
{
2303 2304
	unsigned int l, h;
	unsigned long flags;
2305
	int maxlvt;
2306

2307
	if (!apic_pm_state.active)
2308
		return;
2309

2310
	local_irq_save(flags);
2311 2312 2313 2314 2315 2316 2317 2318 2319

	/*
	 * IO-APIC and PIC have their own resume routines.
	 * We just mask them here to make sure the interrupt
	 * subsystem is completely quiet while we enable x2apic
	 * and interrupt-remapping.
	 */
	mask_ioapic_entries();
	legacy_pic->mask_all();
C
Cyrill Gorcunov 已提交
2320

2321 2322 2323
	if (x2apic_mode) {
		__x2apic_enable();
	} else {
C
Cyrill Gorcunov 已提交
2324 2325 2326 2327 2328 2329
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2330 2331 2332 2333 2334 2335
		if (boot_cpu_data.x86 >= 6) {
			rdmsr(MSR_IA32_APICBASE, l, h);
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
		}
2336
	}
2337

2338
	maxlvt = lapic_get_maxlvt();
2339 2340 2341 2342 2343 2344 2345 2346
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2347
#if defined(CONFIG_X86_MCE_INTEL)
2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
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Cyrill Gorcunov 已提交
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2362
	irq_remapping_reenable(x2apic_mode);
2363

2364 2365
	local_irq_restore(flags);
}
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Thomas Gleixner 已提交
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2367 2368 2369 2370 2371
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2372
static struct syscore_ops lapic_syscore_ops = {
2373 2374 2375
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
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2376

2377
static void apic_pm_activate(void)
2378 2379
{
	apic_pm_state.active = 1;
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Linus Torvalds 已提交
2380 2381
}

2382
static int __init init_lapic_sysfs(void)
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2383
{
2384
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2385 2386
	if (cpu_has_apic)
		register_syscore_ops(&lapic_syscore_ops);
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Hiroshi Shimamoto 已提交
2387

2388
	return 0;
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Linus Torvalds 已提交
2389
}
2390 2391 2392

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2393 2394 2395 2396 2397 2398

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
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Linus Torvalds 已提交
2399

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Yinghai Lu 已提交
2400
#ifdef CONFIG_X86_64
2401

2402 2403
static int multi_checked;
static int multi;
2404

2405
static int set_multi(const struct dmi_system_id *d)
2406 2407 2408
{
	if (multi)
		return 0;
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Cyrill Gorcunov 已提交
2409
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2410 2411 2412 2413
	multi = 1;
	return 0;
}

2414
static const struct dmi_system_id multi_dmi_table[] = {
2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

2426
static void dmi_check_multi(void)
2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
2443
int apic_is_clustered_box(void)
2444 2445
{
	dmi_check_multi();
2446
	return multi;
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2447
}
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Yinghai Lu 已提交
2448
#endif
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2449 2450

/*
2451
 * APIC command line parameters
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2452
 */
2453
static int __init setup_disableapic(char *arg)
2454
{
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2455
	disable_apic = 1;
2456
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2457 2458 2459
	return 0;
}
early_param("disableapic", setup_disableapic);
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Linus Torvalds 已提交
2460

2461
/* same as disableapic, for compatibility */
2462
static int __init setup_nolapic(char *arg)
2463
{
2464
	return setup_disableapic(arg);
2465
}
2466
early_param("nolapic", setup_nolapic);
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Linus Torvalds 已提交
2467

2468 2469 2470 2471 2472 2473 2474
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2475
static int __init parse_disable_apic_timer(char *arg)
2476
{
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Linus Torvalds 已提交
2477
	disable_apic_timer = 1;
2478
	return 0;
2479
}
2480 2481 2482 2483 2484 2485
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2486
}
2487
early_param("nolapic_timer", parse_nolapic_timer);
2488

2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2504
		pr_warning("APIC Verbosity level %s not recognised"
2505 2506 2507 2508 2509 2510 2511 2512
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);
2531 2532 2533 2534 2535 2536 2537 2538 2539

static int __init apic_set_disabled_cpu_apicid(char *arg)
{
	if (!arg || !get_option(&arg, &disabled_cpu_apicid))
		return -EINVAL;

	return 0;
}
early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);