apic.c 54.9 KB
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/*
 *	Local APIC handling, local APIC timers
 *
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 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

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#include <linux/perf_counter.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/timex.h>
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#include <linux/dmar.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
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#include <linux/nmi.h>
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#include <linux/smp.h>
#include <linux/mm.h>
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#include <asm/perf_counter.h>
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#include <asm/pgalloc.h>
#include <asm/atomic.h>
#include <asm/mpspec.h>
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#include <asm/i8253.h>
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/idle.h>
#include <asm/mtrr.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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unsigned int num_processors;
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unsigned disabled_cpus __cpuinitdata;
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/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
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/*
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 * The highest APIC ID seen during enumeration.
 *
 * This determines the messaging protocol we can use: if all APIC IDs
 * are in the 0 ... 7 range, then we can use logical addressing which
 * has some performance advantages (better broadcasting).
 *
 * If there's an APIC ID above 8, we use physical addressing.
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 */
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unsigned int max_physical_apicid;
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/*
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 * Bitmask of physically existing CPUs:
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 */
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physid_mask_t phys_cpu_present_map;

/*
 * Map cpu index to physical APIC ID
 */
DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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#ifdef CONFIG_X86_32
/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
static int force_enable_local_apic;
/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
	force_enable_local_apic = 1;
	return 0;
}
early_param("lapic", parse_lapic);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
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static inline void imcr_pic_to_apic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

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static inline void imcr_apic_to_pic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
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#endif

#ifdef CONFIG_X86_64
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static int apic_calibrate_pmtmr __initdata;
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static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

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int x2apic_mode;
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#ifdef CONFIG_X86_X2APIC
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/* x2apic enabled before OS handover */
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static int x2apic_preenabled;
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static __init int setup_nox2apic(char *str)
{
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	if (x2apic_enabled()) {
		pr_warning("Bios already enabled x2apic, "
			   "can't enforce nox2apic");
		return 0;
	}

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	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
	return 0;
}
early_param("nox2apic", setup_nox2apic);
#endif
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unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
static int disable_apic_timer __cpuinitdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

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int first_system_vector = 0xfe;

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/*
 * Debug level, exported for io_apic.c
 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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static unsigned int calibration_result;

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static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt);
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt);
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static void lapic_timer_broadcast(const struct cpumask *mask);
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static void apic_pm_activate(void);
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
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static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
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	return 1;
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#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
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}

/*
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 * Check, whether this is a modern or a first generation APIC
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 */
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static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
 * bare function to substitute write operation
 * and it's _that_ fast :)
 */
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static void native_apic_write_dummy(u32 reg, u32 v)
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{
	WARN_ON_ONCE((cpu_has_apic || !disable_apic));
}

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static u32 native_apic_read_dummy(u32 reg)
{
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	WARN_ON_ONCE((cpu_has_apic && !disable_apic));
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	return 0;
}

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/*
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 * right after this call apic->write/read doesn't do anything
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 * note that there is no restore operation it works one way
 */
void apic_disable(void)
{
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	apic->read = native_apic_read_dummy;
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	apic->write = native_apic_write_dummy;
}

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void native_apic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 native_safe_apic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void native_apic_icr_write(u32 low, u32 id)
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{
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
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	apic_write(APIC_ICR, low);
}

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u64 native_apic_icr_read(void)
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{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

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	return icr1 | ((u64)icr2 << 32);
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}

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/**
 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
 */
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void __cpuinit enable_NMI_through_LVT0(void)
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{
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	unsigned int v;
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	/* unmask and set to NMI */
	v = APIC_DM_NMI;
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	/* Level triggered for 82489DX (32bit mode) */
	if (!lapic_is_integrated())
		v |= APIC_LVT_LEVEL_TRIGGER;

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	apic_write(APIC_LVT0, v);
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}

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#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
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int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
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	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#define APIC_DIVISOR 16
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
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	apic_write(APIC_LVTT, lvtt_value);
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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
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 * Setup extended LVT, AMD specific (K8, family 10h)
 *
 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
 * MCE interrupts are supported. Thus MCE offset must be set to 0.
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 *
 * If mask=1, the LVT entry does not generate interrupts while mask=0
 * enables the vector. See also the BKDGs.
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 */
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#define APIC_EILVT_LVTOFF_MCE 0
#define APIC_EILVT_LVTOFF_IBS 1

static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
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{
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	unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
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	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
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	apic_write(reg, v);
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}

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u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_MCE;
}

u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_IBS;
}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
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{
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	apic_write(APIC_TMICT, delta);
	return 0;
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}

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/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
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{
	unsigned long flags;
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return;

	local_irq_save(flags);

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	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		__setup_APIC_LVTT(calibration_result,
				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, v);
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		apic_write(APIC_TMICT, 0xffffffff);
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		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
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	local_irq_restore(flags);
}

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/*
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 * Local APIC timer broadcast function
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 */
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static void lapic_timer_broadcast(const struct cpumask *mask)
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{
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#ifdef CONFIG_SMP
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	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
}
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/*
 * Setup the local APIC timer for this CPU. Copy the initilized values
 * of the boot CPU and register the clock event in the framework.
 */
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static void __cpuinit setup_APIC_timer(void)
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{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
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	if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)) {
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

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	memcpy(levt, &lapic_clockevent, sizeof(*levt));
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	levt->cpumask = cpumask_of(smp_processor_id());
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	clockevents_register_device(levt);
}
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/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

	if (cpu_has_tsc)
		rdtscll(tsc);

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

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static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
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{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

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	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
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	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
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		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
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		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
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		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
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	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
	if (cpu_has_tsc) {
		res = (((u64)(*deltatsc)) * pm_100ms);
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		do_div(res, deltapm);
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		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
					  "PM-Timer: %lu (%ld) \n",
					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
606 607 608 609 610
	}

	return 0;
}

611 612 613 614 615
static int __init calibrate_APIC_clock(void)
{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
616
	long delta, deltatsc;
617 618 619 620 621 622 623 624 625
	int pm_referenced = 0;

	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
626
	 * Setup the APIC counter to maximum. There is no way the lapic
627 628
	 * can underflow in the 100ms detection time frame
	 */
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Cyrill Gorcunov 已提交
629
	__setup_APIC_LVTT(0xffffffff, 0, 0);
630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

646 647
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

648 649
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
650
					&delta, &deltatsc);
651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
		clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

	calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
	apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
		    calibration_result);

	if (cpu_has_tsc) {
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
670 671
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
672 673 674 675 676 677 678 679 680 681 682 683
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
		    calibration_result / (1000000 / HZ),
		    calibration_result % (1000000 / HZ));

	/*
	 * Do a sanity check on the APIC calibration result
	 */
	if (calibration_result < (1000000 / HZ)) {
		local_irq_enable();
684
		pr_warning("APIC frequency too slow, disabling apic timer\n");
685 686 687 688 689
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

690 691 692 693
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
	} else
		local_irq_enable();

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
726
		pr_warning("APIC timer disabled due to verification failure\n");
727 728 729 730 731 732
			return -1;
	}

	return 0;
}

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Hiroshi Shimamoto 已提交
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/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
738 739 740
void __init setup_boot_APIC_clock(void)
{
	/*
741 742 743 744
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
745 746
	 */
	if (disable_apic_timer) {
747
		pr_info("Disabling APIC timer\n");
748
		/* No broadcast on UP ! */
749 750
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
751
			setup_APIC_timer();
752
		}
753 754 755
		return;
	}

756 757 758
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

759
	if (calibrate_APIC_clock()) {
760 761 762 763 764 765
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

766 767 768 769 770 771 772 773
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
	if (nmi_watchdog != NMI_IO_APIC)
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
	else
774
		pr_warning("APIC timer registered as dummy,"
775
			" due to nmi_watchdog=%d!\n", nmi_watchdog);
776

777
	/* Setup the lapic or request the broadcast */
778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
	setup_APIC_timer();
}

void __cpuinit setup_secondary_APIC_clock(void)
{
	setup_APIC_timer();
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
806
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
807 808 809 810 811 812 813 814
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
815
	inc_irq_stat(apic_timer_irqs);
816 817 818 819 820 821 822 823 824 825 826 827

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
828
void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 */
	ack_APIC_irq();
	/*
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
	exit_idle();
	irq_enter();
	local_apic_timer_interrupt();
	irq_exit();
846

847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
868
	int maxlvt;
869 870
	u32 v;

871
	/* APIC hasn't been mapped yet */
872
	if (!x2apic_mode && !apic_phys)
873 874 875
		return;

	maxlvt = lapic_get_maxlvt();
876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

899
	/* lets not touch this if we didn't frob it */
900
#ifdef CONFIG_X86_THERMAL_VECTOR
901 902 903 904 905
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
906 907 908 909 910 911 912 913
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

914 915 916 917 918 919 920 921 922 923
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
924 925 926 927 928 929 930 931

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
932 933 934 935 936 937 938 939 940
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

941 942 943 944
	/* APIC hasn't been mapped yet */
	if (!apic_phys)
		return;

945 946 947 948 949 950 951 952 953
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
954 955 956 957 958 959 960 961 962 963 964 965 966 967

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
968 969
}

970 971 972 973 974 975
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
976 977 978 979 980 981 982 983 984
void lapic_shutdown(void)
{
	unsigned long flags;

	if (!cpu_has_apic)
		return;

	local_irq_save(flags);

985 986 987 988 989 990 991
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034

	local_irq_restore(flags);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = lapic_get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
1035
	reg0 = apic_read(APIC_ID);
1036
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1037
	apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1038
	reg1 = apic_read(APIC_ID);
1039 1040
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
1041
	if (reg1 != (reg0 ^ apic->apic_id_mask))
1042 1043 1044
		return 0;

	/*
L
Linus Torvalds 已提交
1045 1046 1047 1048 1049
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
1050
	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
L
Linus Torvalds 已提交
1051 1052 1053 1054 1055 1056
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

1057 1058 1059
/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
1060 1061
void __init sync_Arb_IDs(void)
{
C
Cyrill Gorcunov 已提交
1062 1063 1064 1065 1066
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
Linus Torvalds 已提交
1067 1068 1069 1070 1071 1072 1073 1074
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1075 1076
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
L
Linus Torvalds 已提交
1077 1078 1079 1080 1081 1082 1083
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1084
	unsigned int value;
L
Linus Torvalds 已提交
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1104 1105 1106 1107 1108 1109 1110 1111 1112

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
L
Linus Torvalds 已提交
1113
	value |= SPURIOUS_APIC_VECTOR;
1114
	apic_write(APIC_SPIV, value);
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Linus Torvalds 已提交
1115 1116 1117 1118

	/*
	 * Set up the virtual wire mode.
	 */
1119
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1120
	value = APIC_DM_NMI;
1121 1122
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1123
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1124 1125
}

1126 1127
static void __cpuinit lapic_setup_esr(void)
{
1128 1129 1130
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1131
		pr_info("No ESR for 82489DX.\n");
1132 1133
		return;
	}
1134

1135
	if (apic->disable_esr) {
1136
		/*
1137 1138 1139 1140
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1141
		 */
1142
		pr_info("Leaving ESR disabled.\n");
1143
		return;
1144
	}
1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1165 1166 1167
}


1168 1169 1170 1171
/**
 * setup_local_APIC - setup the local APIC
 */
void __cpuinit setup_local_APIC(void)
L
Linus Torvalds 已提交
1172
{
1173
	unsigned int value;
1174
	int i, j;
L
Linus Torvalds 已提交
1175

J
Jan Beulich 已提交
1176
	if (disable_apic) {
1177
		arch_disable_smp_support();
J
Jan Beulich 已提交
1178 1179 1180
		return;
	}

1181 1182
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1183
	if (lapic_is_integrated() && apic->disable_esr) {
1184 1185 1186 1187 1188 1189
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1190
	perf_counters_lapic_init();
1191

J
Jack Steiner 已提交
1192
	preempt_disable();
L
Linus Torvalds 已提交
1193 1194 1195 1196 1197

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1198
	if (!apic->apic_id_registered())
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Linus Torvalds 已提交
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		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1206
	apic->init_apic_ldr();
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Linus Torvalds 已提交
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	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1214
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
1215

1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

L
Linus Torvalds 已提交
1235 1236 1237 1238 1239 1240 1241 1242 1243 1244
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 * See also the comment in end_level_ioapic_irq().  --macro
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1273

L
Linus Torvalds 已提交
1274 1275 1276 1277
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1278
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1291
	if (!smp_processor_id() && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1292
		value = APIC_DM_EXTINT;
1293
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1294
				smp_processor_id());
L
Linus Torvalds 已提交
1295 1296
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1297
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1298
				smp_processor_id());
L
Linus Torvalds 已提交
1299
	}
1300
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1301 1302 1303 1304 1305 1306 1307 1308

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1309 1310
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1311
	apic_write(APIC_LVT1, value);
1312

J
Jack Steiner 已提交
1313
	preempt_enable();
1314 1315 1316 1317 1318 1319

#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
	if (smp_processor_id() == 0)
		cmci_recheck();
#endif
1320
}
L
Linus Torvalds 已提交
1321

1322 1323 1324
void __cpuinit end_local_APIC_setup(void)
{
	lapic_setup_esr();
1325 1326

#ifdef CONFIG_X86_32
1327 1328 1329 1330 1331 1332 1333
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1334 1335
#endif

1336
	setup_apic_nmi_watchdog(NULL);
1337
	apic_pm_activate();
L
Linus Torvalds 已提交
1338 1339
}

Y
Yinghai Lu 已提交
1340
#ifdef CONFIG_X86_X2APIC
1341 1342
void check_x2apic(void)
{
1343
	if (x2apic_enabled()) {
1344
		pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1345
		x2apic_preenabled = x2apic_mode = 1;
1346 1347 1348 1349 1350 1351 1352
	}
}

void enable_x2apic(void)
{
	int msr, msr2;

1353
	if (!x2apic_mode)
Y
Yinghai Lu 已提交
1354 1355
		return;

1356 1357
	rdmsr(MSR_IA32_APICBASE, msr, msr2);
	if (!(msr & X2APIC_ENABLE)) {
1358
		pr_info("Enabling x2apic\n");
1359 1360 1361
		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
	}
}
1362
#endif /* CONFIG_X86_X2APIC */
1363

A
Al Viro 已提交
1364
void __init enable_IR_x2apic(void)
1365 1366 1367 1368
{
#ifdef CONFIG_INTR_REMAP
	int ret;
	unsigned long flags;
1369
	struct IO_APIC_route_entry **ioapic_entries = NULL;
1370

1371 1372 1373 1374
	ret = dmar_table_init();
	if (ret) {
		pr_debug("dmar_table_init() failed with %d:\n", ret);
		goto ir_failed;
1375 1376
	}

1377 1378 1379
	if (!intr_remapping_supported()) {
		pr_debug("intr-remapping not supported\n");
		goto ir_failed;
1380 1381 1382
	}


1383 1384 1385
	if (!x2apic_preenabled && skip_ioapic_setup) {
		pr_info("Skipped enabling intr-remap because of skipping "
			"io-apic setup\n");
1386 1387 1388
		return;
	}

1389 1390 1391 1392 1393 1394 1395
	ioapic_entries = alloc_ioapic_entries();
	if (!ioapic_entries) {
		pr_info("Allocate ioapic_entries failed: %d\n", ret);
		goto end;
	}

	ret = save_IO_APIC_setup(ioapic_entries);
1396
	if (ret) {
1397
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1398 1399
		goto end;
	}
1400

1401
	local_irq_save(flags);
1402
	mask_IO_APIC_setup(ioapic_entries);
1403 1404
	mask_8259A();

1405
	ret = enable_intr_remapping(x2apic_supported());
1406
	if (ret)
1407
		goto end_restore;
1408

1409 1410
	pr_info("Enabled Interrupt-remapping\n");

1411 1412
	if (x2apic_supported() && !x2apic_mode) {
		x2apic_mode = 1;
1413
		enable_x2apic();
1414
		pr_info("Enabled x2apic\n");
1415
	}
1416 1417

end_restore:
1418 1419 1420 1421
	if (ret)
		/*
		 * IR enabling failed
		 */
1422
		restore_IO_APIC_setup(ioapic_entries);
1423 1424 1425 1426

	unmask_8259A();
	local_irq_restore(flags);

1427
end:
1428 1429
	if (ioapic_entries)
		free_ioapic_entries(ioapic_entries);
1430 1431 1432 1433 1434 1435 1436 1437 1438

	if (!ret)
		return;

ir_failed:
	if (x2apic_preenabled)
		panic("x2apic enabled by bios. But IR enabling failed");
	else if (cpu_has_x2apic)
		pr_info("Not enabling x2apic,Intr-remapping\n");
1439 1440 1441 1442 1443 1444
#else
	if (!cpu_has_x2apic)
		return;

	if (x2apic_preenabled)
		panic("x2apic enabled prior OS handover,"
1445
		      " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
1446 1447 1448 1449
#endif

	return;
}
1450

1451

1452
#ifdef CONFIG_X86_64
L
Linus Torvalds 已提交
1453 1454 1455 1456
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1457
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1458
 */
1459
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1460 1461
{
	if (!cpu_has_apic) {
1462
		pr_info("No local APIC present\n");
L
Linus Torvalds 已提交
1463 1464 1465 1466 1467 1468
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
#else
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	u32 h, l, features;

	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1484
		    (boot_cpu_data.x86 >= 15))
1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

	if (!cpu_has_apic) {
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1502 1503
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1504 1505 1506 1507 1508 1509 1510 1511 1512
			return -1;
		}
		/*
		 * Some BIOSes disable the local APIC in the APIC_BASE
		 * MSR. This can only be done in software for Intel P6 or later
		 * and AMD K7 (Model > 1) or later.
		 */
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1513
			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
	}
	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
1526
		pr_warning("Could not enable APIC!\n");
1527 1528 1529 1530 1531 1532 1533 1534 1535 1536
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
	rdmsr(MSR_IA32_APICBASE, l, h);
	if (l & MSR_IA32_APICBASE_ENABLE)
		mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;

1537
	pr_info("Found and enabled local APIC!\n");
1538 1539 1540 1541 1542 1543

	apic_pm_activate();

	return 0;

no_apic:
1544
	pr_info("No local APIC present or hardware disabled\n");
1545 1546 1547
	return -1;
}
#endif
L
Linus Torvalds 已提交
1548

Y
Yinghai Lu 已提交
1549
#ifdef CONFIG_X86_64
1550 1551
void __init early_init_lapic_mapping(void)
{
1552
	unsigned long phys_addr;
1553 1554 1555 1556 1557 1558 1559 1560

	/*
	 * If no local APIC can be found then go out
	 * : it means there is no mpatable and MADT
	 */
	if (!smp_found_config)
		return;

1561
	phys_addr = mp_lapic_addr;
1562

1563
	set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1564
	apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1565
		    APIC_BASE, phys_addr);
1566 1567 1568 1569 1570

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1571
	boot_cpu_physical_apicid = read_apic_id();
1572
}
Y
Yinghai Lu 已提交
1573
#endif
1574

1575 1576 1577
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
1578 1579
void __init init_apic_mappings(void)
{
1580 1581
	unsigned int new_apicid;

1582
	if (x2apic_mode) {
1583
		boot_cpu_physical_apicid = read_apic_id();
1584 1585 1586
		return;
	}

1587
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1588
	if (!smp_found_config && detect_init_APIC()) {
1589 1590 1591 1592
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1593 1594
		apic_phys = mp_lapic_addr;

1595 1596 1597 1598 1599 1600
		/*
		 * acpi lapic path already maps that address in
		 * acpi_register_lapic_address()
		 */
		if (!acpi_lapic)
			set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1601

1602 1603
		apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
					APIC_BASE, apic_phys);
1604
	}
L
Linus Torvalds 已提交
1605 1606 1607 1608 1609

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1610 1611 1612
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1613 1614 1615 1616 1617 1618 1619
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1620 1621
		apic_version[new_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
1622
	}
L
Linus Torvalds 已提交
1623 1624 1625
}

/*
1626 1627
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
L
Linus Torvalds 已提交
1628
 */
1629 1630
int apic_version[MAX_APICS];

1631
int __init APIC_init_uniprocessor(void)
L
Linus Torvalds 已提交
1632
{
1633
	if (disable_apic) {
1634
		pr_info("Apic disabled\n");
1635 1636
		return -1;
	}
J
Jan Beulich 已提交
1637
#ifdef CONFIG_X86_64
1638 1639
	if (!cpu_has_apic) {
		disable_apic = 1;
1640
		pr_info("Apic disabled by BIOS\n");
1641 1642
		return -1;
	}
Y
Yinghai Lu 已提交
1643 1644 1645 1646 1647 1648 1649 1650 1651
#else
	if (!smp_found_config && !cpu_has_apic)
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
	if (!cpu_has_apic &&
	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1652 1653
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
Y
Yinghai Lu 已提交
1654 1655 1656 1657
		return -1;
	}
#endif

1658
	enable_IR_x2apic();
Y
Yinghai Lu 已提交
1659
#ifdef CONFIG_X86_64
1660
	default_setup_apic_routing();
Y
Yinghai Lu 已提交
1661
#endif
1662

1663
	verify_local_APIC();
1664 1665
	connect_bsp_APIC();

Y
Yinghai Lu 已提交
1666
#ifdef CONFIG_X86_64
1667
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Y
Yinghai Lu 已提交
1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678
#else
	/*
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
	 */
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1679
	setup_local_APIC();
L
Linus Torvalds 已提交
1680

1681
#ifdef CONFIG_X86_IO_APIC
1682 1683
	/*
	 * Now enable IO-APICs, actually call clear_IO_APIC
1684
	 * We need clear_IO_APIC before enabling error vector
1685 1686 1687
	 */
	if (!skip_ioapic_setup && nr_ioapics)
		enable_IO_APIC();
Y
Yinghai Lu 已提交
1688
#endif
1689 1690 1691

	end_local_APIC_setup();

Y
Yinghai Lu 已提交
1692
#ifdef CONFIG_X86_IO_APIC
1693 1694
	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
		setup_IO_APIC();
1695
	else {
1696
		nr_ioapics = 0;
1697 1698 1699 1700
		localise_nmi_watchdog();
	}
#else
	localise_nmi_watchdog();
Y
Yinghai Lu 已提交
1701 1702
#endif

1703
	setup_boot_clock();
Y
Yinghai Lu 已提交
1704
#ifdef CONFIG_X86_64
1705
	check_nmi_watchdog();
Y
Yinghai Lu 已提交
1706 1707
#endif

1708
	return 0;
L
Linus Torvalds 已提交
1709 1710 1711
}

/*
1712
 * Local APIC interrupts
L
Linus Torvalds 已提交
1713 1714
 */

1715 1716 1717
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1718
void smp_spurious_interrupt(struct pt_regs *regs)
L
Linus Torvalds 已提交
1719
{
1720 1721
	u32 v;

1722 1723
	exit_idle();
	irq_enter();
L
Linus Torvalds 已提交
1724
	/*
1725 1726 1727
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1728
	 */
1729 1730 1731
	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
		ack_APIC_irq();
1732

1733 1734
	inc_irq_stat(irq_spurious_count);

1735
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1736 1737
	pr_info("spurious APIC interrupt on CPU#%d, "
		"should never happen.\n", smp_processor_id());
1738 1739
	irq_exit();
}
L
Linus Torvalds 已提交
1740

1741 1742 1743
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1744
void smp_error_interrupt(struct pt_regs *regs)
1745
{
1746
	u32 v, v1;
L
Linus Torvalds 已提交
1747

1748 1749 1750 1751 1752 1753 1754 1755
	exit_idle();
	irq_enter();
	/* First tickle the hardware, only then report what went on. -- REW */
	v = apic_read(APIC_ESR);
	apic_write(APIC_ESR, 0);
	v1 = apic_read(APIC_ESR);
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
1756

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768
	/*
	 * Here is what the APIC error bits mean:
	 * 0: Send CS error
	 * 1: Receive CS error
	 * 2: Send accept error
	 * 3: Receive accept error
	 * 4: Reserved
	 * 5: Send illegal vector
	 * 6: Received illegal vector
	 * 7: Illegal register address
	 */
	pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1769 1770
		smp_processor_id(), v , v1);
	irq_exit();
L
Linus Torvalds 已提交
1771 1772
}

1773
/**
1774 1775
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
1776 1777
void __init connect_bsp_APIC(void)
{
1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
1790
		imcr_pic_to_apic();
1791 1792
	}
#endif
1793 1794
	if (apic->enable_apic_mode)
		apic->enable_apic_mode();
1795 1796
}

1797 1798 1799 1800 1801 1802 1803
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
1804
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1805
{
1806 1807
	unsigned int value;

1808 1809 1810 1811 1812 1813 1814 1815 1816 1817
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
1818
		imcr_apic_to_pic();
1819 1820 1821 1822
		return;
	}
#endif

1823
	/* Go back to Virtual Wire compatibility mode */
L
Linus Torvalds 已提交
1824

1825 1826 1827 1828 1829 1830
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
1831

1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
1848

1849 1850 1851 1852
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
1853 1854 1855 1856 1857 1858 1859
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1860 1861
}

1862 1863 1864 1865
void __cpuinit generic_processor_info(int apicid, int version)
{
	int cpu;

1866 1867 1868 1869
	/*
	 * Validate version
	 */
	if (version == 0x0) {
1870
		pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1871 1872
			   "fixing up to 0x10. (tell your hw vendor)\n",
				version);
1873
		version = 0x10;
1874
	}
1875
	apic_version[apicid] = version;
1876

1877 1878 1879 1880 1881 1882 1883 1884 1885
	if (num_processors >= nr_cpu_ids) {
		int max = nr_cpu_ids;
		int thiscpu = max + disabled_cpus;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i reached."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
1886 1887 1888 1889
		return;
	}

	num_processors++;
1890
	cpu = cpumask_next_zero(-1, cpu_present_mask);
1891

1892 1893 1894 1895 1896
	if (version != apic_version[boot_cpu_physical_apicid])
		WARN_ONCE(1,
			"ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
			apic_version[boot_cpu_physical_apicid], cpu, version);

1897 1898 1899 1900 1901 1902 1903 1904 1905
	physid_set(apicid, phys_cpu_present_map);
	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
		 */
		cpu = 0;
	}
1906 1907 1908
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
#ifdef CONFIG_X86_32
	/*
	 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
	 * but we need to work other dependencies like SMP_SUSPEND etc
	 * before this can be done without some confusion.
	 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
	 *       - Ashok Raj <ashok.raj@intel.com>
	 */
	if (max_physical_apicid >= 8) {
		switch (boot_cpu_data.x86_vendor) {
		case X86_VENDOR_INTEL:
			if (!APIC_XAPIC(version)) {
				def_to_bigsmp = 0;
				break;
			}
			/* If P4 and above fall through */
		case X86_VENDOR_AMD:
			def_to_bigsmp = 1;
		}
	}
#endif

1931
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1932 1933
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1934
#endif
1935

1936 1937
	set_cpu_possible(cpu, true);
	set_cpu_present(cpu, true);
1938 1939
}

1940 1941 1942 1943
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

#ifdef CONFIG_X86_32
int default_apicid_to_node(int logical_apicid)
{
#ifdef CONFIG_SMP
	return apicid_2_node[hard_smp_processor_id()];
#else
	return 0;
#endif
}
1964
#endif
1965

1966
/*
1967
 * Power management
1968
 */
1969 1970 1971
#ifdef CONFIG_PM

static struct {
1972 1973 1974 1975 1976
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;
1998

1999 2000
	if (!apic_pm_state.active)
		return 0;
2001

2002
	maxlvt = lapic_get_maxlvt();
2003

2004
	apic_pm_state.apic_id = apic_read(APIC_ID);
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2017
#ifdef CONFIG_X86_THERMAL_VECTOR
2018 2019 2020
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
2021

2022 2023
	local_irq_save(flags);
	disable_local_APIC();
2024

2025 2026
	if (intr_remapping_enabled)
		disable_intr_remapping();
2027

2028 2029
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
2030 2031
}

2032
static int lapic_resume(struct sys_device *dev)
L
Linus Torvalds 已提交
2033
{
2034 2035 2036
	unsigned int l, h;
	unsigned long flags;
	int maxlvt;
2037
	int ret = 0;
2038 2039
	struct IO_APIC_route_entry **ioapic_entries = NULL;

2040 2041
	if (!apic_pm_state.active)
		return 0;
2042

2043
	local_irq_save(flags);
2044
	if (intr_remapping_enabled) {
2045 2046 2047
		ioapic_entries = alloc_ioapic_entries();
		if (!ioapic_entries) {
			WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2048 2049
			ret = -ENOMEM;
			goto restore;
2050 2051 2052 2053 2054 2055
		}

		ret = save_IO_APIC_setup(ioapic_entries);
		if (ret) {
			WARN(1, "Saving IO-APIC state failed: %d\n", ret);
			free_ioapic_entries(ioapic_entries);
2056
			goto restore;
2057 2058 2059 2060 2061
		}

		mask_IO_APIC_setup(ioapic_entries);
		mask_8259A();
	}
C
Cyrill Gorcunov 已提交
2062

2063
	if (x2apic_mode)
C
Cyrill Gorcunov 已提交
2064
		enable_x2apic();
2065
	else {
C
Cyrill Gorcunov 已提交
2066 2067 2068 2069 2070 2071
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2072 2073 2074 2075
		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_BASE;
		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
		wrmsr(MSR_IA32_APICBASE, l, h);
2076
	}
2077

2078
	maxlvt = lapic_get_maxlvt();
2079 2080 2081 2082 2083 2084 2085 2086
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
C
Cyrill Gorcunov 已提交
2087
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
C
Cyrill Gorcunov 已提交
2101

2102
	if (intr_remapping_enabled) {
2103
		reenable_intr_remapping(x2apic_mode);
2104 2105 2106 2107
		unmask_8259A();
		restore_IO_APIC_setup(ioapic_entries);
		free_ioapic_entries(ioapic_entries);
	}
2108
restore:
2109
	local_irq_restore(flags);
C
Cyrill Gorcunov 已提交
2110

2111
	return ret;
2112
}
T
Thomas Gleixner 已提交
2113

2114 2115 2116 2117 2118
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2119 2120 2121 2122 2123
static struct sysdev_class lapic_sysclass = {
	.name		= "lapic",
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
2124

2125
static struct sys_device device_lapic = {
H
Hiroshi Shimamoto 已提交
2126 2127
	.id	= 0,
	.cls	= &lapic_sysclass,
2128
};
T
Thomas Gleixner 已提交
2129

2130 2131 2132
static void __cpuinit apic_pm_activate(void)
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
2133 2134
}

2135
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
2136
{
2137
	int error;
H
Hiroshi Shimamoto 已提交
2138

2139 2140 2141
	if (!cpu_has_apic)
		return 0;
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
H
Hiroshi Shimamoto 已提交
2142

2143 2144 2145 2146
	error = sysdev_class_register(&lapic_sysclass);
	if (!error)
		error = sysdev_register(&device_lapic);
	return error;
L
Linus Torvalds 已提交
2147
}
2148 2149 2150

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2151 2152 2153 2154 2155 2156

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
2157

Y
Yinghai Lu 已提交
2158
#ifdef CONFIG_X86_64
2159 2160

static int __cpuinit apic_cluster_num(void)
L
Linus Torvalds 已提交
2161 2162 2163
{
	int i, clusters, zeros;
	unsigned id;
2164
	u16 *bios_cpu_apicid;
L
Linus Torvalds 已提交
2165 2166
	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);

2167
	bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2168
	bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
L
Linus Torvalds 已提交
2169

2170
	for (i = 0; i < nr_cpu_ids; i++) {
2171
		/* are we being called early in kernel startup? */
2172 2173
		if (bios_cpu_apicid) {
			id = bios_cpu_apicid[i];
2174
		} else if (i < nr_cpu_ids) {
2175 2176 2177 2178
			if (cpu_present(i))
				id = per_cpu(x86_bios_cpu_apicid, i);
			else
				continue;
2179
		} else
2180 2181
			break;

L
Linus Torvalds 已提交
2182 2183 2184 2185 2186 2187
		if (id != BAD_APICID)
			__set_bit(APIC_CLUSTERID(id), clustermap);
	}

	/* Problem:  Partially populated chassis may not have CPUs in some of
	 * the APIC clusters they have been allocated.  Only present CPUs have
2188 2189 2190
	 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
	 * Since clusters are allocated sequentially, count zeros only if
	 * they are bounded by ones.
L
Linus Torvalds 已提交
2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201
	 */
	clusters = 0;
	zeros = 0;
	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
		if (test_bit(i, clustermap)) {
			clusters += 1 + zeros;
			zeros = 0;
		} else
			++zeros;
	}

2202 2203 2204 2205 2206 2207 2208 2209 2210 2211
	return clusters;
}

static int __cpuinitdata multi_checked;
static int __cpuinitdata multi;

static int __cpuinit set_multi(const struct dmi_system_id *d)
{
	if (multi)
		return 0;
C
Cyrill Gorcunov 已提交
2212
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
	multi = 1;
	return 0;
}

static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

static void __cpuinit dmi_check_multi(void)
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
__cpuinit int apic_is_clustered_box(void)
{
	dmi_check_multi();
	if (multi)
2250 2251
		return 1;

2252 2253 2254
	if (!is_vsmp_box())
		return 0;

L
Linus Torvalds 已提交
2255
	/*
2256 2257
	 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
	 * not guaranteed to be synced between boards
L
Linus Torvalds 已提交
2258
	 */
2259 2260 2261 2262
	if (apic_cluster_num() > 1)
		return 1;

	return 0;
L
Linus Torvalds 已提交
2263
}
Y
Yinghai Lu 已提交
2264
#endif
L
Linus Torvalds 已提交
2265 2266

/*
2267
 * APIC command line parameters
L
Linus Torvalds 已提交
2268
 */
2269
static int __init setup_disableapic(char *arg)
2270
{
L
Linus Torvalds 已提交
2271
	disable_apic = 1;
2272
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2273 2274 2275
	return 0;
}
early_param("disableapic", setup_disableapic);
L
Linus Torvalds 已提交
2276

2277
/* same as disableapic, for compatibility */
2278
static int __init setup_nolapic(char *arg)
2279
{
2280
	return setup_disableapic(arg);
2281
}
2282
early_param("nolapic", setup_nolapic);
L
Linus Torvalds 已提交
2283

2284 2285 2286 2287 2288 2289 2290
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2291
static int __init parse_disable_apic_timer(char *arg)
2292
{
L
Linus Torvalds 已提交
2293
	disable_apic_timer = 1;
2294
	return 0;
2295
}
2296 2297 2298 2299 2300 2301
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2302
}
2303
early_param("nolapic_timer", parse_nolapic_timer);
2304

2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2320
		pr_warning("APIC Verbosity level %s not recognised"
2321 2322 2323 2324 2325 2326 2327 2328
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);