apic.c 54.1 KB
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/*
 *	Local APIC handling, local APIC timers
 *
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 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

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#include <linux/perf_event.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/timex.h>
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#include <linux/dmar.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
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#include <linux/nmi.h>
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#include <linux/smp.h>
#include <linux/mm.h>
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#include <asm/perf_event.h>
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
#include <asm/atomic.h>
#include <asm/mpspec.h>
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#include <asm/i8253.h>
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/idle.h>
#include <asm/mtrr.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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#include <asm/kvm_para.h>
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unsigned int num_processors;
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unsigned disabled_cpus __cpuinitdata;
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/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
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/*
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 * The highest APIC ID seen during enumeration.
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 */
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unsigned int max_physical_apicid;
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/*
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 * Bitmask of physically existing CPUs:
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 */
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physid_mask_t phys_cpu_present_map;

/*
 * Map cpu index to physical APIC ID
 */
DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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#ifdef CONFIG_X86_32
/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
static int force_enable_local_apic;
/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
	force_enable_local_apic = 1;
	return 0;
}
early_param("lapic", parse_lapic);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
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static inline void imcr_pic_to_apic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

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static inline void imcr_apic_to_pic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
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#endif

#ifdef CONFIG_X86_64
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static int apic_calibrate_pmtmr __initdata;
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static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

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int x2apic_mode;
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#ifdef CONFIG_X86_X2APIC
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/* x2apic enabled before OS handover */
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static int x2apic_preenabled;
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static __init int setup_nox2apic(char *str)
{
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	if (x2apic_enabled()) {
		pr_warning("Bios already enabled x2apic, "
			   "can't enforce nox2apic");
		return 0;
	}

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	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
	return 0;
}
early_param("nox2apic", setup_nox2apic);
#endif
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unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
static int disable_apic_timer __cpuinitdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

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int first_system_vector = 0xfe;

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/*
 * Debug level, exported for io_apic.c
 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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static unsigned int calibration_result;

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static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt);
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt);
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static void lapic_timer_broadcast(const struct cpumask *mask);
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static void apic_pm_activate(void);
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
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static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
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	return 1;
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#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
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}

/*
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 * Check, whether this is a modern or a first generation APIC
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 */
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static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
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 * right after this call apic become NOOP driven
 * so apic->write/read doesn't do anything
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 */
void apic_disable(void)
{
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	pr_info("APIC: switched to apic NOOP\n");
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	apic = &apic_noop;
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}

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void native_apic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 native_safe_apic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void native_apic_icr_write(u32 low, u32 id)
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{
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
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	apic_write(APIC_ICR, low);
}

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u64 native_apic_icr_read(void)
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{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

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	return icr1 | ((u64)icr2 << 32);
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}

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/**
 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
 */
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void __cpuinit enable_NMI_through_LVT0(void)
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{
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	unsigned int v;
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	/* unmask and set to NMI */
	v = APIC_DM_NMI;
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	/* Level triggered for 82489DX (32bit mode) */
	if (!lapic_is_integrated())
		v |= APIC_LVT_LEVEL_TRIGGER;

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	apic_write(APIC_LVT0, v);
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}

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#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
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int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
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	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#define APIC_DIVISOR 16
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
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	apic_write(APIC_LVTT, lvtt_value);
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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
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 * Setup extended LVT, AMD specific (K8, family 10h)
 *
 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
 * MCE interrupts are supported. Thus MCE offset must be set to 0.
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 *
 * If mask=1, the LVT entry does not generate interrupts while mask=0
 * enables the vector. See also the BKDGs.
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 */
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#define APIC_EILVT_LVTOFF_MCE 0
#define APIC_EILVT_LVTOFF_IBS 1

static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
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{
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	unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
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	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
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	apic_write(reg, v);
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}

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u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_MCE;
}

u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_IBS;
}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
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{
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	apic_write(APIC_TMICT, delta);
	return 0;
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}

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/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
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{
	unsigned long flags;
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return;

	local_irq_save(flags);

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	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		__setup_APIC_LVTT(calibration_result,
				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, v);
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		apic_write(APIC_TMICT, 0);
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		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
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	local_irq_restore(flags);
}

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/*
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 * Local APIC timer broadcast function
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 */
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static void lapic_timer_broadcast(const struct cpumask *mask)
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{
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#ifdef CONFIG_SMP
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	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
}
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/*
 * Setup the local APIC timer for this CPU. Copy the initilized values
 * of the boot CPU and register the clock event in the framework.
 */
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static void __cpuinit setup_APIC_timer(void)
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{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
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	if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)) {
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

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	memcpy(levt, &lapic_clockevent, sizeof(*levt));
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	levt->cpumask = cpumask_of(smp_processor_id());
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	clockevents_register_device(levt);
}
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/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

	if (cpu_has_tsc)
		rdtscll(tsc);

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

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static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
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{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

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	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
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	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
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		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
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		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
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		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
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	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
	if (cpu_has_tsc) {
		res = (((u64)(*deltatsc)) * pm_100ms);
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		do_div(res, deltapm);
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		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
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					  "PM-Timer: %lu (%ld)\n",
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					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
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	}

	return 0;
}

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static int __init calibrate_APIC_clock(void)
{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
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	long delta, deltatsc;
598 599 600 601 602 603 604 605 606
	int pm_referenced = 0;

	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
607
	 * Setup the APIC counter to maximum. There is no way the lapic
608 609
	 * can underflow in the 100ms detection time frame
	 */
C
Cyrill Gorcunov 已提交
610
	__setup_APIC_LVTT(0xffffffff, 0, 0);
611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

627 628
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

629 630
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
631
					&delta, &deltatsc);
632 633 634 635 636 637 638 639 640 641 642 643

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
		clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

	calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
644
	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
645 646 647 648 649 650
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
		    calibration_result);

	if (cpu_has_tsc) {
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
651 652
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
653 654 655 656 657 658 659 660 661 662 663 664
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
		    calibration_result / (1000000 / HZ),
		    calibration_result % (1000000 / HZ));

	/*
	 * Do a sanity check on the APIC calibration result
	 */
	if (calibration_result < (1000000 / HZ)) {
		local_irq_enable();
665
		pr_warning("APIC frequency too slow, disabling apic timer\n");
666 667 668 669 670
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

671 672 673 674
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
	} else
		local_irq_enable();

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
707
		pr_warning("APIC timer disabled due to verification failure\n");
708 709 710 711 712 713
			return -1;
	}

	return 0;
}

H
Hiroshi Shimamoto 已提交
714 715 716 717 718
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
719 720 721
void __init setup_boot_APIC_clock(void)
{
	/*
722 723 724 725
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
726 727
	 */
	if (disable_apic_timer) {
728
		pr_info("Disabling APIC timer\n");
729
		/* No broadcast on UP ! */
730 731
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
732
			setup_APIC_timer();
733
		}
734 735 736
		return;
	}

737 738 739
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

740
	if (calibrate_APIC_clock()) {
741 742 743 744 745 746
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

747 748 749 750 751 752 753 754
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
	if (nmi_watchdog != NMI_IO_APIC)
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
	else
755
		pr_warning("APIC timer registered as dummy,"
756
			" due to nmi_watchdog=%d!\n", nmi_watchdog);
757

758
	/* Setup the lapic or request the broadcast */
759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
	setup_APIC_timer();
}

void __cpuinit setup_secondary_APIC_clock(void)
{
	setup_APIC_timer();
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
787
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
788 789 790 791 792 793 794 795
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
796
	inc_irq_stat(apic_timer_irqs);
797 798 799 800 801 802 803 804 805 806 807 808

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
809
void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 */
	ack_APIC_irq();
	/*
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
	exit_idle();
	irq_enter();
	local_apic_timer_interrupt();
	irq_exit();
827

828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
849
	int maxlvt;
850 851
	u32 v;

852
	/* APIC hasn't been mapped yet */
853
	if (!x2apic_mode && !apic_phys)
854 855 856
		return;

	maxlvt = lapic_get_maxlvt();
857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

880
	/* lets not touch this if we didn't frob it */
881
#ifdef CONFIG_X86_THERMAL_VECTOR
882 883 884 885 886
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
887 888 889 890 891 892 893 894
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

895 896 897 898 899 900 901 902 903 904
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
905 906 907 908 909 910 911 912

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
913 914 915 916 917 918 919 920 921
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

922 923 924 925
	/* APIC hasn't been mapped yet */
	if (!apic_phys)
		return;

926 927 928 929 930 931 932 933 934
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
935 936 937 938 939 940 941 942 943 944 945 946 947 948

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
949 950
}

951 952 953 954 955 956
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
957 958 959 960
void lapic_shutdown(void)
{
	unsigned long flags;

961
	if (!cpu_has_apic && !apic_from_smp_config())
962 963 964 965
		return;

	local_irq_save(flags);

966 967 968 969 970 971 972
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015

	local_irq_restore(flags);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = lapic_get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
1016
	reg0 = apic_read(APIC_ID);
1017
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1018
	apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1019
	reg1 = apic_read(APIC_ID);
1020 1021
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
1022
	if (reg1 != (reg0 ^ apic->apic_id_mask))
1023 1024 1025
		return 0;

	/*
L
Linus Torvalds 已提交
1026 1027 1028 1029 1030
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
1031
	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
L
Linus Torvalds 已提交
1032 1033 1034 1035 1036 1037
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

1038 1039 1040
/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
1041 1042
void __init sync_Arb_IDs(void)
{
C
Cyrill Gorcunov 已提交
1043 1044 1045 1046 1047
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
Linus Torvalds 已提交
1048 1049 1050 1051 1052 1053 1054 1055
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1056 1057
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
L
Linus Torvalds 已提交
1058 1059 1060 1061 1062 1063 1064
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1065
	unsigned int value;
L
Linus Torvalds 已提交
1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1085 1086 1087 1088 1089 1090 1091 1092 1093

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
L
Linus Torvalds 已提交
1094
	value |= SPURIOUS_APIC_VECTOR;
1095
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1096 1097 1098 1099

	/*
	 * Set up the virtual wire mode.
	 */
1100
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1101
	value = APIC_DM_NMI;
1102 1103
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1104
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1105 1106
}

1107 1108
static void __cpuinit lapic_setup_esr(void)
{
1109 1110 1111
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1112
		pr_info("No ESR for 82489DX.\n");
1113 1114
		return;
	}
1115

1116
	if (apic->disable_esr) {
1117
		/*
1118 1119 1120 1121
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1122
		 */
1123
		pr_info("Leaving ESR disabled.\n");
1124
		return;
1125
	}
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1146 1147 1148
}


1149 1150 1151 1152
/**
 * setup_local_APIC - setup the local APIC
 */
void __cpuinit setup_local_APIC(void)
L
Linus Torvalds 已提交
1153
{
1154
	unsigned int value;
1155
	int i, j;
L
Linus Torvalds 已提交
1156

J
Jan Beulich 已提交
1157
	if (disable_apic) {
1158
		arch_disable_smp_support();
J
Jan Beulich 已提交
1159 1160 1161
		return;
	}

1162 1163
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1164
	if (lapic_is_integrated() && apic->disable_esr) {
1165 1166 1167 1168 1169 1170
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1171
	perf_events_lapic_init();
1172

J
Jack Steiner 已提交
1173
	preempt_disable();
L
Linus Torvalds 已提交
1174 1175 1176 1177 1178

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1179
	BUG_ON(!apic->apic_id_registered());
L
Linus Torvalds 已提交
1180 1181 1182 1183 1184 1185

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1186
	apic->init_apic_ldr();
L
Linus Torvalds 已提交
1187 1188 1189 1190 1191 1192 1193

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1194
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
1195

1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

L
Linus Torvalds 已提交
1215 1216 1217 1218 1219 1220 1221 1222 1223 1224
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 * See also the comment in end_level_ioapic_irq().  --macro
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1253

L
Linus Torvalds 已提交
1254 1255 1256 1257
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1258
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1271
	if (!smp_processor_id() && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1272
		value = APIC_DM_EXTINT;
1273
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1274
				smp_processor_id());
L
Linus Torvalds 已提交
1275 1276
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1277
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1278
				smp_processor_id());
L
Linus Torvalds 已提交
1279
	}
1280
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1281 1282 1283 1284 1285 1286 1287 1288

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1289 1290
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1291
	apic_write(APIC_LVT1, value);
1292

J
Jack Steiner 已提交
1293
	preempt_enable();
1294 1295 1296 1297 1298 1299

#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
	if (smp_processor_id() == 0)
		cmci_recheck();
#endif
1300
}
L
Linus Torvalds 已提交
1301

1302 1303 1304
void __cpuinit end_local_APIC_setup(void)
{
	lapic_setup_esr();
1305 1306

#ifdef CONFIG_X86_32
1307 1308 1309 1310 1311 1312 1313
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1314 1315
#endif

1316
	setup_apic_nmi_watchdog(NULL);
1317
	apic_pm_activate();
L
Linus Torvalds 已提交
1318 1319
}

Y
Yinghai Lu 已提交
1320
#ifdef CONFIG_X86_X2APIC
1321 1322
void check_x2apic(void)
{
1323
	if (x2apic_enabled()) {
1324
		pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1325
		x2apic_preenabled = x2apic_mode = 1;
1326 1327 1328 1329 1330 1331 1332
	}
}

void enable_x2apic(void)
{
	int msr, msr2;

1333
	if (!x2apic_mode)
Y
Yinghai Lu 已提交
1334 1335
		return;

1336 1337
	rdmsr(MSR_IA32_APICBASE, msr, msr2);
	if (!(msr & X2APIC_ENABLE)) {
1338
		printk_once(KERN_INFO "Enabling x2apic\n");
1339 1340 1341
		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
	}
}
1342
#endif /* CONFIG_X86_X2APIC */
1343

1344
int __init enable_IR(void)
1345 1346
{
#ifdef CONFIG_INTR_REMAP
1347 1348
	if (!intr_remapping_supported()) {
		pr_debug("intr-remapping not supported\n");
1349
		return 0;
1350 1351
	}

1352 1353 1354
	if (!x2apic_preenabled && skip_ioapic_setup) {
		pr_info("Skipped enabling intr-remap because of skipping "
			"io-apic setup\n");
1355
		return 0;
1356 1357
	}

1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
	if (enable_intr_remapping(x2apic_supported()))
		return 0;

	pr_info("Enabled Interrupt-remapping\n");

	return 1;

#endif
	return 0;
}

void __init enable_IR_x2apic(void)
{
	unsigned long flags;
	struct IO_APIC_route_entry **ioapic_entries = NULL;
	int ret, x2apic_enabled = 0;
Y
Yinghai Lu 已提交
1374
	int dmar_table_init_ret;
1375 1376

	dmar_table_init_ret = dmar_table_init();
Y
Yinghai Lu 已提交
1377 1378
	if (dmar_table_init_ret && !x2apic_supported())
		return;
1379

1380 1381
	ioapic_entries = alloc_ioapic_entries();
	if (!ioapic_entries) {
1382 1383
		pr_err("Allocate ioapic_entries failed\n");
		goto out;
1384 1385 1386
	}

	ret = save_IO_APIC_setup(ioapic_entries);
1387
	if (ret) {
1388
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1389
		goto out;
1390
	}
1391

1392
	local_irq_save(flags);
1393
	legacy_pic->mask_all();
1394
	mask_IO_APIC_setup(ioapic_entries);
1395

1396 1397 1398 1399 1400
	if (dmar_table_init_ret)
		ret = 0;
	else
		ret = enable_IR();

1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412
	if (!ret) {
		/* IR is required if there is APIC ID > 255 even when running
		 * under KVM
		 */
		if (max_physical_apicid > 255 || !kvm_para_available())
			goto nox2apic;
		/*
		 * without IR all CPUs can be addressed by IOAPIC/MSI
		 * only in physical mode
		 */
		x2apic_force_phys();
	}
1413

1414
	x2apic_enabled = 1;
1415

1416 1417
	if (x2apic_supported() && !x2apic_mode) {
		x2apic_mode = 1;
1418
		enable_x2apic();
1419
		pr_info("Enabled x2apic\n");
1420
	}
1421

1422 1423
nox2apic:
	if (!ret) /* IR enabling failed */
1424
		restore_IO_APIC_setup(ioapic_entries);
1425
	legacy_pic->restore_mask();
1426 1427
	local_irq_restore(flags);

1428
out:
1429 1430
	if (ioapic_entries)
		free_ioapic_entries(ioapic_entries);
1431

1432
	if (x2apic_enabled)
1433 1434 1435
		return;

	if (x2apic_preenabled)
1436
		panic("x2apic: enabled by BIOS but kernel init failed.");
1437
	else if (cpu_has_x2apic)
1438
		pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1439
}
1440

1441
#ifdef CONFIG_X86_64
L
Linus Torvalds 已提交
1442 1443 1444 1445
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1446
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1447
 */
1448
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1449 1450
{
	if (!cpu_has_apic) {
1451
		pr_info("No local APIC present\n");
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Linus Torvalds 已提交
1452 1453 1454 1455 1456 1457
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472
#else
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	u32 h, l, features;

	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1473
		    (boot_cpu_data.x86 >= 15))
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

	if (!cpu_has_apic) {
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1491 1492
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1493 1494 1495 1496 1497 1498 1499 1500 1501
			return -1;
		}
		/*
		 * Some BIOSes disable the local APIC in the APIC_BASE
		 * MSR. This can only be done in software for Intel P6 or later
		 * and AMD K7 (Model > 1) or later.
		 */
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1502
			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
	}
	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
1515
		pr_warning("Could not enable APIC!\n");
1516 1517 1518 1519 1520 1521 1522 1523 1524 1525
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
	rdmsr(MSR_IA32_APICBASE, l, h);
	if (l & MSR_IA32_APICBASE_ENABLE)
		mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;

1526
	pr_info("Found and enabled local APIC!\n");
1527 1528 1529 1530 1531 1532

	apic_pm_activate();

	return 0;

no_apic:
1533
	pr_info("No local APIC present or hardware disabled\n");
1534 1535 1536
	return -1;
}
#endif
L
Linus Torvalds 已提交
1537

Y
Yinghai Lu 已提交
1538
#ifdef CONFIG_X86_64
1539 1540 1541 1542 1543 1544 1545 1546 1547
void __init early_init_lapic_mapping(void)
{
	/*
	 * If no local APIC can be found then go out
	 * : it means there is no mpatable and MADT
	 */
	if (!smp_found_config)
		return;

1548
	set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1549
	apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1550
		    APIC_BASE, mp_lapic_addr);
1551 1552 1553 1554 1555

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1556
	boot_cpu_physical_apicid = read_apic_id();
1557
}
Y
Yinghai Lu 已提交
1558
#endif
1559

1560 1561 1562
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
1563 1564
void __init init_apic_mappings(void)
{
1565 1566
	unsigned int new_apicid;

1567
	if (x2apic_mode) {
1568
		boot_cpu_physical_apicid = read_apic_id();
1569 1570 1571
		return;
	}

1572
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1573
	if (!smp_found_config && detect_init_APIC()) {
1574 1575 1576 1577
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1578 1579
		apic_phys = mp_lapic_addr;

1580 1581 1582 1583 1584 1585
		/*
		 * acpi lapic path already maps that address in
		 * acpi_register_lapic_address()
		 */
		if (!acpi_lapic)
			set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1586

1587 1588
		apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
					APIC_BASE, apic_phys);
1589
	}
L
Linus Torvalds 已提交
1590 1591 1592 1593 1594

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1595 1596 1597
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1598 1599 1600 1601 1602 1603 1604
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1605 1606
		apic_version[new_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
1607
	}
L
Linus Torvalds 已提交
1608 1609 1610
}

/*
1611 1612
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
L
Linus Torvalds 已提交
1613
 */
1614 1615
int apic_version[MAX_APICS];

1616
int __init APIC_init_uniprocessor(void)
L
Linus Torvalds 已提交
1617
{
1618
	if (disable_apic) {
1619
		pr_info("Apic disabled\n");
1620 1621
		return -1;
	}
J
Jan Beulich 已提交
1622
#ifdef CONFIG_X86_64
1623 1624
	if (!cpu_has_apic) {
		disable_apic = 1;
1625
		pr_info("Apic disabled by BIOS\n");
1626 1627
		return -1;
	}
Y
Yinghai Lu 已提交
1628 1629 1630 1631 1632 1633 1634 1635 1636
#else
	if (!smp_found_config && !cpu_has_apic)
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
	if (!cpu_has_apic &&
	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1637 1638
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
Y
Yinghai Lu 已提交
1639 1640 1641 1642
		return -1;
	}
#endif

1643
#ifndef CONFIG_SMP
1644
	enable_IR_x2apic();
1645
	default_setup_apic_routing();
1646
#endif
1647

1648
	verify_local_APIC();
1649 1650
	connect_bsp_APIC();

Y
Yinghai Lu 已提交
1651
#ifdef CONFIG_X86_64
1652
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Y
Yinghai Lu 已提交
1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
#else
	/*
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
	 */
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1664
	setup_local_APIC();
L
Linus Torvalds 已提交
1665

1666
#ifdef CONFIG_X86_IO_APIC
1667 1668
	/*
	 * Now enable IO-APICs, actually call clear_IO_APIC
1669
	 * We need clear_IO_APIC before enabling error vector
1670 1671 1672
	 */
	if (!skip_ioapic_setup && nr_ioapics)
		enable_IO_APIC();
Y
Yinghai Lu 已提交
1673
#endif
1674 1675 1676

	end_local_APIC_setup();

Y
Yinghai Lu 已提交
1677
#ifdef CONFIG_X86_IO_APIC
1678 1679
	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
		setup_IO_APIC();
1680
	else {
1681
		nr_ioapics = 0;
1682 1683 1684 1685
		localise_nmi_watchdog();
	}
#else
	localise_nmi_watchdog();
Y
Yinghai Lu 已提交
1686 1687
#endif

1688
	x86_init.timers.setup_percpu_clockev();
Y
Yinghai Lu 已提交
1689
#ifdef CONFIG_X86_64
1690
	check_nmi_watchdog();
Y
Yinghai Lu 已提交
1691 1692
#endif

1693
	return 0;
L
Linus Torvalds 已提交
1694 1695 1696
}

/*
1697
 * Local APIC interrupts
L
Linus Torvalds 已提交
1698 1699
 */

1700 1701 1702
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1703
void smp_spurious_interrupt(struct pt_regs *regs)
L
Linus Torvalds 已提交
1704
{
1705 1706
	u32 v;

1707 1708
	exit_idle();
	irq_enter();
L
Linus Torvalds 已提交
1709
	/*
1710 1711 1712
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1713
	 */
1714 1715 1716
	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
		ack_APIC_irq();
1717

1718 1719
	inc_irq_stat(irq_spurious_count);

1720
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1721 1722
	pr_info("spurious APIC interrupt on CPU#%d, "
		"should never happen.\n", smp_processor_id());
1723 1724
	irq_exit();
}
L
Linus Torvalds 已提交
1725

1726 1727 1728
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1729
void smp_error_interrupt(struct pt_regs *regs)
1730
{
1731
	u32 v, v1;
L
Linus Torvalds 已提交
1732

1733 1734 1735 1736 1737 1738 1739 1740
	exit_idle();
	irq_enter();
	/* First tickle the hardware, only then report what went on. -- REW */
	v = apic_read(APIC_ESR);
	apic_write(APIC_ESR, 0);
	v1 = apic_read(APIC_ESR);
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
1741

1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
	/*
	 * Here is what the APIC error bits mean:
	 * 0: Send CS error
	 * 1: Receive CS error
	 * 2: Send accept error
	 * 3: Receive accept error
	 * 4: Reserved
	 * 5: Send illegal vector
	 * 6: Received illegal vector
	 * 7: Illegal register address
	 */
	pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1754 1755
		smp_processor_id(), v , v1);
	irq_exit();
L
Linus Torvalds 已提交
1756 1757
}

1758
/**
1759 1760
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
1761 1762
void __init connect_bsp_APIC(void)
{
1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
1775
		imcr_pic_to_apic();
1776 1777
	}
#endif
1778 1779
	if (apic->enable_apic_mode)
		apic->enable_apic_mode();
1780 1781
}

1782 1783 1784 1785 1786 1787 1788
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
1789
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1790
{
1791 1792
	unsigned int value;

1793 1794 1795 1796 1797 1798 1799 1800 1801 1802
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
1803
		imcr_apic_to_pic();
1804 1805 1806 1807
		return;
	}
#endif

1808
	/* Go back to Virtual Wire compatibility mode */
L
Linus Torvalds 已提交
1809

1810 1811 1812 1813 1814 1815
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
1816

1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
1833

1834 1835 1836 1837
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
1838 1839 1840 1841 1842 1843 1844
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1845 1846
}

1847 1848 1849 1850
void __cpuinit generic_processor_info(int apicid, int version)
{
	int cpu;

1851 1852 1853 1854
	/*
	 * Validate version
	 */
	if (version == 0x0) {
1855
		pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1856 1857
			   "fixing up to 0x10. (tell your hw vendor)\n",
				version);
1858
		version = 0x10;
1859
	}
1860
	apic_version[apicid] = version;
1861

1862 1863 1864 1865 1866 1867 1868 1869 1870
	if (num_processors >= nr_cpu_ids) {
		int max = nr_cpu_ids;
		int thiscpu = max + disabled_cpus;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i reached."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
1871 1872 1873 1874
		return;
	}

	num_processors++;
1875
	cpu = cpumask_next_zero(-1, cpu_present_mask);
1876

1877 1878 1879 1880 1881
	if (version != apic_version[boot_cpu_physical_apicid])
		WARN_ONCE(1,
			"ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
			apic_version[boot_cpu_physical_apicid], cpu, version);

1882 1883 1884 1885 1886 1887 1888 1889 1890
	physid_set(apicid, phys_cpu_present_map);
	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
		 */
		cpu = 0;
	}
1891 1892 1893
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

1894
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1895 1896
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1897
#endif
1898

1899 1900
	set_cpu_possible(cpu, true);
	set_cpu_present(cpu, true);
1901 1902
}

1903 1904 1905 1906
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

#ifdef CONFIG_X86_32
int default_apicid_to_node(int logical_apicid)
{
#ifdef CONFIG_SMP
	return apicid_2_node[hard_smp_processor_id()];
#else
	return 0;
#endif
}
1927
#endif
1928

1929
/*
1930
 * Power management
1931
 */
1932 1933 1934
#ifdef CONFIG_PM

static struct {
1935 1936 1937 1938 1939
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;
1961

1962 1963
	if (!apic_pm_state.active)
		return 0;
1964

1965
	maxlvt = lapic_get_maxlvt();
1966

1967
	apic_pm_state.apic_id = apic_read(APIC_ID);
1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1980
#ifdef CONFIG_X86_THERMAL_VECTOR
1981 1982 1983
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
1984

1985 1986
	local_irq_save(flags);
	disable_local_APIC();
1987

1988 1989
	if (intr_remapping_enabled)
		disable_intr_remapping();
1990

1991 1992
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
1993 1994
}

1995
static int lapic_resume(struct sys_device *dev)
L
Linus Torvalds 已提交
1996
{
1997 1998 1999
	unsigned int l, h;
	unsigned long flags;
	int maxlvt;
2000
	int ret = 0;
2001 2002
	struct IO_APIC_route_entry **ioapic_entries = NULL;

2003 2004
	if (!apic_pm_state.active)
		return 0;
2005

2006
	local_irq_save(flags);
2007
	if (intr_remapping_enabled) {
2008 2009 2010
		ioapic_entries = alloc_ioapic_entries();
		if (!ioapic_entries) {
			WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2011 2012
			ret = -ENOMEM;
			goto restore;
2013 2014 2015 2016 2017 2018
		}

		ret = save_IO_APIC_setup(ioapic_entries);
		if (ret) {
			WARN(1, "Saving IO-APIC state failed: %d\n", ret);
			free_ioapic_entries(ioapic_entries);
2019
			goto restore;
2020 2021 2022
		}

		mask_IO_APIC_setup(ioapic_entries);
2023
		legacy_pic->mask_all();
2024
	}
C
Cyrill Gorcunov 已提交
2025

2026
	if (x2apic_mode)
C
Cyrill Gorcunov 已提交
2027
		enable_x2apic();
2028
	else {
C
Cyrill Gorcunov 已提交
2029 2030 2031 2032 2033 2034
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2035 2036 2037 2038
		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_BASE;
		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
		wrmsr(MSR_IA32_APICBASE, l, h);
2039
	}
2040

2041
	maxlvt = lapic_get_maxlvt();
2042 2043 2044 2045 2046 2047 2048 2049
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
C
Cyrill Gorcunov 已提交
2050
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
C
Cyrill Gorcunov 已提交
2064

2065
	if (intr_remapping_enabled) {
2066
		reenable_intr_remapping(x2apic_mode);
2067
		legacy_pic->restore_mask();
2068 2069 2070
		restore_IO_APIC_setup(ioapic_entries);
		free_ioapic_entries(ioapic_entries);
	}
2071
restore:
2072
	local_irq_restore(flags);
C
Cyrill Gorcunov 已提交
2073

2074
	return ret;
2075
}
T
Thomas Gleixner 已提交
2076

2077 2078 2079 2080 2081
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2082 2083 2084 2085 2086
static struct sysdev_class lapic_sysclass = {
	.name		= "lapic",
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
2087

2088
static struct sys_device device_lapic = {
H
Hiroshi Shimamoto 已提交
2089 2090
	.id	= 0,
	.cls	= &lapic_sysclass,
2091
};
T
Thomas Gleixner 已提交
2092

2093 2094 2095
static void __cpuinit apic_pm_activate(void)
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
2096 2097
}

2098
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
2099
{
2100
	int error;
H
Hiroshi Shimamoto 已提交
2101

2102 2103 2104
	if (!cpu_has_apic)
		return 0;
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
H
Hiroshi Shimamoto 已提交
2105

2106 2107 2108 2109
	error = sysdev_class_register(&lapic_sysclass);
	if (!error)
		error = sysdev_register(&device_lapic);
	return error;
L
Linus Torvalds 已提交
2110
}
2111 2112 2113

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2114 2115 2116 2117 2118 2119

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
2120

Y
Yinghai Lu 已提交
2121
#ifdef CONFIG_X86_64
2122 2123

static int __cpuinit apic_cluster_num(void)
L
Linus Torvalds 已提交
2124 2125 2126
{
	int i, clusters, zeros;
	unsigned id;
2127
	u16 *bios_cpu_apicid;
L
Linus Torvalds 已提交
2128 2129
	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);

2130
	bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2131
	bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
L
Linus Torvalds 已提交
2132

2133
	for (i = 0; i < nr_cpu_ids; i++) {
2134
		/* are we being called early in kernel startup? */
2135 2136
		if (bios_cpu_apicid) {
			id = bios_cpu_apicid[i];
2137
		} else if (i < nr_cpu_ids) {
2138 2139 2140 2141
			if (cpu_present(i))
				id = per_cpu(x86_bios_cpu_apicid, i);
			else
				continue;
2142
		} else
2143 2144
			break;

L
Linus Torvalds 已提交
2145 2146 2147 2148 2149 2150
		if (id != BAD_APICID)
			__set_bit(APIC_CLUSTERID(id), clustermap);
	}

	/* Problem:  Partially populated chassis may not have CPUs in some of
	 * the APIC clusters they have been allocated.  Only present CPUs have
2151 2152 2153
	 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
	 * Since clusters are allocated sequentially, count zeros only if
	 * they are bounded by ones.
L
Linus Torvalds 已提交
2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164
	 */
	clusters = 0;
	zeros = 0;
	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
		if (test_bit(i, clustermap)) {
			clusters += 1 + zeros;
			zeros = 0;
		} else
			++zeros;
	}

2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
	return clusters;
}

static int __cpuinitdata multi_checked;
static int __cpuinitdata multi;

static int __cpuinit set_multi(const struct dmi_system_id *d)
{
	if (multi)
		return 0;
C
Cyrill Gorcunov 已提交
2175
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212
	multi = 1;
	return 0;
}

static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

static void __cpuinit dmi_check_multi(void)
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
__cpuinit int apic_is_clustered_box(void)
{
	dmi_check_multi();
	if (multi)
2213 2214
		return 1;

2215 2216 2217
	if (!is_vsmp_box())
		return 0;

L
Linus Torvalds 已提交
2218
	/*
2219 2220
	 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
	 * not guaranteed to be synced between boards
L
Linus Torvalds 已提交
2221
	 */
2222 2223 2224 2225
	if (apic_cluster_num() > 1)
		return 1;

	return 0;
L
Linus Torvalds 已提交
2226
}
Y
Yinghai Lu 已提交
2227
#endif
L
Linus Torvalds 已提交
2228 2229

/*
2230
 * APIC command line parameters
L
Linus Torvalds 已提交
2231
 */
2232
static int __init setup_disableapic(char *arg)
2233
{
L
Linus Torvalds 已提交
2234
	disable_apic = 1;
2235
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2236 2237 2238
	return 0;
}
early_param("disableapic", setup_disableapic);
L
Linus Torvalds 已提交
2239

2240
/* same as disableapic, for compatibility */
2241
static int __init setup_nolapic(char *arg)
2242
{
2243
	return setup_disableapic(arg);
2244
}
2245
early_param("nolapic", setup_nolapic);
L
Linus Torvalds 已提交
2246

2247 2248 2249 2250 2251 2252 2253
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2254
static int __init parse_disable_apic_timer(char *arg)
2255
{
L
Linus Torvalds 已提交
2256
	disable_apic_timer = 1;
2257
	return 0;
2258
}
2259 2260 2261 2262 2263 2264
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2265
}
2266
early_param("nolapic_timer", parse_nolapic_timer);
2267

2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2283
		pr_warning("APIC Verbosity level %s not recognised"
2284 2285 2286 2287 2288 2289 2290 2291
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);