- 18 11月, 2022 9 次提交
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由 William Wang 提交于
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由 Jiawei Lin 提交于
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由 William Wang 提交于
It should fix the timing problem caused by ldld violation check and forward error check
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由 William Wang 提交于
Now we update data field (fwd data, uop) in load queue when load_s2 is valid. It will help to on lq wen fanout problem. State flags will be treated differently. They are still updated accurately according to loadIn.valid
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由 Ziyue-Zhang 提交于
Co-authored-by: NZiyue Zhang <zhangziyue21b@ict.ac.cn>
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由 William Wang 提交于
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由 William Wang 提交于
In previous design, sbuffer valid entry select and sbuffer data write are in the same cycle, which caused huge fanout. An extra write stage is added to solve this problem. Now sbuffer enq logic is divided into 3 stages: sbuffer_in_s0: * read data and meta from store queue * store them in 2 entry fifo queue sbuffer_in_s1: * read data and meta from fifo queue * update sbuffer meta (vtag, ptag, flag) * prevert that line from being sent to dcache (add a block condition) * prepare cacheline level write enable signal, RegNext() data and mask sbuffer_in_s2: * use cacheline level buffer to update sbuffer data and mask * remove dcache write block (if there is)
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由 zhanglinjuan 提交于
* MainPipe: reduce fanout by duplicating registers * MainPipe: fix wrong assert Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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由 William Wang 提交于
Now sbuffer deq logic is divided into 2 stages: sbuffer_out_s0: * read data and meta from sbuffer * RegNext() them * set line state to inflight sbuffer_out_s1: * send write req to dcache sbuffer_out_extra: * receive write result from dcache * update line state
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- 15 11月, 2022 1 次提交
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由 Jiawei Lin 提交于
misc: bump chisel-circt
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- 14 11月, 2022 1 次提交
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由 Steve Gou 提交于
frontend: Add ChiselDB records
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- 11 11月, 2022 1 次提交
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由 Steve Gou 提交于
frontend bump nanhu
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- 10 11月, 2022 3 次提交
- 09 11月, 2022 25 次提交
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由 LinJiawei 提交于
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由 Jenius 提交于
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由 Jenius 提交于
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由 Jenius 提交于
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由 Jenius 提交于
* add 1 stage for mmio_state before sending request to MMIO bus * check whether the last fetch packet commit all its intructions (the result of execution path has been decided) * avoid speculative execution to MMIO bus
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* when f3_flush is enabled, f3_lastHalf_disable is still set and influence the next packet
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由 Jenius 提交于
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由 Guokai Chen 提交于
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由 Jenius 提交于
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* Under the circumstance that 2 continuous ftq reqs both have last half RVI, but the f3_lastHalf.valid cancel condition in wb-stage is set by !f3_lastHalf.valid, which makes the miss pred f3_lastHalf req has not been flushed.
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* reset state_vec register in replacement
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由 Jenius 提交于
* latch arbiter out before entering dataArray, without which will causes write valid ( state_reg ) fanout to every bit of WEM and D of SRAM
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由 Lingrui98 提交于
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由 Lingrui98 提交于
Previously the BranchPredictionUpdate bundle was inherited from BranchPredictionBundle, and that made some field of the bundle unused. It was hard to find which signals are really in use. Now we make BranchPredictionUpdate a independent bundle, so that the signals in it are all in use.
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由 Jenius 提交于
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