Merge pull request #1690 from chenguokai/frontend_db

frontend: Add ChiselDB records

src/main/scala/xiangshan/frontend/IFU.scala

@@ -25,6 +25,7 @@ import xiangshan.cache.mmu._
 import xiangshan.frontend.icache._
 import utils._
 import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle}
+import huancun.utils.ChiselDB
 
 trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{
   def mmioBusWidth = 64
@@ -97,6 +98,24 @@ class IfuToPredChecker(implicit p: Parameters) extends XSBundle {
   val pc            = Vec(PredictWidth, UInt(VAddrBits.W))
 }
 
+class FetchToIBufferDB extends Bundle {
+  val start_addr = UInt(39.W)
+  val instr_count = UInt(32.W)
+  val exception = Bool()
+  val is_cache_hit = Bool()
+}
+
+class IfuWbToFtqDB extends Bundle {
+  val start_addr = UInt(39.W)
+  val is_miss_pred = Bool()
+  val miss_pred_offset = UInt(32.W)
+  val checkJalFault = Bool()
+  val checkRetFault = Bool()
+  val checkTargetFault = Bool()
+  val checkNotCFIFault = Bool()
+  val checkInvalidTaken = Bool()
+}
+
 class NewIFU(implicit p: Parameters) extends XSModule
   with HasICacheParameters
   with HasIFUConst
@@ -762,6 +781,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
         wb_ftq_req.startAddr, wb_ftq_req.nextStartAddr, wb_ftq_req.ftqOffset.valid, wb_ftq_req.ftqOffset.bits)
   }
 
+
   /** performance counter */
   val f3_perf_info     = RegEnable(f2_perf_info,  f2_fire)
   val f3_req_0    = io.toIbuffer.fire()
@@ -802,5 +822,41 @@ class NewIFU(implicit p: Parameters) extends XSModule
   XSPerfAccumulate("hit_0_except_1",   f3_perf_info.hit_0_except_1 && io.toIbuffer.fire() )
   XSPerfAccumulate("miss_0_except_1",   f3_perf_info.miss_0_except_1 && io.toIbuffer.fire() )
   XSPerfAccumulate("except_0",   f3_perf_info.except_0 && io.toIbuffer.fire() )
+
+  val fetchToIBufferTable = ChiselDB.createTable("FetchToIBuffer" + p(XSCoreParamsKey).HartId.toString, new FetchToIBufferDB)
+  val ifuWbToFtqTable = ChiselDB.createTable("IfuWbToFtq" + p(XSCoreParamsKey).HartId.toString, new IfuWbToFtqDB)
+
+  val fetchIBufferDumpData = Wire(new FetchToIBufferDB)
+  fetchIBufferDumpData.start_addr := f3_ftq_req.startAddr
+  fetchIBufferDumpData.instr_count := PopCount(io.toIbuffer.bits.enqEnable)
+  fetchIBufferDumpData.exception := (f3_perf_info.except_0 && io.toIbuffer.fire()) || (f3_perf_info.hit_0_except_1 && io.toIbuffer.fire()) || (f3_perf_info.miss_0_except_1 && io.toIbuffer.fire())
+  fetchIBufferDumpData.is_cache_hit := f3_hit
+
+  val ifuWbToFtqDumpData = Wire(new IfuWbToFtqDB)
+  ifuWbToFtqDumpData.start_addr := wb_ftq_req.startAddr
+  ifuWbToFtqDumpData.is_miss_pred := checkFlushWb.bits.misOffset.valid
+  ifuWbToFtqDumpData.miss_pred_offset := checkFlushWb.bits.misOffset.bits
+  ifuWbToFtqDumpData.checkJalFault := checkJalFault
+  ifuWbToFtqDumpData.checkRetFault := checkRetFault
+  ifuWbToFtqDumpData.checkTargetFault := checkTargetFault
+  ifuWbToFtqDumpData.checkNotCFIFault := checkNotCFIFault
+  ifuWbToFtqDumpData.checkInvalidTaken := checkInvalidTaken
+
+  fetchToIBufferTable.log(
+    data = fetchIBufferDumpData,
+    en = io.toIbuffer.fire(),
+    site = "IFU" + p(XSCoreParamsKey).HartId.toString,
+    clock = clock,
+    reset = reset
+  )
+  ifuWbToFtqTable.log(
+    data = ifuWbToFtqDumpData,
+    en = checkFlushWb.valid,
+    site = "IFU" + p(XSCoreParamsKey).HartId.toString,
+    clock = clock,
+    reset = reset
+  )
+
+
 }
 

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -24,6 +24,19 @@ import xiangshan._
 import xiangshan.frontend.icache._
 import xiangshan.backend.CtrlToFtqIO
 import xiangshan.backend.decode.ImmUnion
+import huancun.utils.ChiselDB
+
+class FtqDebugBundle extends Bundle {
+  val pc = UInt(39.W)
+  val target = UInt(39.W)
+  val isBr = Bool()
+  val isJmp = Bool()
+  val isCall = Bool()
+  val isRet = Bool()
+  val misPred = Bool()
+  val isTaken = Bool()
+  val predStage = UInt(2.W)
+}
 
 class FtqPtr(implicit p: Parameters) extends CircularQueuePtr[FtqPtr](
   p => p(XSCoreParamsKey).FtqSize
@@ -1192,7 +1205,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
 
   io.bpuInfo.bpRight := PopCount(mbpRights)
   io.bpuInfo.bpWrong := PopCount(mbpWrongs)
-
+  
+  val ftqBranchTraceDB = ChiselDB.createTable("FTQTable" + p(XSCoreParamsKey).HartId.toString, new FtqDebugBundle)
   // Cfi Info
   for (i <- 0 until PredictWidth) {
     val pc = commit_pc_bundle.startAddr + (i * instBytes).U
@@ -1214,6 +1228,25 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     p"taken(${isTaken}) mispred(${misPred}) cycle($predCycle) hist(${histPtr.value}) " +
     p"startAddr(${Hexadecimal(commit_pc_bundle.startAddr)}) AddIntoHist(${addIntoHist}) " +
     p"brInEntry(${inFtbEntry}) brIdx(${brIdx}) target(${Hexadecimal(target)})\n")
+
+    val logbundle = Wire(new FtqDebugBundle)
+    logbundle.pc := pc
+    logbundle.target := target
+    logbundle.isBr := isBr
+    logbundle.isJmp := isJmp
+    logbundle.isCall := isJmp && commit_pd.hasCall
+    logbundle.isRet := isJmp && commit_pd.hasRet
+    logbundle.misPred := misPred
+    logbundle.isTaken := isTaken
+    logbundle.predStage := commit_stage
+
+    ftqBranchTraceDB.log(
+      data = logbundle /* hardware of type T */,
+      en = v && do_commit && isCfi,
+      site = "FTQ" + p(XSCoreParamsKey).HartId.toString,
+      clock = clock,
+      reset = reset
+    )
   }
 
   val enq = io.fromBpu.resp