misc: bump chisel-circt

Makefile

@@ -34,8 +34,8 @@ SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-
 # select firrtl compiler
 ifeq ($(MFC),1)
 override FC_ARGS = --mfc
-override FPGA_MEM_ARGS =
-override SIM_MEM_ARGS =
+override FPGA_MEM_ARGS = --infer-rw
+override SIM_MEM_ARGS = --infer-rw
 endif
 
 

build.sc

@@ -28,7 +28,7 @@ object ivys {
   val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
   val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
   val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.3.2"
-  val chiselCirct = ivy"com.sifive::chisel-circt:0.4.0"
+  val chiselCirct = ivy"com.sifive::chisel-circt:0.6.0"
   val scalatest = ivy"org.scalatest::scalatest:3.2.2"
   val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
 }