<bug-fix> IFU: fix f3_lastHalf_disable flush bug

* when f3_flush is enabled, f3_lastHalf_disable is still set and
influence the next packet

src/main/scala/xiangshan/frontend/IFU.scala

@@ -692,7 +692,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
     */
   //f3_fire is after wb_valid
   when(wb_valid && RegNext(f3_hasLastHalf,init = false.B) 
-        && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) && !f3_fire  && !RegNext(f3_fire,init = false.B)
+        && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) && !f3_fire  && !RegNext(f3_fire,init = false.B) && !f3_flush
       ){
     f3_lastHalf_disable := true.B
   }