IPrefetch: fix merge error for req.ready

src/main/scala/xiangshan/frontend/icache/IPrefetch.scala

@@ -111,7 +111,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
 
   fromITLB.ready := true.B
 
-  fromFtq.req.ready :=  (!enableBit || (enableBit && p3_ready)) && toIMeta.ready
+  fromFtq.req.ready :=  true.B
 
   /** Prefetch Stage 1: cache probe filter */
   val p1_valid =  generatePipeControl(lastFire = p0_fire, thisFire = p1_fire || p1_discard, thisFlush = false.B, lastFlush = false.B)