have not connected the performance counters to CSR

Case: vvvdvvvddddd
            ^    ^
If the leftmost instruction is a store and it writebacks, these instructions won't be replayed.
However, we cannot move headPtr to the left hand side of the dispatchPtr since there're still
instructions that have not been dispatched to issue queues.
In this case, we only remove the instructions before dispatchPtr.
Moving headPtr in case of store writeback only affects performance, since instructions leave dispatch queue when they commit.

This reverts commit 176183df.

* lr_valid will be copied from processor to emulator when:
    * sc falied &&
    * processor's lr_valid is set to false &&
    * emulator's lr_valid is set to true