roqIdx: use CircularQueuePtr

src/main/scala/utils/CircularQueuePtr.scala

@@ -9,6 +9,9 @@ class CircularQueuePtr(val entries: Int) extends Bundle {
   val flag = Bool()
   val value = UInt(PTR_WIDTH.W)
 
+  override def toPrintable: Printable = {
+    p"$flag:$value"
+  }
 }
 
 trait HasCircularQueuePtrHelper {

src/main/scala/xiangshan/Bundle.scala

@@ -5,6 +5,7 @@ import chisel3.util._
 import bus.simplebus._
 import xiangshan.backend.brq.BrqPtr
 import xiangshan.backend.rename.FreeListPtr
+import xiangshan.backend.roq.RoqPtr
 import xiangshan.frontend.PreDecodeInfo
 import xiangshan.frontend.HasBPUParameter
 import xiangshan.frontend.HasTageParameter
@@ -139,35 +140,37 @@ class CfCtrl extends XSBundle {
   val brTag = new BrqPtr
 }
 
-trait HasRoqIdx { this: HasXSParameter =>
-  val roqIdx = UInt(RoqIdxWidth.W)
+// trait HasRoqIdx { this: HasXSParameter =>
+  
 
-  def isAfter(thatIdx: UInt): Bool = {
-    Mux(
-      this.roqIdx.head(1) === thatIdx.head(1),
-      this.roqIdx.tail(1) > thatIdx.tail(1),
-      this.roqIdx.tail(1) < thatIdx.tail(1)
-    )
-  }
+//   def isAfter(thatIdx: UInt): Bool = {
+//     Mux(
+//       this.roqIdx.head(1) === thatIdx.head(1),
+//       this.roqIdx.tail(1) > thatIdx.tail(1),
+//       this.roqIdx.tail(1) < thatIdx.tail(1)
+//     )
+//   }
 
-  def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
-    isAfter(that.roqIdx)
-  }
+//   def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
+//     isAfter(that.roqIdx)
+//   }
 
-  def needFlush(redirect: Valid[Redirect]): Bool = {
-    redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe || this.isAfter(redirect.bits.roqIdx)) // TODO: need check by JiaWei
-  }
-}
+//   def needFlush(redirect: Valid[Redirect]): Bool = {
+//     redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe || this.isAfter(redirect.bits.roqIdx)) // TODO: need check by JiaWei
+//   }
+// }
 
 // CfCtrl -> MicroOp at Rename Stage
-class MicroOp extends CfCtrl with HasRoqIdx {
+class MicroOp extends CfCtrl /*with HasRoqIdx*/ {
   val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
   val src1State, src2State, src3State = SrcState()
+  val roqIdx = new RoqPtr
   val lsroqIdx = UInt(LsroqIdxWidth.W)
   val diffTestDebugLrScValid = Bool()
 }
 
-class Redirect extends XSBundle with HasRoqIdx {
+class Redirect extends XSBundle /*with HasRoqIdx*/ {
+  val roqIdx = new RoqPtr
   val isException = Bool()
   val isMisPred = Bool()
   val isReplay = Bool()
@@ -224,7 +227,8 @@ class RoqCommit extends XSBundle {
   val isWalk = Bool()
 }
 
-class TlbFeedback extends XSBundle with HasRoqIdx{
+class TlbFeedback extends XSBundle {
+  val roqIdx = new RoqPtr
   val hit = Bool()
 }
 

src/main/scala/xiangshan/XSCore.scala

@@ -55,7 +55,7 @@ case class XSCoreParameters
   NRFpReadPorts: Int = 14,
   NRFpWritePorts: Int = 8,
   LsroqSize: Int = 16,
-  RoqSize: Int = 32,
+  RoqSize: Int = 24,
   dpParams: DispatchParameters = DispatchParameters(
     DqEnqWidth = 4,
     IntDqSize = 12,

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -167,7 +167,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   io.redirect.valid := commitValid &&
     commitIsMisPred &&
     !io.roqRedirect.valid &&
-    !io.redirect.bits.needFlush(io.memRedirect)
+    !io.redirect.bits.roqIdx.needFlush(io.memRedirect)
 
   io.redirect.bits := commitEntry.exuOut.redirect
   io.out.valid := commitValid
@@ -228,7 +228,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
       val ptr = BrqPtr(brQueue(i).ptrFlag, i.U)
       when(
         (io.redirect.valid && ptr.needBrFlush(io.redirect.bits.brTag)) ||
-          (s.isWb && brQueue(i).exuOut.uop.needFlush(io.memRedirect))
+          (s.isWb && brQueue(i).exuOut.uop.roqIdx.needFlush(io.memRedirect))
       ){
         s := s_idle
       }

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -6,6 +6,7 @@ import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
 import chisel3.ExcitingUtils._
+import xiangshan.backend.roq.RoqPtr
 
 case class DispatchParameters
 (
@@ -30,7 +31,7 @@ class Dispatch extends XSModule {
     // enq Roq
     val toRoq =  Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get RoqIdx
-    val roqIdxs = Input(Vec(RenameWidth, UInt(RoqIdxWidth.W)))
+    val roqIdxs = Input(Vec(RenameWidth, new RoqPtr))
     // enq Lsroq
     val toLsroq =  Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get LsroqIdx

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -5,6 +5,7 @@ import chisel3.util._
 import chisel3.ExcitingUtils._
 import xiangshan._
 import utils.{XSDebug, XSError, XSInfo}
+import xiangshan.backend.roq.RoqPtr
 
 // read rob and enqueue
 class Dispatch1 extends XSModule {
@@ -16,7 +17,7 @@ class Dispatch1 extends XSModule {
     // enq Roq
     val toRoq =  Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get RoqIdx
-    val roqIdxs = Input(Vec(RenameWidth, UInt(RoqIdxWidth.W)))
+    val roqIdxs = Input(Vec(RenameWidth, new RoqPtr))
     // enq Lsroq
     val toLsroq =  Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get LsroqIdx
@@ -59,7 +60,7 @@ class Dispatch1 extends XSModule {
   val cancelled = WireInit(VecInit(Seq.fill(RenameWidth)(io.redirect.valid && !io.redirect.bits.isReplay)))
 
   val uopWithIndex = Wire(Vec(RenameWidth, new MicroOp))
-  val roqIndexReg = Reg(Vec(RenameWidth, UInt(RoqIdxWidth.W)))
+  val roqIndexReg = Reg(Vec(RenameWidth, new RoqPtr))
   val roqIndexRegValid = RegInit(VecInit(Seq.fill(RenameWidth)(false.B)))
   val roqIndexAcquired = WireInit(VecInit(Seq.tabulate(RenameWidth)(i => io.toRoq(i).ready || roqIndexRegValid(i))))
   val lsroqIndexReg = Reg(Vec(RenameWidth, UInt(LsroqIdxWidth.W)))

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -106,15 +106,15 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
   val roqNeedFlush = Wire(Vec(size, Bool()))
   val needCancel = Wire(Vec(size, Bool()))
   for (i <- 0 until size) {
-    roqNeedFlush(i) := uopEntries(i.U).needFlush(io.redirect)
+    roqNeedFlush(i) := uopEntries(i.U).roqIdx.needFlush(io.redirect)
     needCancel(i) := stateEntries(i) =/= s_invalid && ((roqNeedFlush(i) && mispredictionValid) || exceptionValid || flushPipeValid)
     when (needCancel(i)) {
       stateEntries(i) := s_invalid
     }
 
     XSInfo(needCancel(i), p"valid entry($i)(pc = ${Hexadecimal(uopEntries(i.U).cf.pc)}) " +
-      p"roqIndex 0x${Hexadecimal(uopEntries(i.U).roqIdx)} " +
-      p"cancelled with redirect roqIndex 0x${Hexadecimal(io.redirect.bits.roqIdx)}\n")
+      p"roqIndex ${uopEntries(i.U).roqIdx} " +
+      p"cancelled with redirect roqIndex ${io.redirect.bits.roqIdx}\n")
   }
 
   // replay: from s_dispatched to s_valid
@@ -127,7 +127,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
     }
 
     XSInfo(needReplay(i), p"dispatched entry($i)(pc = ${Hexadecimal(uopEntries(i.U).cf.pc)}) " +
-      p"replayed with roqIndex ${Hexadecimal(io.redirect.bits.roqIdx)}\n")
+      p"replayed with roqIndex ${io.redirect.bits.roqIdx}\n")
   }
 
   /**

src/main/scala/xiangshan/backend/exu/AluExeUnit.scala

@@ -15,7 +15,7 @@ class AluExeUnit extends Exu(Exu.aluExeUnitCfg) {
   val (iovalid, src1, src2, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, 
     io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
 
-  val redirectHit = uop.needFlush(io.redirect)
+  val redirectHit = uop.roqIdx.needFlush(io.redirect)
   val valid = iovalid && !redirectHit
 
   val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)

src/main/scala/xiangshan/backend/exu/DivExeUnit.scala

@@ -55,9 +55,10 @@ class DivExeUnit extends Exu(Exu.divExeUnitCfg) {
     io.redirect.bits.isFlushPipe,
     io.redirect.bits.brTag.value
   )
-  XSDebug(io.in.valid, "src1:%x src2:%x func:%b pc:%x roqIdx:%d\n", src1, src2, func, io.in.bits.uop.cf.pc, io.in.bits.uop.roqIdx)
-  XSDebug(io.out.valid, "Out(%d %d) res:%x func:%b pc:%x roqIdx:%d\n",
-    io.out.valid, io.out.ready, io.out.bits.data, io.out.bits.uop.ctrl.fuOpType, io.out.bits.uop.cf.pc, io.out.bits.uop.roqIdx
+  XSDebug(io.in.valid, p"src1: 0x${Hexadecimal(src1)} src2: 0x${Hexadecimal(src2)} func: ${Binary(func)} " +
+    p"pc: ${io.in.bits.uop.cf.pc} roqIdx: ${io.in.bits.uop.roqIdx}\n")
+  XSDebug(io.out.valid, p"Out(${io.out.valid} ${io.out.ready}) res: ${Hexadecimal(io.out.bits.data)} " +
+    p"func: ${Binary(io.out.bits.uop.ctrl.fuOpType)} pc: ${Hexadecimal(io.out.bits.uop.cf.pc)} roqIdx: ${io.out.bits.uop.roqIdx}\n"
   )
 
 }

src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala

@@ -53,9 +53,12 @@ class MulDivFenceExeUnit extends Exu(Exu.mulDivFenceExeUnitCfg){
     io.redirect.bits.isFlushPipe,
     io.redirect.bits.brTag.value
   )
-  XSDebug(io.in.valid, "src1:%x src2:%x pc:%x fuType:%b fuOpType:%b roqIdx:%d (%d%d%d)\n", src1, src2, io.in.bits.uop.cf.pc, io.in.bits.uop.ctrl.fuType, io.in.bits.uop.ctrl.fuOpType, io.in.bits.uop.roqIdx, isMul, isDiv, isFence)
+  XSDebug(io.in.valid, "src1:%x src2:%x pc:%x fuType:%b fuOpType:%b roqIdx:%d (%d%d%d)\n",
+    src1, src2, io.in.bits.uop.cf.pc, io.in.bits.uop.ctrl.fuType, io.in.bits.uop.ctrl.fuOpType,
+    io.in.bits.uop.roqIdx.asUInt, isMul, isDiv, isFence)
   XSDebug(io.out.valid, "Out(%d %d) res:%x pc:%x fuType:%b fuOpType:%b roqIdx:%d chosen:%d\n",
-    io.out.valid, io.out.ready, io.out.bits.data, io.out.bits.uop.cf.pc, io.in.bits.uop.ctrl.fuType, io.in.bits.uop.ctrl.fuOpType, io.in.bits.uop.roqIdx, arb.io.chosen
+    io.out.valid, io.out.ready, io.out.bits.data, io.out.bits.uop.cf.pc, io.in.bits.uop.ctrl.fuType,
+    io.in.bits.uop.ctrl.fuOpType, io.in.bits.uop.roqIdx.asUInt, arb.io.chosen
   )
 }
 

src/main/scala/xiangshan/backend/fu/Divider.scala

@@ -67,7 +67,7 @@ class Divider(len: Int) extends FunctionUnit(divCfg) {
     }
   }
 
-  when(state=/=s_idle && ctrlReg.uop.needFlush(io.redirect)){
+  when(state=/=s_idle && ctrlReg.uop.roqIdx.needFlush(io.redirect)){
     state := s_idle
   }
 

src/main/scala/xiangshan/backend/fu/Jump.scala

@@ -13,7 +13,7 @@ class Jump extends FunctionUnit(jmpCfg){
 
   val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
 
-  val redirectHit = uop.needFlush(io.redirect)
+  val redirectHit = uop.roqIdx.needFlush(io.redirect)
   val valid = iovalid && !redirectHit
 
   val isRVC = uop.cf.brUpdate.pd.isRVC

src/main/scala/xiangshan/backend/fu/Multiplier.scala

@@ -41,7 +41,7 @@ trait HasPipelineReg { this: ArrayMultiplier =>
   val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
   val rdyVec = Array.fill(latency)(Wire(Bool())) :+ io.out.ready
   val ctrlVec = io.in.bits.ctrl +: Array.fill(latency)(Reg(new MulDivCtrl))
-  val flushVec = ctrlVec.zip(validVec).map(x => x._2 && x._1.uop.needFlush(io.redirect))
+  val flushVec = ctrlVec.zip(validVec).map(x => x._2 && x._1.uop.roqIdx.needFlush(io.redirect))
 
   for(i <- 0 until latency){
     rdyVec(i) := !validVec(i+1) || rdyVec(i+1)

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -39,7 +39,7 @@ class IssueQueue
   XSDebug(io.tlbFeedback.valid,
     "tlb feedback: hit: %d roqIdx: %d\n",
     io.tlbFeedback.bits.hit,
-    io.tlbFeedback.bits.roqIdx
+    io.tlbFeedback.bits.roqIdx.asUInt
   )
   /*
       invalid --[enq]--> valid --[deq]--> wait --[tlbHit]--> invalid
@@ -259,11 +259,11 @@ class IssueQueue
     val cnt = cntQueue(uopQIdx)
     val nextIdx = i.U - moveMask(i)
     //TODO: support replay
-    val roqIdxMatch = uop.roqIdx === io.tlbFeedback.bits.roqIdx
+    val roqIdxMatch = uop.roqIdx.asUInt === io.tlbFeedback.bits.roqIdx.asUInt
     val notEmpty = stateQueue(i)=/=s_invalid
     val replayThis = (stateQueue(i)===s_wait) && tlbMiss && roqIdxMatch
     val tlbHitThis = notEmpty && tlbHit && roqIdxMatch
-    val flushThis = notEmpty && uop.needFlush(io.redirect)
+    val flushThis = notEmpty && uop.roqIdx.needFlush(io.redirect)
 
     when(replayThis){
       stateQueue(nextIdx) := s_replay

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -201,17 +201,17 @@ class ReservationStation
   // Redirect
   //-----------------------------------------
   // redirect enq
-  enqRedHit := io.redirect.valid && io.enqCtrl.bits.needFlush(io.redirect)
+  enqRedHit := io.redirect.valid && io.enqCtrl.bits.roqIdx.needFlush(io.redirect)
 
   // redirect issQue
-  val redHitVec = List.tabulate(iqSize)(i => issQue(i).uop.needFlush(io.redirect))
+  val redHitVec = List.tabulate(iqSize)(i => issQue(i).uop.roqIdx.needFlush(io.redirect))
   for (i <- validQue.indices) {
     when (redHitVec(i) && validQue(i)) {
       validQue(i) := false.B
     }
   }
   // reditect deq(issToExu)
-  val redIdHitVec = List.tabulate(iqSize)(i => issQue(idQue(i)).uop.needFlush(io.redirect))
+  val redIdHitVec = List.tabulate(iqSize)(i => issQue(idQue(i)).uop.roqIdx.needFlush(io.redirect))
   val selIsRed = ParallelOR((deqSelOH & VecInit(redIdHitVec).asUInt).asBools).asBool
 
   //-----------------------------------------
@@ -219,7 +219,7 @@ class ReservationStation
   //-----------------------------------------
   val issueToExu = Reg(new ExuInput)
   val issueToExuValid = RegInit(false.B)
-  val deqFlushHit = issueToExu.uop.needFlush(io.redirect)
+  val deqFlushHit = issueToExu.uop.roqIdx.needFlush(io.redirect)
   val deqCanIn = !issueToExuValid || io.deq.ready || deqFlushHit
   
   val toIssFire = deqCanIn && has1Rdy && !isPop && !selIsRed
@@ -259,7 +259,7 @@ class ReservationStation
   // send out directly without store the data
   val enqAlreadyRdy = if(src3Listen) { if(src2Listen) enqSrcRdy(0)&&enqSrcRdy(1)&&enqSrcRdy(2) else enqSrcRdy(0)&&enqSrcRdy(2) } else  { if(src2Listen) enqSrcRdy(0)&&enqSrcRdy(1) else enqSrcRdy(0) }
   val enqALRdyNext = OneCycleFire(enqAlreadyRdy && enqFire)
-  val enqSendFlushHit = issQue(enqSelIqNext).uop.needFlush(io.redirect)
+  val enqSendFlushHit = issQue(enqSelIqNext).uop.roqIdx.needFlush(io.redirect)
   val enqSendEnable = if(fifo) { RegNext(tailAll===0.U) && enqALRdyNext && (!issueToExuValid || deqFlushHit) && (enqSelIqNext === deqSelIq) && !isPop && !enqSendFlushHit/* && has1Rdy*//* && io.deq.ready*/ } else { enqALRdyNext && (!issueToExuValid || deqFlushHit) && (enqSelIqNext === deqSelIq) && !isPop && !enqSendFlushHit/* && has1Rdy*//* && io.deq.ready*/ } // FIXME: has1Rdy has combination loop
   when (enqSendEnable) {
     io.deq.valid := true.B
@@ -293,7 +293,9 @@ class ReservationStation
         }
         // XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit, "WakeUp: Sel:%d Src:(%d|%d) Rdy:%d Hit:%d HitVec:%b Data:%x\n", i.U, j.U, psrc(i)(j), srcRdyVec(i)(j), hit, VecInit(hitVec).asUInt, data)
         for (k <- cdbValid.indices) {
-          XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit && hitVec(k), "WakeUpHit: IQIdx:%d Src%d:%d Ports:%d Data:%x Pc:%x RoqIdx:%x\n", i.U, j.U, psrc(i)(j), k.U, cdbData(k), io.wakeUpPorts(k).bits.uop.cf.pc, io.wakeUpPorts(k).bits.uop.roqIdx)
+          XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit && hitVec(k),
+            "WakeUpHit: IQIdx:%d Src%d:%d Ports:%d Data:%x Pc:%x RoqIdx:%x\n",
+            i.U, j.U, psrc(i)(j), k.U, cdbData(k), io.wakeUpPorts(k).bits.uop.cf.pc, io.wakeUpPorts(k).bits.uop.roqIdx.asUInt)
         }
       }
     }
@@ -317,13 +319,15 @@ class ReservationStation
         }
         // XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit, "BypassCtrl: Sel:%d Src:(%d|%d) Rdy:%d Hit:%d HitVec:%b\n", i.U, j.U, psrc(i)(j), srcRdyVec(i)(j), hit, VecInit(hitVec).asUInt)
         for (k <- bpValid.indices) {
-          XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit && hitVec(k), "BypassCtrlHit: IQIdx:%d Src%d:%d Ports:%d Pc:%x RoqIdx:%x\n", i.U, j.U, psrc(i)(j), k.U, io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx)
+          XSDebug(validQue(i) && !srcRdyVec(i)(j) && hit && hitVec(k),
+            "BypassCtrlHit: IQIdx:%d Src%d:%d Ports:%d Pc:%x RoqIdx:%x\n",
+            i.U, j.U, psrc(i)(j), k.U, io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx.asUInt)
         }
         // XSDebug(RegNext(validQue(i) && !srcRdyVec(i)(j) && hit), "BypassData: Sel:%d Src:(%d|%d) HitVecNext:%b Data:%x (for last cycle's Ctrl)\n", i.U, j.U, psrc(i)(j), VecInit(hitVecNext).asUInt, ParallelMux(hitVecNext zip bpData))
         for (k <- bpValid.indices) {
           XSDebug(RegNext(validQue(i) && !srcRdyVec(i)(j) && hit && hitVec(k)),
             "BypassDataHit: IQIdx:%d Src%d:%d Ports:%d Data:%x Pc:%x RoqIdx:%x\n",
-            i.U, j.U, psrc(i)(j), k.U, bpData(k), io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx)
+            i.U, j.U, psrc(i)(j), k.U, bpData(k), io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx.asUInt)
         }
       }
     }
@@ -344,11 +348,15 @@ class ReservationStation
       }
       // XSDebug(enqFire && hit, "EnqBypassCtrl: enqSelIq:%d Src:(%d|%d) Hit:%d HitVec:%b \n", enqSelIq, i.U, enqPsrc(i), hit, VecInit(hitVec).asUInt)
       for (k <- bpValid.indices) {
-        XSDebug(enqFire && hit && !enqSrcRdy(i) && hitVec(k), "EnqBypassCtrlHit: enqSelIq:%d Src%d:%d Ports:%d Pc:%x RoqIdx:%x\n", enqSelIq, i.U, enqPsrc(i), k.U, io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx)
+        XSDebug(enqFire && hit && !enqSrcRdy(i) && hitVec(k),
+          "EnqBypassCtrlHit: enqSelIq:%d Src%d:%d Ports:%d Pc:%x RoqIdx:%x\n",
+          enqSelIq, i.U, enqPsrc(i), k.U, io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx.asUInt)
       }
       // XSDebug(RegNext(enqFire && hit), "EnqBypassData: enqSelIqNext:%d Src:(%d|%d) HitVecNext:%b Data:%x (for last cycle's Ctrl)\n", enqSelIqNext, i.U, enqPsrc(i), VecInit(hitVecNext).asUInt, ParallelMux(hitVecNext zip bpData))
       for (k <- bpValid.indices) {
-        XSDebug(RegNext(enqFire && hit && !enqSrcRdy(i) && hitVec(k)), "EnqBypassDataHit: enqSelIq:%d Src%d:%d Ports:%d Data:%x Pc:%x RoqIdx:%x\n", enqSelIq, i.U, enqPsrc(i), k.U, bpData(k), io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx)
+        XSDebug(RegNext(enqFire && hit && !enqSrcRdy(i) && hitVec(k)),
+          "EnqBypassDataHit: enqSelIq:%d Src%d:%d Ports:%d Data:%x Pc:%x RoqIdx:%x\n",
+          enqSelIq, i.U, enqPsrc(i), k.U, bpData(k), io.bypassUops(k).bits.cf.pc, io.bypassUops(k).bits.roqIdx.asUInt)
       }
     }
   
@@ -364,12 +372,23 @@ class ReservationStation
     sel.bits.ctrl.fpWen := issQue(deqSelIq).uop.ctrl.fpWen
   }
   XSInfo(io.redirect.valid, "Redirect: valid:%d isExp:%d isFpp:%d brTag:%d redHitVec:%b redIdHitVec:%b enqHit:%d selIsRed:%d\n", io.redirect.valid, io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.brTag.value, VecInit(redHitVec).asUInt, VecInit(redIdHitVec).asUInt, enqRedHit, selIsRed)
-  XSInfo(enqFire, s"EnqCtrl(%d %d) enqSelIq:%d Psrc/Rdy(%d:%d %d:%d %d:%d) Dest:%d oldDest:%d pc:%x roqIdx:%x\n", io.enqCtrl.valid, io.enqCtrl.ready, enqSelIq
-    , io.enqCtrl.bits.psrc1, io.enqCtrl.bits.src1State, io.enqCtrl.bits.psrc2, io.enqCtrl.bits.src2State, io.enqCtrl.bits.psrc3, io.enqCtrl.bits.src3State, io.enqCtrl.bits.pdest, io.enqCtrl.bits.old_pdest, io.enqCtrl.bits.cf.pc, io.enqCtrl.bits.roqIdx)
-  XSInfo(enqFireNext, "EnqData: src1:%x src2:%x src3:%x pc:%x roqIdx:%x(for last cycle's Ctrl)\n", io.enqData.src1, io.enqData.src2, io.enqData.src3, issQue(enqSelIqNext).uop.cf.pc, issQue(enqSelIqNext).uop.roqIdx)
-  XSInfo(deqFire, "Deq:(%d %d) [%d|%x][%d|%x][%d|%x] pdest:%d pc:%x roqIdx:%x\n", io.deq.valid, io.deq.ready, io.deq.bits.uop.psrc1, io.deq.bits.src1, io.deq.bits.uop.psrc2, io.deq.bits.src2, io.deq.bits.uop.psrc3, io.deq.bits.src3, io.deq.bits.uop.pdest, io.deq.bits.uop.cf.pc, io.deq.bits.uop.roqIdx)
+  XSInfo(enqFire,
+    s"EnqCtrl(%d %d) enqSelIq:%d Psrc/Rdy(%d:%d %d:%d %d:%d) Dest:%d oldDest:%d pc:%x roqIdx:%x\n",
+    io.enqCtrl.valid, io.enqCtrl.ready, enqSelIq, io.enqCtrl.bits.psrc1, io.enqCtrl.bits.src1State,
+    io.enqCtrl.bits.psrc2, io.enqCtrl.bits.src2State, io.enqCtrl.bits.psrc3, io.enqCtrl.bits.src3State,
+    io.enqCtrl.bits.pdest, io.enqCtrl.bits.old_pdest, io.enqCtrl.bits.cf.pc, io.enqCtrl.bits.roqIdx.asUInt)
+  XSInfo(enqFireNext,
+    "EnqData: src1:%x src2:%x src3:%x pc:%x roqIdx:%x(for last cycle's Ctrl)\n",
+    io.enqData.src1, io.enqData.src2, io.enqData.src3, issQue(enqSelIqNext).uop.cf.pc, issQue(enqSelIqNext).uop.roqIdx.asUInt)
+  XSInfo(deqFire,
+    "Deq:(%d %d) [%d|%x][%d|%x][%d|%x] pdest:%d pc:%x roqIdx:%x\n",
+    io.deq.valid, io.deq.ready, io.deq.bits.uop.psrc1, io.deq.bits.src1, io.deq.bits.uop.psrc2, io.deq.bits.src2, io.deq.bits.uop.psrc3,
+    io.deq.bits.src3, io.deq.bits.uop.pdest, io.deq.bits.uop.cf.pc, io.deq.bits.uop.roqIdx.asUInt)
   XSDebug("tailAll:%d KID(%d%d%d) tailDot:%b tailDot2:%b selDot:%b popDot:%b moveDot:%b In(%d %d) Out(%d %d)\n", tailAll, tailKeep, tailInc, tailDec, tailDot, tailDot2, selDot, popDot, moveDot, io.enqCtrl.valid, io.enqCtrl.ready, io.deq.valid, io.deq.ready)
-  XSInfo(issueToExuValid, "FireStage:Out(%d %d) src1(%d|%x) src2(%d|%x) src3(%d|%x) deqFlush:%d pc:%x roqIdx:%d\n", io.deq.valid, io.deq.ready, issueToExu.uop.psrc1, issueToExu.src1, issueToExu.uop.psrc2, issueToExu.src2, issueToExu.uop.psrc3, issueToExu.src3, deqFlushHit, issueToExu.uop.cf.pc, issueToExu.uop.roqIdx)
+  XSInfo(issueToExuValid,
+    "FireStage:Out(%d %d) src1(%d|%x) src2(%d|%x) src3(%d|%x) deqFlush:%d pc:%x roqIdx:%d\n",
+    io.deq.valid, io.deq.ready, issueToExu.uop.psrc1, issueToExu.src1, issueToExu.uop.psrc2, issueToExu.src2, issueToExu.uop.psrc3, issueToExu.src3,
+    deqFlushHit, issueToExu.uop.cf.pc, issueToExu.uop.roqIdx.asUInt)
   if(enableBypass) {
     XSDebug("popOne:%d isPop:%d popSel:%d deqSel:%d deqCanIn:%d toIssFire:%d has1Rdy:%d selIsRed:%d nonValid:%b SelUop:(%d, %d)\n", popOne, isPop, popSel, deqSel, deqCanIn, toIssFire, has1Rdy, selIsRed, nonValid, io.selectedUop.valid, io.selectedUop.bits.pdest)
   } else {
@@ -396,7 +415,7 @@ class ReservationStation
         srcData(idQue(i))(2),
         issQue(idQue(i)).uop.brTag.value,
         issQue(idQue(i)).uop.cf.pc,
-        issQue(idQue(i)).uop.roqIdx
+        issQue(idQue(i)).uop.roqIdx.asUInt
       )
     }.otherwise {
       XSDebug("%d |%d|%d| %d|%b|%x| %d|%b|%x| %d|%b|%x| %x |%x|%x\n",
@@ -414,7 +433,7 @@ class ReservationStation
         srcData(idQue(i))(2),
         issQue(idQue(i)).uop.brTag.value,
         issQue(idQue(i)).uop.cf.pc,
-        issQue(idQue(i)).uop.roqIdx
+        issQue(idQue(i)).uop.roqIdx.asUInt
       )
     }
   }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -10,19 +10,35 @@ import xiangshan.backend.LSUOpType
 import xiangshan.backend.decode.isa.Privileged.WFI
 
 
-class Roq extends XSModule {
+class RoqPtr extends CircularQueuePtr(RoqPtr.RoqSize) with HasCircularQueuePtrHelper {
+  def needFlush(redirect: Valid[Redirect]): Bool = {
+    redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe || isAfter(this, redirect.bits.roqIdx))
+  }
+}
+
+object RoqPtr extends HasXSParameter {
+  def apply(f: Bool, v: UInt): RoqPtr = {
+    val ptr = Wire(new RoqPtr)
+    ptr.flag := f
+    ptr.value := v
+    ptr
+  }
+}
+
+
+class Roq extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val brqRedirect = Input(Valid(new Redirect))
     val memRedirect = Input(Valid(new Redirect))
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
-    val roqIdxs = Output(Vec(RenameWidth, UInt(RoqIdxWidth.W)))
+    val roqIdxs = Output(Vec(RenameWidth, new RoqPtr))
     val redirect = Output(Valid(new Redirect))
     val exception = Output(new MicroOp)
     // exu + brq
     val exeWbResults = Vec(exuParameters.ExuCnt + 1, Flipped(ValidIO(new ExuOutput)))
     val commits = Vec(CommitWidth, Valid(new RoqCommit))
     val bcommit = Output(UInt(BrTagWidth.W))
-    val roqDeqPtr = Output(UInt(RoqIdxWidth.W))
+    val roqDeqPtr = Output(new RoqPtr)
   })
 
   val numWbPorts = io.exeWbResults.length
@@ -35,15 +51,15 @@ class Roq extends XSModule {
   val exuData = Reg(Vec(RoqSize, UInt(XLEN.W)))//for debug
   val exuDebug = Reg(Vec(RoqSize, new DebugBundle))//for debug
 
-  val enqPtrExt = RegInit(0.U(RoqIdxWidth.W))
-  val deqPtrExt = RegInit(0.U(RoqIdxWidth.W))
-  val walkPtrExt = Reg(UInt(RoqIdxWidth.W))
-  val walkTgtExt = Reg(UInt(RoqIdxWidth.W))
-  val enqPtr = enqPtrExt(InnerRoqIdxWidth-1,0)
-  val deqPtr = deqPtrExt(InnerRoqIdxWidth-1,0)
-  val walkPtr = walkPtrExt(InnerRoqIdxWidth-1,0)
-  val isEmpty = enqPtr === deqPtr && enqPtrExt.head(1)===deqPtrExt.head(1)
-  val isFull = enqPtr === deqPtr && enqPtrExt.head(1)=/=deqPtrExt.head(1)
+  val enqPtrExt = RegInit(0.U.asTypeOf(new RoqPtr))
+  val deqPtrExt = RegInit(0.U.asTypeOf(new RoqPtr))
+  val walkPtrExt = Reg(new RoqPtr)
+  val walkTgtExt = Reg(new RoqPtr)
+  val enqPtr = enqPtrExt.value
+  val deqPtr = deqPtrExt.value
+  val walkPtr = walkPtrExt.value
+  val isEmpty = enqPtr === deqPtr && enqPtrExt.flag ===deqPtrExt.flag
+  val isFull = enqPtr === deqPtr && enqPtrExt.flag =/= deqPtrExt.flag
   val notFull = !isFull
 
   val s_idle :: s_walk :: s_extrawalk :: Nil = Enum(3)
@@ -60,12 +76,12 @@ class Roq extends XSModule {
   for (i <- 0 until RenameWidth) {
     val offset = PopCount(validDispatch.take(i))
     val roqIdxExt = enqPtrExt + offset
-    val roqIdx = roqIdxExt.tail(1)
+    val roqIdx = roqIdxExt.value
 
     when(io.dp1Req(i).fire()){
       microOp(roqIdx) := io.dp1Req(i).bits
       valid(roqIdx) := true.B
-      flag(roqIdx) := roqIdxExt.head(1).asBool()
+      flag(roqIdx) := roqIdxExt.flag
       writebacked(roqIdx) := false.B
       when(noSpecEnq(i)){ hasNoSpec := true.B }
     }
@@ -90,7 +106,7 @@ class Roq extends XSModule {
   for(i <- 0 until numWbPorts){
     when(io.exeWbResults(i).fire()){
       val wbIdxExt = io.exeWbResults(i).bits.uop.roqIdx
-      val wbIdx = wbIdxExt.tail(1)
+      val wbIdx = wbIdxExt.value
       writebacked(wbIdx) := true.B
       microOp(wbIdx).cf.exceptionVec := io.exeWbResults(i).bits.uop.cf.exceptionVec
       microOp(wbIdx).lsroqIdx := io.exeWbResults(i).bits.uop.lsroqIdx
@@ -100,14 +116,10 @@ class Roq extends XSModule {
       exuDebug(wbIdx) := io.exeWbResults(i).bits.debug
 
       val debugUop = microOp(wbIdx)
-      XSInfo(true.B, "writebacked pc 0x%x wen %d data 0x%x ldst %d pdst %d skip %x roqIdx: %d\n",
-        debugUop.cf.pc,
-        debugUop.ctrl.rfWen,
-        io.exeWbResults(i).bits.data,
-        debugUop.ctrl.ldest,
-        io.exeWbResults(i).bits.uop.pdest,
-        io.exeWbResults(i).bits.debug.isMMIO,
-        wbIdxExt
+      XSInfo(true.B,
+        p"writebacked pc 0x${Hexadecimal(debugUop.cf.pc)} wen ${debugUop.ctrl.rfWen} " +
+        p"data 0x${Hexadecimal(io.exeWbResults(i).bits.data)} ldst ${debugUop.ctrl.ldest} pdst ${debugUop.ctrl.ldest} " +
+        p"skip ${io.exeWbResults(i).bits.debug.isMMIO} roqIdx: ${wbIdxExt}\n"
       )
     }
   }
@@ -135,7 +147,7 @@ class Roq extends XSModule {
   // Commit uop to Rename (walk)
   val shouldWalkVec = Wire(Vec(CommitWidth, Bool()))
   val walkPtrMatchVec  = Wire(Vec(CommitWidth, Bool()))
-  val walkPtrVec = Wire(Vec(CommitWidth, UInt(RoqIdxWidth.W)))
+  val walkPtrVec = Wire(Vec(CommitWidth, new RoqPtr))
   for(i <- shouldWalkVec.indices){
     walkPtrVec(i) := walkPtrExt - i.U
     walkPtrMatchVec(i) := walkPtrVec(i) === walkTgtExt
@@ -189,7 +201,7 @@ class Roq extends XSModule {
       }
 
       is(s_walk){
-        val idx = walkPtrVec(i).tail(1)
+        val idx = walkPtrVec(i).value
         val v = valid(idx)
         val walkUop = microOp(idx)
         io.commits(i).valid := v && shouldWalkVec(i)
@@ -229,7 +241,7 @@ class Roq extends XSModule {
     }
     walkPtrExt := walkPtrExt - CommitWidth.U
     // ringBufferWalkExtended := ringBufferWalkExtended - validCommit
-    XSInfo("rolling back: enqPtr %d deqPtr %d walk %d:%d\n", enqPtr, deqPtr, walkPtrExt.head(1), walkPtr)
+    XSInfo("rolling back: enqPtr %d deqPtr %d walk %d:%d\n", enqPtr, deqPtr, walkPtrExt.flag, walkPtr)
   }
 
   // move tail ptr
@@ -265,9 +277,8 @@ class Roq extends XSModule {
   // when rollback, reset writebacked entry to valid
   when(io.memRedirect.valid) { // TODO: opt timing
     for (i <- 0 until RoqSize) {
-      val recRoqIdx = Wire(new XSBundle with HasRoqIdx)
-      recRoqIdx.roqIdx := Cat(flag(i).asUInt, i.U((RoqIdxWidth - 1).W))
-      when (valid(i) && recRoqIdx.isAfter(io.memRedirect.bits)) {
+      val recRoqIdx = RoqPtr(flag(i), i.U)
+      when (valid(i) && isAfter(recRoqIdx, io.memRedirect.bits.roqIdx)) {
         writebacked(i) := false.B
       }
     }
@@ -275,15 +286,15 @@ class Roq extends XSModule {
 
   // when exception occurs, cancels all
   when (io.redirect.valid) { // TODO: need check for flushPipe
-    enqPtrExt := 0.U
-    deqPtrExt := 0.U
+    enqPtrExt := 0.U.asTypeOf(new RoqPtr)
+    deqPtrExt := 0.U.asTypeOf(new RoqPtr)
     for (i <- 0 until RoqSize) {
       valid(i) := false.B
     }
   }
 
   // debug info
-  XSDebug("enqPtr %d:%d deqPtr %d:%d\n", enqPtrExt.head(1), enqPtr, deqPtrExt.head(1), deqPtr)
+  XSDebug(p"enqPtr ${enqPtrExt} deqPtr ${deqPtrExt}\n")
   XSDebug("")
   for(i <- 0 until RoqSize){
     XSDebug(false, !valid(i), "-")

src/main/scala/xiangshan/cache/dtlb.scala

@@ -6,6 +6,7 @@ import xiangshan._
 import utils._
 import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.decode.XSTrap
+import xiangshan.backend.roq.RoqPtr
 import xiangshan.mem._
 import bus.simplebus._
 import xiangshan.backend.fu.HasCSRConst
@@ -62,11 +63,12 @@ class PermBundle(val hasV: Boolean = true) extends TlbBundle {
   }
 }
 
-class comBundle extends TlbBundle with HasRoqIdx{
+class comBundle extends TlbBundle with HasCircularQueuePtrHelper{
+  val roqIdx = new RoqPtr
   val valid = Bool()
   val bits = new PtwReq
   def isPrior(that: comBundle): Bool = {
-    (this.valid && !that.valid) || (this.valid && that.valid && (that isAfter this))
+    (this.valid && !that.valid) || (this.valid && that.valid && isAfter(that.roqIdx, this.roqIdx))
   }
 }
 object Compare {
@@ -128,7 +130,7 @@ object TlbCmd {
 class TlbReq extends TlbBundle {
   val vaddr = UInt(VAddrBits.W)
   val cmd = TlbCmd()
-  val roqIdx = UInt(RoqIdxWidth.W)
+  val roqIdx = new RoqPtr
   val debug = new Bundle {
     val pc = UInt(XLEN.W)
     val lsroqIdx = UInt(LsroqIdxWidth.W)

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -70,7 +70,7 @@ class LoadUnit extends XSModule {
   l2_out.bits.uop   := io.ldin.bits.uop
   l2_out.bits.miss  := false.B
   l2_out.bits.mmio  := l2_mmio
-  l2_out.valid := io.ldin.valid && !io.ldin.bits.uop.needFlush(io.redirect)
+  l2_out.valid := io.ldin.valid && !io.ldin.bits.uop.roqIdx.needFlush(io.redirect)
   // when we are sure it's a MMIO req, we do not need to wait for cache ready
   l2_out.ready := (l2_dcache && io.dcache.req.ready) || l2_mmio || l2_dtlb_miss
   io.ldin.ready := l2_out.ready
@@ -132,11 +132,11 @@ class LoadUnit extends XSModule {
   val l3_bundle = RegEnable(next = l2_out.bits, enable = l2_out.fire())
   val l3_uop = l3_bundle.uop
   // dltb miss reqs ends here
-  val l3_passdown = l3_valid && !l3_dtlb_miss && !l3_uop.needFlush(io.redirect)
+  val l3_passdown = l3_valid && !l3_dtlb_miss && !l3_uop.roqIdx.needFlush(io.redirect)
 
   io.tlbFeedback.valid := l3_valid
   io.tlbFeedback.bits := l3_tlbFeedback
-  io.dcache.s1_kill := l3_valid && l3_dcache && l3_uop.needFlush(io.redirect)
+  io.dcache.s1_kill := l3_valid && l3_dcache && l3_uop.roqIdx.needFlush(io.redirect)
 
   // dump l3
   XSDebug(l3_valid, "l3: pc 0x%x addr 0x%x -> 0x%x op %b data 0x%x mask %x dltb_miss %b dcache %b mmio %b\n",
@@ -145,7 +145,7 @@ class LoadUnit extends XSModule {
     l3_dtlb_miss, l3_dcache, l3_bundle.mmio)
 
   XSDebug(io.tlbFeedback.valid, "tlbFeedback: hit %b roqIdx %d\n",
-    io.tlbFeedback.bits.hit, io.tlbFeedback.bits.roqIdx)
+    io.tlbFeedback.bits.hit, io.tlbFeedback.bits.roqIdx.asUInt)
 
   XSDebug(io.dcache.s1_kill, "l3: dcache s1_kill\n")
 
@@ -180,7 +180,7 @@ class LoadUnit extends XSModule {
   } .otherwise {
     l4_out.bits := l4_bundle
   }
-  l4_out.valid := l4_valid && !l4_out.bits.uop.needFlush(io.redirect)
+  l4_out.valid := l4_valid && !l4_out.bits.uop.roqIdx.needFlush(io.redirect)
 
   // Store addr forward match
   // If match, get data / fmask from store queue / store buffer
@@ -230,7 +230,12 @@ class LoadUnit extends XSModule {
   XSDebug(l4_valid, "l4: lsroq forwardData: 0x%x forwardMask: %x\n",
     io.lsroq.forward.forwardData.asUInt, io.lsroq.forward.forwardMask.asUInt)
 
-  XSDebug(io.redirect.valid, p"Redirect: excp:${io.redirect.bits.isException} flushPipe:${io.redirect.bits.isFlushPipe} misp:${io.redirect.bits.isMisPred} replay:${io.redirect.bits.isReplay} pc:0x${Hexadecimal(io.redirect.bits.pc)} target:0x${Hexadecimal(io.redirect.bits.target)} brTag:${io.redirect.bits.brTag} l2:${io.ldin.bits.uop.needFlush(io.redirect)} l3:${l3_uop.needFlush(io.redirect)} l4:${l4_out.bits.uop.needFlush(io.redirect)}\n")
+  XSDebug(io.redirect.valid,
+    p"Redirect: excp:${io.redirect.bits.isException} flushPipe:${io.redirect.bits.isFlushPipe} misp:${io.redirect.bits.isMisPred} " +
+    p"replay:${io.redirect.bits.isReplay} pc:0x${Hexadecimal(io.redirect.bits.pc)} target:0x${Hexadecimal(io.redirect.bits.target)} " +
+    p"brTag:${io.redirect.bits.brTag} l2:${io.ldin.bits.uop.roqIdx.needFlush(io.redirect)} l3:${l3_uop.roqIdx.needFlush(io.redirect)} " +
+    p"l4:${l4_out.bits.uop.roqIdx.needFlush(io.redirect)}\n"
+  )
   //-------------------------------------------------------
   // LD Pipeline Stage 5
   // Do data ecc check, merge result and write back to LS ROQ

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -7,6 +7,7 @@ import xiangshan._
 import xiangshan.cache._
 import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants}
 import xiangshan.backend.LSUOpType
+import xiangshan.backend.roq.RoqPtr
 
 class LsRoqEntry extends XSBundle {
   val vaddr = UInt(VAddrBits.W) // TODO: need opt
@@ -27,7 +28,7 @@ class InflightBlockInfo extends XSBundle {
 }
 
 // Load/Store Roq (Lsroq) for XiangShan Out of Order LSU
-class Lsroq extends XSModule with HasDCacheParameters {
+class Lsroq extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper{
   val io = IO(new Bundle() {
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
     val lsroqIdxs = Output(Vec(RenameWidth, UInt(LsroqIdxWidth.W)))
@@ -42,7 +43,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
     val rollback = Output(Valid(new Redirect))
     val dcache = new DCacheLineIO
     val uncache = new DCacheWordIO
-    val roqDeqPtr = Input(UInt(RoqIdxWidth.W))
+    val roqDeqPtr = Input(new RoqPtr)
     // val refill = Flipped(Valid(new DCacheLineReq ))
   })
   
@@ -244,11 +245,17 @@ class Lsroq extends XSModule with HasDCacheParameters {
 
 
   when(io.dcache.req.fire()){
-    XSDebug("miss req: pc:0x%x roqIdx:%d lsroqIdx:%d (p)addr:0x%x vaddr:0x%x\n", io.dcache.req.bits.meta.uop.cf.pc, io.dcache.req.bits.meta.uop.roqIdx, io.dcache.req.bits.meta.uop.lsroqIdx, io.dcache.req.bits.addr, io.dcache.req.bits.meta.vaddr) 
+    XSDebug("miss req: pc:0x%x roqIdx:%d lsroqIdx:%d (p)addr:0x%x vaddr:0x%x\n",
+      io.dcache.req.bits.meta.uop.cf.pc, io.dcache.req.bits.meta.uop.roqIdx.asUInt, io.dcache.req.bits.meta.uop.lsroqIdx,
+      io.dcache.req.bits.addr, io.dcache.req.bits.meta.vaddr
+    )
   }
 
   when(io.dcache.resp.fire()){
-    XSDebug("miss resp: pc:0x%x roqIdx:%d lsroqIdx:%d (p)addr:0x%x data %x\n", io.dcache.resp.bits.meta.uop.cf.pc, io.dcache.resp.bits.meta.uop.roqIdx, io.dcache.resp.bits.meta.uop.lsroqIdx, io.dcache.resp.bits.meta.paddr, io.dcache.resp.bits.data) 
+    XSDebug("miss resp: pc:0x%x roqIdx:%d lsroqIdx:%d (p)addr:0x%x data %x\n",
+      io.dcache.resp.bits.meta.uop.cf.pc, io.dcache.resp.bits.meta.uop.roqIdx.asUInt, io.dcache.resp.bits.meta.uop.lsroqIdx,
+      io.dcache.resp.bits.meta.paddr, io.dcache.resp.bits.data
+    )
   }
 
   // Refill 64 bit in a cycle
@@ -510,7 +517,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
     assert(valid.length == uop.length)
     assert(valid.length == 2)
     Mux(valid(0) && valid(1),
-      Mux(uop(0).isAfter(uop(1)), uop(1), uop(0)),
+      Mux(isAfter(uop(0).roqIdx, uop(1).roqIdx), uop(1), uop(0)),
       Mux(valid(0) && !valid(1), uop(0), uop(1)))
   }
 
@@ -520,7 +527,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
     (0 until length).map(i => {
       (0 until length).map(j => {
         Mux(valid(i) && valid(j),
-          uop(i).isAfter(uop(j)),
+          isAfter(uop(i).roqIdx, uop(j).roqIdx),
           Mux(!valid(i), true.B, false.B))
       })
     })
@@ -560,7 +567,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
       // when l/s writeback to roq together, check if rollback is needed
       val wbViolationVec = VecInit((0 until LoadPipelineWidth).map(j => {
         io.loadIn(j).valid &&
-          io.loadIn(j).bits.uop.isAfter(io.storeIn(i).bits.uop) &&
+          isAfter(io.loadIn(j).bits.uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) &&
           io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.loadIn(j).bits.paddr(PAddrBits - 1, 3) &&
           (io.storeIn(i).bits.mask & io.loadIn(j).bits.mask).orR
       }))
@@ -571,7 +578,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
       // check if rollback is needed for load in l4
       val l4ViolationVec = VecInit((0 until LoadPipelineWidth).map(j => {
         io.forward(j).valid && // L4 valid\
-          io.forward(j).uop.isAfter(io.storeIn(i).bits.uop) &&
+          isAfter(io.forward(j).uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) &&
           io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.forward(j).paddr(PAddrBits - 1, 3) &&
           (io.storeIn(i).bits.mask & io.forward(j).mask).orR
       }))
@@ -596,17 +603,17 @@ class Lsroq extends XSModule with HasDCacheParameters {
       XSDebug(
         lsroqViolation,
         "need rollback (ld wb before store) pc %x roqidx %d target %x\n",
-        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx, lsroqViolationUop.roqIdx
+        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, lsroqViolationUop.roqIdx.asUInt
       )
       XSDebug(
         wbViolation,
         "need rollback (ld/st wb together) pc %x roqidx %d target %x\n",
-        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx, wbViolationUop.roqIdx
+        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, wbViolationUop.roqIdx.asUInt
       )
       XSDebug(
         l4Violation,
         "need rollback (l4 load) pc %x roqidx %d target %x\n",
-        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx, l4ViolationUop.roqIdx
+        io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, l4ViolationUop.roqIdx.asUInt
       )
     }.otherwise {
       rollback(i).valid := false.B
@@ -618,7 +625,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
       a.valid,
       Mux(
         b.valid,
-        Mux(a.bits.isAfter(b.bits), b, a), // a,b both valid, sel oldest
+        Mux(isAfter(a.bits.roqIdx, b.bits.roqIdx), b, a), // a,b both valid, sel oldest
         a // sel a
       ),
       b // sel b
@@ -688,7 +695,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
   // invalidate lsroq term using robIdx
   val needCancel = Wire(Vec(LsroqSize, Bool()))
   for (i <- 0 until LsroqSize) {
-    needCancel(i) := uop(i).needFlush(io.brqRedirect) && allocated(i) && !commited(i)
+    needCancel(i) := uop(i).roqIdx.needFlush(io.brqRedirect) && allocated(i) && !commited(i)
     when(needCancel(i)) {
       when(io.brqRedirect.bits.isReplay){
         valid(i) := false.B
@@ -708,7 +715,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
 
   // assert(!io.rollback.valid)
   when(io.rollback.valid) {
-    XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx)
+    XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx.asUInt)
   }
 
   // debug info

src/main/scala/xiangshan/mem/Memend.scala

@@ -6,6 +6,7 @@ import chisel3.util.experimental.BoringUtils
 import xiangshan._
 import utils._
 import chisel3.util.experimental.BoringUtils
+import xiangshan.backend.roq.RoqPtr
 
 import xiangshan.cache._
 import bus.tilelink.{TLArbiter, TLCached, TLMasterUtilities, TLParameters}
@@ -73,7 +74,7 @@ class MemToBackendIO extends XSBundle {
   val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
   val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
   val lsroqIdxs = Output(Vec(RenameWidth, UInt(LsroqIdxWidth.W)))
-  val roqDeqPtr = Input(UInt(RoqIdxWidth.W))
+  val roqDeqPtr = Input(new RoqPtr)
 }
 
 class Memend extends XSModule {

src/main/scala/xiangshan/mem/StoreUnit.scala

@@ -67,7 +67,7 @@ class StoreUnit extends XSModule {
   s2_out.bits.uop := io.stin.bits.uop
   s2_out.bits.miss := io.dtlb.resp.bits.miss
   s2_out.bits.mask := genWmask(s2_out.bits.vaddr, io.stin.bits.uop.ctrl.fuOpType(1,0))
-  s2_out.valid := io.stin.valid && !io.dtlb.resp.bits.miss && !s2_out.bits.uop.needFlush(io.redirect)
+  s2_out.valid := io.stin.valid && !io.dtlb.resp.bits.miss && !s2_out.bits.uop.roqIdx.needFlush(io.redirect)
   io.stin.ready := s2_out.ready
 
   // exception check
@@ -93,7 +93,7 @@ class StoreUnit extends XSModule {
   XSDebug(io.tlbFeedback.valid, 
     "S3 Store: tlbHit: %d roqIdx: %d\n",
     io.tlbFeedback.bits.hit,
-    io.tlbFeedback.bits.roqIdx
+    io.tlbFeedback.bits.roqIdx.asUInt
   )
 
   // get paddr from dtlb, check if rollback is needed