[WIP] Lsroq: fix MMIO's bug

src/main/scala/xiangshan/backend/Backend.scala

@@ -171,6 +171,7 @@ class Backend extends XSModule
     })
 
   io.mem.commits <> roq.io.commits
+  io.mem.roqDeqPtr := roq.io.roqDeqPtr
   io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
   io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
   jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -71,7 +71,6 @@ class Dispatch1 extends XSModule {
     io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i)
     io.toRoq(i).bits := io.fromRename(i).bits
     io.toRoq(i).bits.ctrl.commitType := Cat(isLs(i), isStore(i) | isFp(i)) // TODO: add it to decode
-    io.toRoq(i).bits.lsroqIdx := Mux(lsroqIndexRegValid(i), lsroqIndexReg(i), io.lsroqIdx(i))
 
     io.toLsroq(i).valid := io.fromRename(i).valid && !lsroqIndexRegValid(i) && isLs(i) && io.fromRename(i).bits.ctrl.fuType =/= FuType.mou && roqIndexAcquired(i) && !cancelled(i)
     io.toLsroq(i).bits := io.fromRename(i).bits

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -22,6 +22,7 @@ class Roq extends XSModule {
     val exeWbResults = Vec(exuParameters.ExuCnt + 1, Flipped(ValidIO(new ExuOutput)))
     val commits = Vec(CommitWidth, Valid(new RoqCommit))
     val bcommit = Output(UInt(BrTagWidth.W))
+    val roqDeqPtr = Output(UInt(RoqIdxWidth.W))
   })
 
   val numWbPorts = io.exeWbResults.length
@@ -48,6 +49,8 @@ class Roq extends XSModule {
   val s_idle :: s_walk :: s_extrawalk :: Nil = Enum(3)
   val state = RegInit(s_idle)
 
+  io.roqDeqPtr := deqPtrExt
+
   // Dispatch
   val noSpecEnq = io.dp1Req.map(i => i.bits.ctrl.noSpecExec)
   val hasNoSpec = RegInit(false.B)

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -42,6 +42,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
     val rollback = Output(Valid(new Redirect))
     val dcache = new DCacheLineIO
     val uncache = new DCacheWordIO
+    val roqDeqPtr = Input(UInt(RoqIdxWidth.W))
     // val refill = Flipped(Valid(new DCacheLineReq ))
   })
   
@@ -631,7 +632,7 @@ class Lsroq extends XSModule with HasDCacheParameters {
   val commitType = io.commits(0).bits.uop.ctrl.commitType 
   io.uncache.req.valid := pending(ringBufferTail) && allocated(ringBufferTail) &&
     (commitType === CommitType.STORE || commitType === CommitType.LOAD) && 
-    io.commits(0).bits.uop.lsroqIdx === ringBufferTailExtended && 
+    io.roqDeqPtr === uop(ringBufferTail).roqIdx && 
     !io.commits(0).bits.isWalk
 
   io.uncache.req.bits.cmd  := Mux(store(ringBufferTail), MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD)

src/main/scala/xiangshan/mem/Memend.scala

@@ -73,6 +73,7 @@ class MemToBackendIO extends XSBundle {
   val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
   val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
   val lsroqIdxs = Output(Vec(RenameWidth, UInt(LsroqIdxWidth.W)))
+  val roqDeqPtr = Input(UInt(RoqIdxWidth.W))
 }
 
 class Memend extends XSModule {
@@ -139,6 +140,7 @@ class Memend extends XSModule {
   lsroq.io.dp1Req      <> io.backend.dp1Req
   lsroq.io.lsroqIdxs   <> io.backend.lsroqIdxs
   lsroq.io.brqRedirect := io.backend.redirect
+  lsroq.io.roqDeqPtr := io.backend.roqDeqPtr
   io.backend.replayAll <> lsroq.io.rollback
 
   lsroq.io.dcache      <> io.loadMiss