Difftest: lr_valid sync now have stricter requirement

* lr_valid will be copied from processor to emulator when:
    * sc falied &&
    * processor's lr_valid is set to false &&
    * emulator's lr_valid is set to true

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -328,6 +328,11 @@ class Roq extends XSModule {
     trapVec(i) := io.commits(i).valid && (state===s_idle) && uop.ctrl.isXSTrap
     isRVC(i) := uop.cf.brUpdate.pd.isRVC
   }
+
+  val scFailed = !diffTestDebugLrScValid(0) && 
+    io.commits(0).bits.uop.ctrl.fuType === FuType.mou &&
+    (io.commits(0).bits.uop.ctrl.fuOpType === LSUOpType.sc_d || io.commits(0).bits.uop.ctrl.fuOpType === LSUOpType.sc_w)
+
   val instrCnt = RegInit(0.U(64.W))
   instrCnt := instrCnt + retireCounter
 
@@ -348,7 +353,7 @@ class Roq extends XSModule {
     BoringUtils.addSource(RegNext(wpc), "difftestWpc")
     BoringUtils.addSource(RegNext(wdata), "difftestWdata")
     BoringUtils.addSource(RegNext(wdst), "difftestWdst")
-    BoringUtils.addSource(RegNext(diffTestDebugLrScValid).asUInt, "difftestLrscValid")
+    BoringUtils.addSource(RegNext(scFailed), "difftestScFailed")
     BoringUtils.addSource(RegNext(difftestIntrNO), "difftestIntrNO")
 
     val hitTrap = trapVec.reduce(_||_)

src/main/scala/xiangshan/cache/atomics.scala

@@ -122,7 +122,7 @@ class AtomicsPipe extends DCacheModule
   val s2_sc_fail = s2_sc && !s2_lrsc_addr_match
   val s2_sc_resp = Mux(s2_sc_fail, 1.U, 0.U)
 
-  BoringUtils.addSource(RegEnable(lrsc_addr, s2_valid), "difftestLrscAddr")
+  // BoringUtils.addSource(RegEnable(lrsc_addr, s2_valid && s2_lr), "difftestLrscAddr")
 
   // we have permission on this block
   // but we can not finish in this pass

src/test/csrc/difftest.cpp

@@ -145,6 +145,15 @@ int difftest_step(DiffState *s) {
   //   return 0;
   // }
 
+  // sync lr/sc reg status
+  if(s->sync.scFailed){
+    struct SyncState {
+      uint64_t lrscValid; // sc inst commited, it failed beacuse lr_valid === 0
+      uint64_t lrscAddr;
+    } sync;
+    sync.lrscValid = 0;
+    ref_difftest_sync((uint64_t*)&sync); // sync lr/sc microarchitectural regs
+  }
 
   // single step difftest
   if (s->intrNO) {
@@ -172,11 +181,6 @@ int difftest_step(DiffState *s) {
         }
         ref_difftest_setregs(ref_r);
       }else{
-        // sync lr/sc reg status
-        struct SyncState sync;
-        sync.lrscValid = selectBit(s->sync.lrscValid, i);
-        sync.lrscAddr = s->sync.lrscAddr;
-        ref_difftest_sync((uint64_t*)&sync); // sync lr/sc microarchitectural regs
         // single step exec
         ref_difftest_exec(1);
       }

src/test/csrc/difftest.h

@@ -36,9 +36,9 @@ enum {
 // DIFFTEST_MTVAL, DIFFTEST_STVAL will be updated while committing exception
 // Compare / snapshot them is not necessary
 
-struct SyncState {
-  uint64_t lrscValid;
-  uint64_t lrscAddr;
+struct SyncChannel {
+  uint64_t scFailed; // sc inst commited, it failed beacuse lr_valid === 0
+  // uint64_t lrscAddr;
 };
 
 struct DiffState {
@@ -56,7 +56,7 @@ struct DiffState {
   int priviledgeMode;
 
   // Microarchitucural signal needed to sync status
-  struct SyncState sync;
+  struct SyncChannel sync;
   // lrscValid needs to be synced as nemu does not know 
   // how many cycles were used to finish a lr/sc pair, 
   // this will lead to different sc results.

src/test/csrc/emu.cpp

@@ -252,8 +252,7 @@ uint64_t Emulator::execute(uint64_t n) {
       diff.intrNO = dut_ptr->io_difftest_intrNO;
       diff.priviledgeMode = dut_ptr->io_difftest_priviledgeMode;
 
-      diff.sync.lrscValid = dut_ptr->io_difftest_lrscValid;
-      diff.sync.lrscAddr = dut_ptr->io_difftest_lrscAddr;
+      diff.sync.scFailed = dut_ptr->io_difftest_scFailed;
 
       if (difftest_step(&diff)) {
         trapCode = STATE_ABORT;

src/test/scala/top/XSSim.scala

@@ -44,8 +44,8 @@ class DiffTestIO extends XSBundle {
   val mideleg = Output(UInt(64.W))
   val medeleg = Output(UInt(64.W))
 
-  val lrscValid = Output(UInt(32.W))
-  val lrscAddr = Output(UInt(64.W))
+  val scFailed = Output(Bool())
+  // val lrscAddr = Output(UInt(64.W))
 }
 
 class LogCtrlIO extends Bundle {
@@ -123,8 +123,8 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
     BoringUtils.addSink(difftest.sscratch, "difftestSscratch")
     BoringUtils.addSink(difftest.mideleg, "difftestMideleg")
     BoringUtils.addSink(difftest.medeleg, "difftestMedeleg")
-    BoringUtils.addSink(difftest.lrscValid, "difftestLrscValid")
-    BoringUtils.addSink(difftest.lrscAddr, "difftestLrscAddr")
+    BoringUtils.addSink(difftest.scFailed, "difftestScFailed")
+    // BoringUtils.addSink(difftest.lrscAddr, "difftestLrscAddr")
     io.difftest := difftest
 
     val trap = WireInit(0.U.asTypeOf(new TrapIO))