[WIP] Lsroq: add temp l/s redispatch logic

src/main/scala/xiangshan/backend/package.scala

@@ -121,6 +121,9 @@ package object backend {
     def sw   = "b001010".U
     def sd   = "b001011".U
 
+    def isLoad(op: UInt): Bool = !op(3)
+    def isStore(op: UInt): Bool = op(3)
+
     // float/double load store
     def flw  = "b010110".U
 

src/main/scala/xiangshan/mem/LSQWrapper.scala

@@ -33,6 +33,20 @@ class LsqWrappper extends XSModule with HasDCacheParameters with NeedImpl {
   val loadQueue = Module(new LoadQueue)
   val storeQueue = Module(new StoreQueue)
 
+  // reorg dp1Req
+  // Note: it is only a behavior level model, refactor needed
+  // TODO: FIXME
+  val dp1LdReq = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
+  val dp1StReq = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
+  var ldPtr = WireInit(0.U)
+  var stPtr = WireInit(0.U)
+  (0 until RenameWidth).map(i => {
+    dp1LdReq(i) <> dp1Req(ldPtr)
+    dp1StReq(i) <> dp1Req(stPtr)
+    ldPtr = ldPtr +& dp1Req(i).valid && LSUOpType.isLoad(dp1Req(i).bits.ctrl.fuOpType)
+    stPtr = stPtr +& dp1Req(i).valid && LSUOpType.isStore(dp1Req(i).bits.ctrl.fuOpType)
+  })
+
   // load queue wiring
   loadQueue.io.dp1Req <> io.dp1Req
   loadQueue.io.brqRedirect <> io.brqRedirect