We use single port SRAM, read and write in the same cycle is not
allowed.

Now DCache has several configurable parameters:
1. nSets
2. nWays
3. blockByte(size block in bytes)
4. rowBits(basic storage unit of cache, the width of a signal sram bank)
5. wordBits(inner cpu bus width) = DataBits = XLEN = 64
6. beatBits(outer tilelink bus width) = l1BusDataWidth = 256

Now, we require beatBits >= rowBits >= wordBits.

Also, we use ErrGen to help testing our implementation.

Now, it can only do normal load.
It will replay req on cache miss.
Enough for dtlb ptw.

to a fully functional IOMSHR.
Now, it should support multiple outstanding IO requests.
There still exists one problem: will IO tilelink share path with memory
tilelink? If so, their transaction id will collide.

may be the last commit of the branch
wait for new memend with new cache in new soc

DCacheTest will use the higher 32bit as revision id
(to make load store order violation flush easier).

We will use them for synchronization later.
Also, we add get_idx/tag/block_addr/beat stuff.
So next time, use these functions instead of manually manipulating bits.

Now, bugs are caused by contention on meta array read/write.
I will stop debugging this pipeline and start refactoring it.

Added some debug logs.

You can pass in a dump function, and it will be executed when Log
triggers and prefix is automatically appended.

Revised the core pipeline.

Just compiles.