Mem: enable new mem pipeline

src/main/scala/xiangshan/mem/MemPipeline.scala

@@ -38,29 +38,31 @@ class Memend(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   })
 
 
-  io <> DontCare
+  // io <> DontCare
 
-//  val lsu = Module(new Lsu)
-//  val dcache = Module(new Dcache)
-//  // val mshq = Module(new MSHQ)
-//  val dtlb = Module(new Dtlb)
-//
-//  dcache.io := DontCare
-//  dtlb.io := DontCare
-//  // mshq.io := DontCare
-//
-//  lsu.io.ldin <> io.backend.ldin
-//  lsu.io.stin <> io.backend.stin
-//  lsu.io.out <> io.backend.out
-//  lsu.io.redirect <> io.backend.redirect
-//  lsu.io.rollback <> io.backend.rollback
-//  lsu.io.mcommit <> io.backend.mcommit
-//  lsu.io.dp1Req <> io.backend.dp1Req
-//  lsu.io.moqIdxs <> io.backend.moqIdxs
-//  lsu.io.dcache <> dcache.io.lsu
-//  lsu.io.dtlb <> dtlb.io.lsu
-//
-//  // for ls pipeline test
-//  dcache.io.dmem <> io.dmem
+ val lsu = Module(new Lsu)
+  val dcache = Module(new Dcache)
+  // val mshq = Module(new MSHQ)
+  val dtlb = Module(new Dtlb)
 
+  dcache.io := DontCare
+  dtlb.io := DontCare
+  // mshq.io := DontCare
+
+  lsu.io.ldin <> io.backend.ldin
+  lsu.io.stin <> io.backend.stin
+  lsu.io.ldout <> io.backend.ldout
+  lsu.io.stout <> io.backend.stout
+  lsu.io.redirect <> io.backend.redirect
+  lsu.io.rollback <> io.backend.rollback
+  lsu.io.mcommit <> io.backend.mcommit
+  lsu.io.dp1Req <> io.backend.dp1Req
+  lsu.io.moqIdxs <> io.backend.moqIdxs
+  lsu.io.dcache <> dcache.io.lsu
+  lsu.io.dtlb <> dtlb.io.lsu
+  
+  //  // for ls pipeline test
+  dcache.io.dmem <> io.dmem
+  dcache.io.lsu.refill <> DontCare
+  
 }
\ No newline at end of file

src/main/scala/xiangshan/mem/cache/dcache.scala

@@ -97,6 +97,7 @@ class Dcache extends XSModule {
 
   // NutShell cache
   assert(!io.lsu.load(1).req.valid)
+  io.lsu.refill <> DontCare
   io.lsu.load(1).resp := DontCare
   io.lsu.load(1).resp.valid := false.B
   io.lsu.load(1).req.ready := false.B

src/main/scala/xiangshan/mem/pipeline/Lsroq.scala

@@ -19,12 +19,12 @@ class LsRoqEntry extends XSBundle {
   val miss = Bool()
   val mmio = Bool()
   val store = Bool()
-  val bwdMask = UInt(8.W)
-  val bwdData = UInt(XLEN.W)
+  val bwdMask = Vec(8, Bool()) // UInt(8.W)
+  val bwdData = Vec(8, UInt(8.W))
 }
 
 // Load/Store Roq (Moq) for XiangShan Out of Order LSU
-class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
+class Lsroq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   val io = IO(new Bundle() {
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
     val moqIdxs = Output(Vec(RenameWidth, UInt(MoqIdxWidth.W)))
@@ -32,7 +32,8 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
     val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle)))
     val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle)))
     val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheStoreReq))
-    val out = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
+    val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
+    val stout = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
     val mcommit = Input(UInt(3.W))
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
     val rollback = Output(Valid(new Redirect))
@@ -66,7 +67,7 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
       valid(ringBufferHead+offset) := false.B
       writebacked(ringBufferHead+offset) := false.B
       store(ringBufferHead+offset) := false.B
-      data(ringBufferHead+offset).bwdMask := 0.U
+      data(ringBufferHead+offset).bwdMask := 0.U(8.W).asBools
     }
     io.dp1Req(i).ready := ringBufferAllowin && !allocated(ringBufferHead+offset)
     io.moqIdxs(i) := ringBufferHeadExtended+offset
@@ -167,20 +168,21 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   storeWbSel(1) := OHToUInt(selvec1.asUInt)
 
   (0 until StorePipelineWidth).map(i => {
-    io.out(i).bits.uop := uop(storeWbSel(i))
-    io.out(i).bits.data := data(storeWbSel(i)).data
-    io.out(i).bits.redirectValid := false.B
-    io.out(i).bits.redirect := DontCare
-    io.out(i).bits.debug.isMMIO := data(storeWbSel(i)).mmio
+    io.stout(i).bits.uop := uop(storeWbSel(i))
+    io.stout(i).bits.data := data(storeWbSel(i)).data
+    io.stout(i).bits.redirectValid := false.B
+    io.stout(i).bits.redirect := DontCare
+    io.stout(i).bits.debug.isMMIO := data(storeWbSel(i)).mmio
     when(storeWbSelVec(storeWbSel(i))){
       writebacked(storeWbSel(i)) := true.B
     }
-    io.out(i).valid := storeWbSelVec(storeWbSel(i))
+    io.stout(i).valid := storeWbSelVec(storeWbSel(i))
   })
 
   // cache miss request
   // TODO
-  // io.miss := DontCare
+  io.miss.valid := false.B
+  io.miss := DontCare
   // val missRefillSelVec = VecInit(
   //   (0 until MoqSize).map(i => allocated(i) && valid(i) && miss(i))
   // )
@@ -196,8 +198,12 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   // get load result from refill resp
   // TODO
 
-  // writeback up to 2 missed load / store insts
+  // writeback up to 2 missed load insts to CDB
   // TODO
+  (0 until 2).map(i => {
+    io.ldout(i) <> DontCare
+    io.ldout(i).valid := false.B
+  })
 
   // remove retired insts from lsroq, add retired store to sbuffer
   val scommitCnt = RegInit(0.U(log2Up(MoqSize).W))
@@ -295,7 +301,7 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
     (0 until 8).map(k => {
       when(data(io.forward(i).moqIdx).bwdMask(k)){
         io.forward(i).forwardMask(k) := true.B
-        io.forward(i).forwardData(k) := data(io.forward(i).moqIdx).bwdData(8*(k+1)-1, 8*k)
+        io.forward(i).forwardData(k) := data(io.forward(i).moqIdx).bwdData(k)
         XSDebug("backwarding "+k+"th byte %x\n", io.forward(i).forwardData(k))
       }
     })
@@ -322,8 +328,8 @@ class LsRoq(implicit val p: XSConfig) extends XSModule with HasMEMConst {
               rollback(i).bits.roqIdx := io.storeIn(i).bits.uop.roqIdx
               rollback(i).bits.target := io.storeIn(i).bits.uop.cf.pc
             }.otherwise{
-              data(j).bwdMask(k) := 1.U
-              data(j).bwdData(8*(k+1)-1, 8*k) := io.storeIn(i).bits.data(8*(k+1)-1, 8*k)
+              data(j).bwdMask(k) := true.B
+              data(j).bwdData(k) := io.storeIn(i).bits.data(8*(k+1)-1, 8*k)
               XSDebug("write backward data: ptr %x byte %x data %x\n", ptr, k.U, io.storeIn(i).bits.data(8*(k+1)-1, 8*k))
             } 
           }

src/main/scala/xiangshan/mem/pipeline/Lsu.scala

@@ -73,7 +73,8 @@ class LoadForwardQueryIO extends XSBundle with HasMEMConst {
 class LsuIO extends XSBundle with HasMEMConst {
   val ldin = Vec(2, Flipped(Decoupled(new ExuInput)))
   val stin = Vec(2, Flipped(Decoupled(new ExuInput)))
-  val out = Vec(4, Decoupled(new ExuOutput))
+  val ldout = Vec(2, Decoupled(new ExuOutput))
+  val stout = Vec(2, Decoupled(new ExuOutput))
   val redirect = Flipped(ValidIO(new Redirect))
   val rollback = Output(Valid(new Redirect))
   val mcommit = Input(UInt(3.W))
@@ -88,7 +89,9 @@ class Lsu(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   override def toString: String = "Ldu"
   val io = IO(new LsuIO)
 
-  val lsroq = Module(new LsRoq)
+  io.dcache.refill <> DontCare
+
+  val lsroq = Module(new Lsroq)
   val sbuffer = Module(new FakeSbuffer)
 
   lsroq.io.mcommit <> io.mcommit
@@ -219,7 +222,7 @@ class Lsu(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   })
   
   (0 until LoadPipelineWidth).map(i => {
-    PipelineConnect(l4_out(i), l5_in(i), io.out(i).fire(), l5_in(i).bits.uop.brTag.needFlush(io.redirect))
+    PipelineConnect(l4_out(i), l5_in(i), io.ldout(i).fire(), l5_in(i).bits.uop.brTag.needFlush(io.redirect))
   })
 
 //-------------------------------------------------------
@@ -270,7 +273,7 @@ class Lsu(implicit val p: XSConfig) extends XSModule with HasMEMConst {
     loadOut(i).bits.redirectValid := false.B
     loadOut(i).bits.redirect := DontCare
     loadOut(i).bits.debug.isMMIO := l5_in(i).bits.mmio
-    loadOut(i).valid := loadWriteBack(i)
+    loadOut(i).valid := l5_in(i).valid
     XSDebug(loadOut(i).fire(), "load writeback: pc %x data %x (%x + %x(%b))\n", 
       loadOut(i).bits.uop.cf.pc, rdataPartialLoad, l5_in(i).bits.data, 
       l5_in(i).bits.forwardData.asUInt, l5_in(i).bits.forwardMask.asUInt
@@ -283,7 +286,10 @@ class Lsu(implicit val p: XSConfig) extends XSModule with HasMEMConst {
     lsroq.io.loadIn(i).valid := loadWriteBack(i)
 
     // pipeline control
-    l5_in(i).ready := io.out(i).ready
+    l5_in(i).ready := io.ldout(i).ready
+
+    lsroq.io.ldout(i).ready := false.B // TODO
+    // TODO: writeback missed load
   })
 
 //-------------------------------------------------------
@@ -357,10 +363,10 @@ class Lsu(implicit val p: XSConfig) extends XSModule with HasMEMConst {
   
   // Writeback to CDB
   (0 until LoadPipelineWidth).map(i => {
-    io.out(i) <> loadOut(i)
+    io.ldout(i) <> loadOut(i)
   })
   (0 until StorePipelineWidth).map(i => {
-    io.out(LoadPipelineWidth + i) <> lsroq.io.out(i)
+    io.stout(i) <> lsroq.io.stout(i)
   })
 
   // (0 until 2).map(i => {