XSSim: use a 'TLCacheCork' to deal tl bce channels

src/main/scala/xiangshan/cache/dcache.scala

@@ -291,7 +291,8 @@ class DuplicatedMetaArray extends DCacheModule {
   for (w <- 0 until LoadPipelineWidth) {
     meta(w).io.write <> io.write
     meta(w).io.read  <> io.read(w)
-    meta(w).io.resp  <> io.resp(w)
+    io.resp(w) <> meta(w).io.resp
+//    meta(w).io.resp  <> io.resp(w)
   }
 
   def dump() = {

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -84,7 +84,8 @@ class DCache()(implicit p: Parameters) extends LazyModule with HasDCacheParamete
   val clientParameters = TLMasterPortParameters.v1(
     Seq(TLMasterParameters.v1(
       name = "dcache",
-      sourceId = IdRange(0, cfg.nMissEntries+1)
+      sourceId = IdRange(0, cfg.nMissEntries+1),
+      supportsProbe = TransferSizes(cfg.blockBytes)
     ))
   )
 
@@ -147,14 +148,14 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
 
   metaArray.io.read(0) <> metaReadArb.io.out
 
-  metaArray.io.resp(0) <> missQueue.io.meta_resp
+  missQueue.io.meta_resp <> metaArray.io.resp(0)
   // metaArray.io.resp(0) <> prober.io.meta_resp
-  metaArray.io.resp(0) <> stu.io.meta_resp
-  metaArray.io.resp(0) <> ldu(0).io.meta_resp
+  stu.io.meta_resp <> metaArray.io.resp(0)
+  ldu(0).io.meta_resp <> metaArray.io.resp(0)
 
   for (w <- 1 until LoadPipelineWidth) {
     metaArray.io.read(w) <> ldu(w).io.meta_read
-    metaArray.io.resp(w) <> ldu(w).io.meta_resp
+    ldu(w).io.meta_resp <> metaArray.io.resp(w)
   }
 
   //----------------------------------------

src/test/scala/top/XSSim.scala

@@ -9,7 +9,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import device._
 import freechips.rocketchip.amba.axi4.AXI4UserYanker
 import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, LazyModuleImp}
-import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter, TLFuzzer, TLToAXI4, TLXbar}
+import freechips.rocketchip.tilelink.{TLBuffer, TLCacheCork, TLFragmenter, TLFuzzer, TLToAXI4, TLXbar}
 import xiangshan._
 import utils._
 import firrtl.stage.RunFirrtlTransformAnnotation
@@ -53,9 +53,11 @@ class TrapIO extends XSBundle {
 
 class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
 
+  val memAddressSet = AddressSet(0x0L, 0xffffffffffL)
+
   val soc = LazyModule(new XSSoc())
   val axiRam = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0xffffffffffL),
+    memAddressSet,
     memByte = 128 * 1024 * 1024,
     useBlackBox = true
   ))
@@ -64,6 +66,7 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
   axiRam.node :=
     AXI4UserYanker() :=
     TLToAXI4() :=
+    TLCacheCork(sinkIds = 1) :=
     soc.mem
 
   axiMMIO.axiBus :=