Added and modified various debug logs.

src/main/scala/bus/axi4/AXI4.scala

@@ -65,17 +65,22 @@ trait AXI4HasLast {
 class AXI4LiteBundleA extends Bundle {
   val addr  = Output(UInt(AXI4Parameters.addrBits.W))
   val prot  = Output(UInt(AXI4Parameters.protBits.W))
+  def dump(channelName: String) = printf(s"channel $channelName addr: %x prot: %x\n", addr, prot)
 }
 
 class AXI4LiteBundleW(override val dataBits: Int = AXI4Parameters.dataBits) extends Bundle with AXI4HasData {
   val strb = Output(UInt((dataBits/8).W))
+  def dump(channelName: String) = printf(s"channel $channelName strb: %x data: %x\n", strb, data)
 }
 
 class AXI4LiteBundleB extends Bundle {
   val resp = Output(UInt(AXI4Parameters.respBits.W))
+  def dump(channelName: String) = printf(s"channel $channelName resp: %x\n", resp)
 }
 
-class AXI4LiteBundleR(override val dataBits: Int = AXI4Parameters.dataBits) extends AXI4LiteBundleB with AXI4HasData
+class AXI4LiteBundleR(override val dataBits: Int = AXI4Parameters.dataBits) extends AXI4LiteBundleB with AXI4HasData {
+  override def dump(channelName: String) = printf(s"channel $channelName resp: %x data: %x\n", resp, data)
+}
 
 
 class AXI4Lite extends Bundle {
@@ -84,6 +89,23 @@ class AXI4Lite extends Bundle {
   val b  = Flipped(Decoupled(new AXI4LiteBundleB))
   val ar = Decoupled(new AXI4LiteBundleA)
   val r  = Flipped(Decoupled(new AXI4LiteBundleR))
+  def dump = {
+    when (aw.fire()) {
+      aw.bits.dump("AW")
+    }
+    when (w.fire()) {
+      w.bits.dump("W")
+    }
+    when (b.fire()) {
+      b.bits.dump("B")
+    }
+    when (ar.fire()) {
+      ar.bits.dump("AR")
+    }
+    when (r.fire()) {
+      r.bits.dump("R")
+    }
+  }
 }
 
 
@@ -97,12 +119,20 @@ class AXI4BundleA(override val idBits: Int) extends AXI4LiteBundleA with AXI4Has
   val cache = Output(UInt(AXI4Parameters.cacheBits.W))
   val qos   = Output(UInt(AXI4Parameters.qosBits.W))  // 0=no QoS, bigger = higher priority
   // val region = UInt(width = 4) // optional
+  override def dump(channelName: String) = printf(s"channel $channelName addr: %x len: %x size: %x burst: %x lock: %b cache: %x qos: %x prot: %x id: %d user: %x\n",
+    addr, len, size, burst, lock, cache, qos, prot, id, user)
 }
 
 // id ... removed in AXI4
-class AXI4BundleW(override val dataBits: Int) extends AXI4LiteBundleW(dataBits) with AXI4HasLast
-class AXI4BundleB(override val idBits: Int) extends AXI4LiteBundleB with AXI4HasId with AXI4HasUser
-class AXI4BundleR(override val dataBits: Int, override val idBits: Int) extends AXI4LiteBundleR(dataBits) with AXI4HasLast with AXI4HasId with AXI4HasUser
+class AXI4BundleW(override val dataBits: Int) extends AXI4LiteBundleW(dataBits) with AXI4HasLast {
+  override def dump(channelName: String) = printf(s"channel $channelName strb: %x data: %x last: %b\n", strb, data, last)
+}
+class AXI4BundleB(override val idBits: Int) extends AXI4LiteBundleB with AXI4HasId with AXI4HasUser {
+  override def dump(channelName: String) = printf(s"channel $channelName resp: %x id: %d user: %x\n", resp, id, user)
+}
+class AXI4BundleR(override val dataBits: Int, override val idBits: Int) extends AXI4LiteBundleR(dataBits) with AXI4HasLast with AXI4HasId with AXI4HasUser {
+  override def dump(channelName: String) = printf(s"channel $channelName resp: %x data: %x id: %d user: %x last: %b\n", resp, data, id, user, last)
+}
 
 
 class AXI4(val dataBits: Int = AXI4Parameters.dataBits, val idBits: Int = AXI4Parameters.idBits) extends AXI4Lite {
@@ -111,4 +141,21 @@ class AXI4(val dataBits: Int = AXI4Parameters.dataBits, val idBits: Int = AXI4Pa
   override val b  = Flipped(Decoupled(new AXI4BundleB(idBits)))
   override val ar = Decoupled(new AXI4BundleA(idBits))
   override val r  = Flipped(Decoupled(new AXI4BundleR(dataBits, idBits)))
+  override def dump = {
+    when (aw.fire()) {
+      aw.bits.dump("AW")
+    }
+    when (w.fire()) {
+      w.bits.dump("W")
+    }
+    when (b.fire()) {
+      b.bits.dump("B")
+    }
+    when (ar.fire()) {
+      ar.bits.dump("AR")
+    }
+    when (r.fire()) {
+      r.bits.dump("R")
+    }
+  }
 }

src/main/scala/bus/tilelink/NaiveTLToAXI4.scala

@@ -4,13 +4,16 @@ package bus.tilelink
 
 import chisel3._
 import chisel3.util._
+
+import xiangshan.XSModule
+import xiangshan.utils.XSDebug
 import bus.axi4.AXI4
 import bus.axi4.AXI4Parameters
 import utils.GTimer
 
 // a simpel TileLink to AXI4 converter
 // only support TileLink put and get
-class NaiveTLToAXI4(params: TLParameters) extends Module
+class NaiveTLToAXI4(params: TLParameters) extends XSModule
 {
   val io = IO(new Bundle{
     val in = Flipped(new TLCached(params))
@@ -57,45 +60,12 @@ class NaiveTLToAXI4(params: TLParameters) extends Module
   val s_idle :: s_gather_write_data :: s_wait_awready :: s_mem_write :: s_wait_bresp :: s_wait_arready :: s_mem_read :: s_read_resp :: s_write_resp :: Nil = Enum(9)
 
   val state = RegInit(s_idle)
-  val timer = GTimer()
-  val log_prefix = "cycle: %d [L2Cache] state %x "
-  def log_raw(prefix: String, fmt: String, tail: String, args: Bits*) = {
-    if (debug) {
-      printf(prefix + fmt + tail, args:_*)
-    }
-  }
-
-  /** Single log */
-  def log(fmt: String, args: Bits*) = log_raw(log_prefix, fmt, "\n", timer +: state +: args:_*)
-  /** Log with line continued */
-  def log_part(fmt: String, args: Bits*) = log_raw(log_prefix, fmt, "", timer +: state +: args:_*)
-  /** Log with nothing added */
-  def log_plain(fmt: String, args: Bits*) = log_raw("", fmt, "", args:_*)
-
-  when (in.a.fire()) {
-    log("in.a opcode %x, param %x, size %x, source %x, address %x, mask %x, data %x",
-      in.a.bits.opcode,
-      in.a.bits.param,
-      in.a.bits.size,
-      in.a.bits.source,
-      in.a.bits.address,
-      in.a.bits.mask,
-      in.a.bits.data)
-  }
 
-  /*
-  when (out.a.fire()) {
-    log("out.a.opcode %x, dsid %x, param %x, size %x, source %x, address %x, mask %x, data %x",
-      out.a.bits.opcode,
-      out.a.bits.dsid,
-      out.a.bits.param,
-      out.a.bits.size,
-      out.a.bits.source,
-      out.a.bits.address,
-      out.a.bits.mask,
-      out.a.bits.data)
+  when (XSDebug.trigger) {
+    XSDebug.printPrefix
+    in.dump
+    out.dump
   }
-  */
 
   val in_opcode = in.a.bits.opcode
   val in_addr = in.a.bits.address

src/main/scala/bus/tilelink/TileLink.scala

@@ -6,6 +6,7 @@ import chisel3._
 import chisel3.util._
 
 import xiangshan.HasXSParameter
+import xiangshan.utils.XSDebug
 
 case class TLParameters(
   addressBits: Int = 64,
@@ -248,14 +249,12 @@ class TLBundleE(override val params: TLParameters) extends TLChannel
 class TLUnCached(val params: TLParameters) extends Bundle {
   val a = Decoupled(new TLBundleA(params))
   val d = Flipped(Decoupled(new TLBundleD(params)))
-  def dump(cond: Bool) = {
-    when (cond) {
-      when (a.fire()) {
-        a.bits.dump
-      }
-      when (d.fire()) {
-        d.bits.dump
-      }
+  def dump = {
+    when (a.fire()) {
+      a.bits.dump
+    }
+    when (d.fire()) {
+      d.bits.dump
     }
   }
 }
@@ -265,18 +264,16 @@ class TLCached(override val params: TLParameters) extends TLUnCached(params) {
   val b = Flipped(Decoupled(new TLBundleB(params)))
   val c = Decoupled(new TLBundleC(params))
   val e = Decoupled(new TLBundleE(params))
-  override def dump(cond: Bool) = {
-    super.dump(cond)
-    when (cond) {
-      when (b.fire()) {
-        b.bits.dump
-      }
-      when (c.fire()) {
-        c.bits.dump
-      }
-      when (e.fire()) {
-        e.bits.dump
-      }
+  override def dump = {
+    super.dump
+    when (b.fire()) {
+      b.bits.dump
+    }
+    when (c.fire()) {
+      c.bits.dump
+    }
+    when (e.fire()) {
+      e.bits.dump
     }
   }
 }

src/main/scala/xiangshan/mem/cache/dcache.scala

@@ -409,17 +409,17 @@ class DCache extends DCacheModule
   // -------
   // Pipeline
   def dump_pipeline_reqs(pipeline_stage_name: String, valid: Vec[Bool],
-    reqs: Vec[DCacheReq], s0_type: UInt) = {
+    reqs: Vec[DCacheReq], req_type: UInt) = {
       (0 until memWidth) map { w =>
-          XSDebug(s"$pipeline_stage_name")
-          XSDebug("channel %d: valid: %b ", w.U, valid(w))
+          XSDebug(s"$pipeline_stage_name\n")
+          XSDebug("channel %d: valid: %b \n", w.U, valid(w))
           when (valid(w)) {
-            when (s0_type === t_replay) {
-              XSDebug("type: reply ")
-              } .elsewhen (s0_type === t_lsu) {
-              XSDebug("type: reply ")
+            when (req_type === t_replay) {
+              XSDebug("req_type: replay ")
+              } .elsewhen (req_type === t_lsu) {
+              XSDebug("req_type: lsu ")
               } .otherwise {
-                XSDebug("type: unknown ")
+                XSDebug("req_type: unknown ")
               }
               XSDebug("cmd: %x addr: %x data: %x mask: %x meta: %x\n",
                 reqs(w).cmd, reqs(w).addr, reqs(w).data, reqs(w).mask, reqs(w).meta)
@@ -437,6 +437,10 @@ class DCache extends DCacheModule
 
   dump_pipeline_reqs("DCache s0", s0_valid, s0_req, s0_type)
 
+  /*
+  XSDebug("lsu_req fire: %b valid: %b ready: %b\n", io.lsu.req.fire(), io.lsu.req.valid, io.lsu.req.ready)
+  XSDebug("replay_req fire: %b valid: %b ready: %b\n", mshrs.io.replay.fire(), mshrs.io.replay.valid, mshrs.io.replay.ready)
+  */
 
   // Does this request need to send a response or nack
   // for successfully executed load/stores, we send a resp 

src/main/scala/xiangshan/mem/cache/mshrs.scala

@@ -385,7 +385,7 @@ class MSHRFile extends DCacheModule
   // print all input/output requests for debug purpose
 
   // print req
-  XSDebug(req.fire(), "cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n",
+  XSDebug(req.fire(), "req cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n",
     req.bits.cmd, req.bits.addr, req.bits.data, req.bits.mask, req.bits.meta,
     req.bits.tag_match, req.bits.old_meta.coh.state, req.bits.old_meta.tag, req.bits.way_en)
 
@@ -395,35 +395,40 @@ class MSHRFile extends DCacheModule
   }
 
   // print refill
-  XSDebug(io.refill.fire(), "addr %x data: %x wmask: %x way_en: %x\n",
+  XSDebug(io.refill.fire(), "refill addr %x data: %x wmask: %x way_en: %x\n",
     io.refill.bits.addr, io.refill.bits.data,
     io.refill.bits.wmask, io.refill.bits.way_en)
 
   // print meta_write
-  XSDebug(io.meta_write.fire(), "idx %x way_en: %x old_tag: %x new_coh: %d new_tag: %x\n",
+  XSDebug(io.meta_write.fire(), "meta_write idx %x way_en: %x old_tag: %x new_coh: %d new_tag: %x\n",
     io.meta_write.bits.idx, io.meta_write.bits.way_en,
     io.meta_write.bits.data.coh.state, io.meta_write.bits.data.tag,
     io.meta_write.bits.tag)
 
   // print replay
-  XSDebug(io.replay.fire(), "cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n",
+  XSDebug(io.replay.fire(), "replay cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n",
     io.replay.bits.cmd, io.replay.bits.addr, io.replay.bits.data, io.replay.bits.mask, io.replay.bits.meta,
     io.replay.bits.tag_match, io.replay.bits.old_meta.coh.state, io.replay.bits.old_meta.tag, io.replay.bits.way_en)
 
   // print wb_req
-  XSDebug(io.wb_req.fire(), "idx %x tag: %x source: %d param: %x way_en: %x voluntary: %b\n",
+  XSDebug(io.wb_req.fire(), "wb_req idx %x tag: %x source: %d param: %x way_en: %x voluntary: %b\n",
     io.wb_req.bits.idx, io.wb_req.bits.tag,
     io.wb_req.bits.source, io.wb_req.bits.param,
     io.wb_req.bits.way_en, io.wb_req.bits.voluntary)
 
   // print tilelink messages
   when (XSDebug.trigger && io.mem_acquire.fire()) {
+    // add prefix message, so that we can know that,
+    // when and where this message is created
+    XSDebug.printPrefix
     io.mem_acquire.bits.dump
   }
   when (XSDebug.trigger && io.mem_grant.fire()) {
+    XSDebug.printPrefix
     io.mem_grant.bits.dump
   }
   when (XSDebug.trigger && io.mem_finish.fire()) {
+    XSDebug.printPrefix
     io.mem_finish.bits.dump
   }
 }

src/main/scala/xiangshan/mem/cache/wbu.scala

@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import xiangshan.utils.XSDebug
 import bus.tilelink._
 
 class WritebackReq extends DCacheBundle {
@@ -97,12 +98,15 @@ class WritebackUnit extends DCacheModule {
       data_req_cnt := data_req_cnt + 1.U
     }
     when (r2_data_req_fired) {
-      wb_buffer(r2_data_req_cnt) := Mux1H(req.way_en, io.data_resp)
+      val data = Mux1H(req.way_en, io.data_resp)
+      wb_buffer(r2_data_req_cnt) := data
       when (r2_data_req_cnt === (refillCycles-1).U) {
         io.resp := true.B
         state := s_active
         data_req_cnt := 0.U
       }
+      // print data resp
+      XSDebug(s"data_resp cnt: %d data: %x\n", r2_data_req_cnt, data)
     }
   } .elsewhen (state === s_active) {
     io.release.valid := data_req_cnt < refillCycles.U
@@ -125,4 +129,23 @@ class WritebackUnit extends DCacheModule {
       state := s_invalid
     }
   }
+
+  // print all input/output requests for debug purpose
+  // print req
+  val io_req = io.req.bits
+  XSDebug(io.req.fire(), "req tag: %x idx: %x source: %d param: %x way_en: %x voluntary: %b\n",
+    io_req.tag, io_req.idx, io_req.source, io_req.param, io_req.way_en, io_req.voluntary)
+
+  // print data req
+  val io_data_req = io.data_req.bits
+  XSDebug(io.data_req.fire(), "data_req addr: %x way_en: %x\n", io_data_req.addr, io_data_req.way_en)
+
+  // print release
+  when (XSDebug.trigger && io.release.fire()) {
+    XSDebug.printPrefix
+    io.release.bits.dump
+  }
+
+  // print mem_grant
+  XSDebug(io.mem_grant, "mem_grant\n")
 }

src/main/scala/xiangshan/utils/LogUtils.scala

@@ -61,6 +61,13 @@ sealed abstract class LogHelper(val logLevel: XSLogLevel) extends HasXSParameter
   def trigger: Bool = {
     logLevel.id.U >= XSLog.xsLogLevel && XSLog.displayLog
   }
+
+  def printPrefix()(implicit name: String): Unit = {
+    val commonInfo = p"[$logLevel][time=${GTimer()}] $name: "
+    when (trigger) {
+      printf(commonInfo)
+    }
+  }
 }
 
 object XSDebug extends LogHelper(XSLogLevel.DEBUG)