Fixed several wiring errors.

src/main/scala/xiangshan/cache/dcache.scala

@@ -281,7 +281,6 @@ class DuplicatedMetaArray extends DCacheModule {
     val read  = Vec(LoadPipelineWidth, Flipped(DecoupledIO(new L1MetaReadReq)))
     val write = Flipped(DecoupledIO(new L1MetaWriteReq))
     val resp  = Output(Vec(LoadPipelineWidth, Vec(nWays, new L1Metadata)))
-    val nacks = Output(Vec(LoadPipelineWidth, Bool()))
   })
 
   def onReset = L1Metadata(0.U, ClientMetadata.onReset)

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -81,6 +81,9 @@ class DCacheIO extends DCacheBundle {
 class DCache extends DCacheModule {
   val io = IO(new DCacheIO)
 
+  io.lsu.redirect.valid := false.B
+  io.lsu.redirect.bits := DontCare
+
   //----------------------------------------
   // core data structures
   val dataArray = Module(new DuplicatedDataArray)

src/main/scala/xiangshan/cache/missQueue.scala

@@ -368,6 +368,10 @@ class MissQueue extends DCacheModule
   val refill_arb     = Module(new Arbiter(new L1DataWriteReq,   cfg.nMissEntries))
   val wb_req_arb     = Module(new Arbiter(new WritebackReq,     cfg.nMissEntries))
 
+  // assign default values to output signals
+  io.finish.ready := false.B
+  io.mem_grant.ready := false.B
+
   val entry_alloc_idx = Wire(UInt())
   val req_ready = WireInit(false.B)
 
@@ -389,6 +393,9 @@ class MissQueue extends DCacheModule
     // entry finish
     entry.io.finish.valid   :=  (i.U === io.finish.bits.entry_id) && io.finish.valid
     entry.io.finish.bits    :=  io.finish.bits
+    when (entry.io.finish.valid) {
+      io.finish.ready := entry.io.finish.ready
+    }
 
     meta_read_arb.io.in(i)  <>  entry.io.meta_read
     entry.io.meta_resp      :=  io.meta_resp