Let stu and miss queue expose their inflight reqs' indexes and addrs.

We will use them for synchronization later.
Also, we add get_idx/tag/block_addr/beat stuff.
So next time, use these functions instead of manually manipulating bits.

src/main/scala/xiangshan/cache/dcache.scala

@@ -51,6 +51,12 @@ trait HasDCacheParameters extends HasL1CacheParameters {
   def idxLSB = blockOffBits
   def offsetmsb = idxLSB-1
   def offsetlsb = wordOffBits
+
+  def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits)
+  def get_tag(addr: UInt) = addr >> untagBits
+  def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits)
+  def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits
+
   def rowWords = rowBits/wordBits
   def doNarrowRead = DataBits * nWays % rowBits == 0
   def eccBytes = cacheParams.dataECCBytes

src/main/scala/xiangshan/cache/ldu.scala

@@ -23,17 +23,15 @@ class LoadPipe extends DCacheModule
   val meta_read = io.meta_read.bits
   val data_read = io.data_read.bits
 
-  def beat_idx(addr: UInt) = addr(blockOffBits - 1, beatOffBits)
-
   // Tag read for new requests
-  meta_read.idx    := io.lsu.req.bits.addr >> blockOffBits
+  meta_read.idx    := get_idx(io.lsu.req.bits.addr)
   meta_read.way_en := ~0.U(nWays.W)
   meta_read.tag    := DontCare
   // Data read for new requests
   data_read.addr   := io.lsu.req.bits.addr
   data_read.way_en := ~0.U(nWays.W)
   // only needs to read the specific beat
-  data_read.rmask  := UIntToOH(beat_idx(io.lsu.req.bits.addr))
+  data_read.rmask  := UIntToOH(get_beat(io.lsu.req.bits.addr))
 
   // Pipeline
   // stage 0
@@ -55,7 +53,7 @@ class LoadPipe extends DCacheModule
   // tag check
   val meta_resp = io.meta_resp
   def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
-  val s1_tag_eq_way = wayMap((w: Int) => meta_resp(w).tag === (s1_addr >> untagBits)).asUInt
+  val s1_tag_eq_way = wayMap((w: Int) => meta_resp(w).tag === (get_tag(s1_addr))).asUInt
   val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta_resp(w).coh.isValid()).asUInt
 
 
@@ -85,7 +83,7 @@ class LoadPipe extends DCacheModule
   val s2_data = Wire(Vec(nWays, UInt(encRowBits.W)))
   val data_resp = io.data_resp
   for (w <- 0 until nWays) {
-    s2_data(w) := data_resp(w)(beat_idx(s2_req.addr))
+    s2_data(w) := data_resp(w)(get_beat(s2_req.addr))
   }
 
   val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)

src/main/scala/xiangshan/cache/loadMissQueue.scala

@@ -30,9 +30,9 @@ class LoadMissEntry extends DCacheModule
   val state = RegInit(s_invalid)
 
   val req     = Reg(new DCacheLoadReq)
-  val req_idx = req.addr(untagBits-1, blockOffBits)
-  val req_tag = req.addr >> untagBits
-  val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
+  val req_idx = get_idx(req.addr)
+  val req_tag = get_tag(req.addr)
+  val req_block_addr = get_block_addr(req.addr)
   val reg_miss_resp = Reg(new MissResp)
 
   val rpq = Module(new Queue(new DCacheLoadReq, cfg.nRPQ))
@@ -156,8 +156,8 @@ class LoadMissQueue extends DCacheModule
 
     entry.io.id := i.U(log2Up(cfg.nLoadMissEntries).W)
 
-    idx_matches(i) := entry.io.idx.valid && entry.io.idx.bits === req.bits.addr(untagBits-1,blockOffBits)
-    tag_matches(i) := entry.io.tag.valid && entry.io.tag.bits === req.bits.addr >> untagBits
+    idx_matches(i) := entry.io.idx.valid && entry.io.idx.bits === get_idx(req.bits.addr)
+    tag_matches(i) := entry.io.tag.valid && entry.io.tag.bits === get_tag(req.bits.addr)
     when (XSDebug.trigger) {
       when (idx_matches(i)) {
         XSDebug(s"entry: $i idx_match\n")

src/main/scala/xiangshan/cache/missQueue.scala

@@ -38,8 +38,8 @@ class MissEntry extends DCacheModule
     val resp   = ValidIO(new MissResp)
     val finish = Flipped(DecoupledIO(new MissFinish))
 
-    val idx = Output(Valid(UInt()))
-    val tag = Output(Valid(UInt()))
+    val block_idx   = Output(Valid(UInt()))
+    val block_addr  = Output(Valid(UInt()))
 
     val mem_acquire = Decoupled(new TLBundleA(cfg.busParams))
     val mem_grant   = Flipped(Decoupled(new TLBundleD(cfg.busParams)))
@@ -67,9 +67,9 @@ class MissEntry extends DCacheModule
   val state = RegInit(s_invalid)
 
   val req     = Reg(new MissReq)
-  val req_idx = req.addr(untagBits-1, blockOffBits)
-  val req_tag = req.addr >> untagBits
-  val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
+  val req_idx = get_idx(req.addr)
+  val req_tag = get_tag(req.addr)
+  val req_block_addr = get_block_addr(req.addr)
 
   // meta read results
   val req_tag_match = Reg(Bool())
@@ -89,10 +89,10 @@ class MissEntry extends DCacheModule
   val grantack = Reg(Valid(new TLBundleE(cfg.busParams)))
   val refill_ctr  = Reg(UInt(log2Up(cacheDataBeats).W))
 
-  io.idx.valid := state =/= s_invalid
-  io.tag.valid := state =/= s_invalid
-  io.idx.bits  := req_idx
-  io.tag.bits  := req_tag
+  io.block_idx.valid  := state =/= s_invalid
+  io.block_addr.valid := state =/= s_invalid
+  io.block_idx.bits   := req_idx
+  io.block_addr.bits  := req_block_addr
 
   // assign default values to output signals
   io.req.ready           := false.B
@@ -356,6 +356,9 @@ class MissQueue extends DCacheModule
 
     val wb_req      = Decoupled(new WritebackReq)
     val wb_resp     = Input(Bool())
+
+    val inflight_req_block_idxes  = Output(Vec(cfg.nMissEntries, Valid(UInt())))
+    val inflight_req_block_addrs  = Output(Vec(cfg.nMissEntries, Valid(UInt())))
   })
 
   val resp_arb       = Module(new Arbiter(new MissResp,    cfg.nMissEntries))
@@ -402,6 +405,9 @@ class MissQueue extends DCacheModule
       entry.io.mem_grant <> io.mem_grant
     }
 
+    io.inflight_req_block_idxes(i) <> entry.io.block_idx
+    io.inflight_req_block_addrs(i) <> entry.io.block_addr
+
     entry
   }
 

src/main/scala/xiangshan/cache/storeMissQueue.scala

@@ -29,9 +29,9 @@ class StoreMissEntry extends DCacheModule
   val state = RegInit(s_invalid)
 
   val req     = Reg(new DCacheStoreReq)
-  val req_idx = req.addr(untagBits-1, blockOffBits)
-  val req_tag = req.addr >> untagBits
-  val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
+  val req_idx = get_idx(req.addr)
+  val req_tag = get_tag(req.addr)
+  val req_block_addr = get_block_addr(req.addr)
   val reg_miss_resp = Reg(new MissResp)
 
   // assign default values to output signals

src/main/scala/xiangshan/cache/stu.scala

@@ -14,6 +14,8 @@ class StorePipe extends DCacheModule
     val data_write = Output(Decoupled(new L1DataWriteReq))
     val meta_read  = Decoupled(new L1MetaReadReq)
     val meta_resp  = Output(Vec(nWays, new L1Metadata))
+    val inflight_req_idxes  = Output(Vec(3, Valid(UInt())))
+    val inflight_req_block_addrs  = Output(Vec(3, Valid(UInt())))
   })
 
 
@@ -26,7 +28,7 @@ class StorePipe extends DCacheModule
   val data_read = io.data_read.bits
 
   // Tag read for new requests
-  meta_read.idx    := io.lsu.req.bits.addr >> blockOffBits
+  meta_read.idx    := get_idx(io.lsu.req.bits.addr)
   meta_read.way_en := ~0.U(nWays.W)
   meta_read.tag    := DontCare
   // Data read for new requests
@@ -54,7 +56,7 @@ class StorePipe extends DCacheModule
   val meta_resp = io.meta_resp
   // tag check
   def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
-  val s1_tag_eq_way = wayMap((w: Int) => meta_resp(w).tag === (s1_addr >> untagBits)).asUInt
+  val s1_tag_eq_way = wayMap((w: Int) => meta_resp(w).tag === (get_tag(s1_addr))).asUInt
   val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta_resp(w).coh.isValid()).asUInt
 
 
@@ -137,6 +139,22 @@ class StorePipe extends DCacheModule
       resp.bits.data, resp.bits.meta.id, resp.bits.meta.replay, resp.bits.miss, resp.bits.nack)
   }
 
+  io.inflight_req_idxes(0).valid := s0_valid
+  io.inflight_req_idxes(1).valid := s1_valid
+  io.inflight_req_idxes(2).valid := s2_valid
+
+  io.inflight_req_idxes(0).bits  := get_idx(s0_req.addr)
+  io.inflight_req_idxes(1).bits  := get_idx(s1_req.addr)
+  io.inflight_req_idxes(2).bits  := get_idx(s2_req.addr)
+
+  io.inflight_req_block_addrs(0).valid := s0_valid
+  io.inflight_req_block_addrs(1).valid := s1_valid
+  io.inflight_req_block_addrs(2).valid := s2_valid
+
+  io.inflight_req_block_addrs(0).bits  := get_block_addr(s0_req.addr)
+  io.inflight_req_block_addrs(1).bits  := get_block_addr(s1_req.addr)
+  io.inflight_req_block_addrs(2).bits  := get_block_addr(s2_req.addr)
+
   // -------
   // Debug logging functions
   def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool,