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提交 fc5cbad8 编写于 作者: A Allen
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Fixed various dcache elaboration errors.

上级 c98e38cf
隐藏空白更改
内联 并排
Showing with 120 addition and 100 deletion
src/main/scala/xiangshan/cache/dcache.scala
浏览文件 @ fc5cbad8
......@@ -139,8 +139,8 @@ class L1DataWriteReq extends L1DataReadReq {
abstract class AbstractDataArray extends DCacheModule {
val io = IO(new DCacheBundle {
val read = Input(Vec(LoadPipelineWidth, DecoupledIO(new L1DataReadReq)))
val write = Input(DecoupledIO(new L1DataWriteReq))
val read = Vec(LoadPipelineWidth, Flipped(DecoupledIO(new L1DataReadReq)))
val write = Flipped(DecoupledIO(new L1DataWriteReq))
val resp = Output(Vec(LoadPipelineWidth, Vec(nWays, Vec(refillCycles, Bits(encRowBits.W)))))
val nacks = Output(Vec(LoadPipelineWidth, Bool()))
})
......@@ -278,9 +278,9 @@ class L1MetadataArray(onReset: () => L1Metadata) extends DCacheModule {
class DuplicatedMetaArray extends DCacheModule {
val io = IO(new DCacheBundle {
val read = Input(Vec(LoadPipelineWidth, Valid(new L1MetaReadReq)))
val write = Input(Valid(new L1MetaWriteReq))
val resp = Output(Vec(LoadPipelineWidth, Vec(nWays, Vec(refillCycles, Bits(encRowBits.W)))))
val read = Vec(LoadPipelineWidth, Flipped(DecoupledIO(new L1MetaReadReq)))
val write = Flipped(DecoupledIO(new L1MetaWriteReq))
val resp = Output(Vec(LoadPipelineWidth, Vec(nWays, new L1Metadata)))
val nacks = Output(Vec(LoadPipelineWidth, Bool()))
})
......
src/main/scala/xiangshan/cache/dcacheWrapper.scala
浏览文件 @ fc5cbad8
......@@ -233,14 +233,14 @@ class DCache extends DCacheModule {
val storeMissReq = storeMissQueue.io.miss_req
missReqArb.io.in(0).valid := loadMissReq.valid
missReqArb.io.in(0).ready := loadMissReq.ready
loadMissReq.ready := missReqArb.io.in(0).ready
missReqArb.io.in(0).bits.cmd := loadMissReq.bits.cmd
missReqArb.io.in(0).bits.addr := loadMissReq.bits.addr
missReqArb.io.in(0).bits.client_id := Cat(loadMissQueueClientId,
loadMissReq.bits.client_id(entryIdMSB, entryIdLSB))
missReqArb.io.in(1).valid := storeMissReq.valid
missReqArb.io.in(1).ready := storeMissReq.ready
storeMissReq.ready := missReqArb.io.in(1).ready
missReqArb.io.in(1).bits.cmd := storeMissReq.bits.cmd
missReqArb.io.in(1).bits.addr := storeMissReq.bits.addr
missReqArb.io.in(1).bits.client_id := Cat(storeMissQueueClientId,
......@@ -271,13 +271,13 @@ class DCache extends DCacheModule {
val missFinishArb = Module(new Arbiter(new MissFinish, 2))
missFinishArb.io.in(0).valid := loadMissFinish.valid
missFinishArb.io.in(0).ready := loadMissFinish.ready
loadMissFinish.ready := missFinishArb.io.in(0).ready
missFinishArb.io.in(0).bits.entry_id := loadMissFinish.bits.entry_id
missFinishArb.io.in(0).bits.client_id := Cat(loadMissQueueClientId,
loadMissFinish.bits.client_id(entryIdMSB, entryIdLSB))
missFinishArb.io.in(1).valid := storeMissFinish.valid
missFinishArb.io.in(1).ready := storeMissFinish.ready
storeMissFinish.ready := missFinishArb.io.in(1).ready
missFinishArb.io.in(1).bits.entry_id := storeMissFinish.bits.entry_id
missFinishArb.io.in(1).bits.client_id := Cat(storeMissQueueClientId,
storeMissFinish.bits.client_id(entryIdMSB, entryIdLSB))
......@@ -316,31 +316,24 @@ class DCache extends DCacheModule {
wb.io.mem_grant := io.bus.d.fire() && io.bus.d.bits.source === cfg.nMissEntries.U
// synchronization stuff
val store_idxes = stu.io.inflight_req_idxes
val store_block_addrs = stu.io.inflight_req_block_addrs
val miss_idxes = missQueue.io.inflight_req_idxes
val miss_block_addrs = missQueue.io.inflight_req_block_addrs
def block_load(addr: UInt) = {
val store_addr_matches = VecInit(store_block_addrs map (entry => entry.valid && entry.bits === get_block_addr(addr)))
val store_addr_matches = VecInit(stu.io.inflight_req_block_addrs map (entry => entry.valid && entry.bits === get_block_addr(addr)))
val store_addr_match = store_addr_matches.reduce(_||_)
val miss_idx_matches = VecInit(miss_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val miss_idx_matches = VecInit(missQueue.io.inflight_req_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val miss_idx_match = miss_idx_matches.reduce(_||_)
store_addr_match || miss_idx_match
}
def block_store(addr: UInt) = {
val miss_idx_matches = VecInit(miss_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val miss_idx_matches = VecInit(missQueue.io.inflight_req_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val miss_idx_match = miss_idx_matches.reduce(_||_)
miss_idx_match
}
def block_miss(addr: UInt) = {
val store_idx_matches = VecInit(store_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val store_idx_matches = VecInit(stu.io.inflight_req_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
val store_idx_match = store_idx_matches.reduce(_||_)
store_idx_match
}
......
src/main/scala/xiangshan/cache/ldu.scala
浏览文件 @ fc5cbad8
......@@ -9,10 +9,10 @@ class LoadPipe extends DCacheModule
{
val io = IO(new DCacheBundle{
val lsu = Flipped(new DCacheLoadIO)
val data_read = Decoupled(new L1DataReadReq)
val data_resp = Output(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Output(Vec(nWays, new L1Metadata))
val data_read = DecoupledIO(new L1DataReadReq)
val data_resp = Input(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val meta_read = DecoupledIO(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
})
// LSU requests
......@@ -107,14 +107,16 @@ class LoadPipe extends DCacheModule
// load data gen
val s2_data_word = s2_data_muxed >> Cat(s2_word_idx, 0.U(log2Ceil(wordBits).W))
val resp = Wire(Valid(new DCacheResp))
resp.valid := s2_valid
resp.bits.data := s2_data_word
resp.bits.meta := s2_req.meta
resp.bits.miss := !s2_hit
resp.bits.nack := s2_nack
val resp = Wire(ValidIO(new DCacheResp))
resp.valid := s2_valid
resp.bits.data := s2_data_word
resp.bits.meta := s2_req.meta
resp.bits.miss := !s2_hit
resp.bits.nack := s2_nack
io.lsu.resp <> resp
io.lsu.resp.valid := resp.valid
io.lsu.resp.bits := resp.bits
assert(!(resp.valid && !io.lsu.resp.ready))
when (resp.valid) {
XSDebug(s"LoadPipe resp: data: %x id: %d replay: %b miss: %b nack: %b\n",
......
src/main/scala/xiangshan/cache/loadMissQueue.scala
浏览文件 @ fc5cbad8
......@@ -15,12 +15,12 @@ class LoadMissEntry extends DCacheModule
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val req = Flipped(new DCacheLoadReq)
val req = Input(new DCacheLoadReq)
val replay = DecoupledIO(new DCacheLoadReq)
val miss_req = DecoupledIO(new MissReq)
val miss_resp = ValidIO(new MissResp)
val miss_finish = Flipped(DecoupledIO(new MissFinish))
val miss_resp = Flipped(ValidIO(new MissResp))
val miss_finish = DecoupledIO(new MissFinish)
val idx = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
......@@ -41,11 +41,15 @@ class LoadMissEntry extends DCacheModule
rpq.io.enq.bits := io.req
rpq.io.deq.ready := false.B
// assign default values to output signals
io.req_pri_rdy := false.B
when (rpq.io.enq.fire()) {
assert(io.req.cmd === M_XRD)
}
io.req_pri_rdy := state === s_invalid
val sec_rdy = state === s_miss_req || state === s_miss_resp
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
// assign default values to output signals
io.replay.valid := false.B
io.replay.bits := DontCare
......@@ -59,15 +63,13 @@ class LoadMissEntry extends DCacheModule
io.idx.bits := req_idx
io.tag.bits := req_tag
XSDebug("entry: %d state: %d\n", io.id, state)
// --------------------------------------------
// s_invalid: receive requests
when (state === s_invalid) {
io.req_pri_rdy := true.B
assert(rpq.io.enq.ready)
when (io.req_pri_val && io.req_pri_rdy) {
assert(req.cmd === M_XRD)
req := io.req
state := s_miss_req
}
......@@ -106,6 +108,11 @@ class LoadMissEntry extends DCacheModule
}
}
//
// we must wait for response here,
// if we do'not wait for response here,
// this entry may be freed before it's response comes back
//
when (state === s_replay_resp) {
replay_resp_ctr := replay_resp_ctr + 1.U
when (replay_resp_ctr === loadPipelineLatency.U) {
......@@ -131,8 +138,8 @@ class LoadMissQueue extends DCacheModule
val replay = new DCacheLoadIO
val miss_req = DecoupledIO(new MissReq)
val miss_resp = ValidIO(new MissResp)
val miss_finish = Flipped(DecoupledIO(new MissFinish))
val miss_resp = Flipped(ValidIO(new MissResp))
val miss_finish = DecoupledIO(new MissFinish)
})
val miss_req_arb = Module(new Arbiter(new MissReq, cfg.nLoadMissEntries))
......@@ -167,7 +174,6 @@ class LoadMissQueue extends DCacheModule
}
}
// entry req
entry.io.req_pri_val := (i.U === entry_alloc_idx) && pri_val
when (i.U === entry_alloc_idx) {
......@@ -179,20 +185,20 @@ class LoadMissQueue extends DCacheModule
replay_arb.io.in(i) <> entry.io.replay
miss_req_arb.io.in(i) <> entry.io.miss_req
when ((i.U === io.miss_resp.bits.client_id) && io.miss_resp.valid) {
entry.io.miss_resp.valid := true.B
entry.io.miss_resp.bits := io.miss_resp.bits
}
entry.io.miss_resp.valid := (i.U === io.miss_resp.bits.client_id) && io.miss_resp.valid
entry.io.miss_resp.bits := io.miss_resp.bits
miss_finish_arb.io.in(i) <> entry.io.miss_finish
entry
}
entry_alloc_idx := RegNext(PriorityEncoder(entries.map(m=>m.io.req_pri_rdy)))
entry_alloc_idx := PriorityEncoder(entries.map(m=>m.io.req_pri_rdy))
req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy)
io.replay.req <> replay_arb.io.out
io.lsu.resp <> io.replay.resp
io.miss_resp <> miss_req_arb.io.out
io.miss_req <> miss_req_arb.io.out
io.miss_finish <> miss_finish_arb.io.out
}
src/main/scala/xiangshan/cache/missQueue.scala
浏览文件 @ fc5cbad8
......@@ -35,22 +35,22 @@ class MissEntry extends DCacheModule
// client requests
val req = Flipped(DecoupledIO(new MissReq))
val resp = ValidIO(new MissResp)
val resp = DecoupledIO(new MissResp)
val finish = Flipped(DecoupledIO(new MissFinish))
val block_idx = Output(Valid(UInt()))
val block_addr = Output(Valid(UInt()))
val mem_acquire = Decoupled(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(Decoupled(new TLBundleD(cfg.busParams)))
val mem_finish = Decoupled(new TLBundleE(cfg.busParams))
val mem_acquire = DecoupledIO(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(DecoupledIO(new TLBundleD(cfg.busParams)))
val mem_finish = DecoupledIO(new TLBundleE(cfg.busParams))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Output(Vec(nWays, new L1Metadata))
val meta_write = Decoupled(new L1MetaWriteReq)
val refill = Decoupled(new L1DataWriteReq)
val meta_read = DecoupledIO(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
val meta_write = DecoupledIO(new L1MetaWriteReq)
val refill = DecoupledIO(new L1DataWriteReq)
val wb_req = Decoupled(new WritebackReq)
val wb_req = DecoupledIO(new WritebackReq)
val wb_resp = Input(Bool())
})
......@@ -97,6 +97,7 @@ class MissEntry extends DCacheModule
// assign default values to output signals
io.req.ready := false.B
io.resp.valid := false.B
io.resp.bits := DontCare
io.finish.ready := false.B
io.mem_acquire.valid := false.B
......@@ -342,27 +343,26 @@ class MissQueue extends DCacheModule
{
val io = IO(new Bundle {
val req = Flipped(DecoupledIO(new MissReq))
val resp = DecoupledIO(new MissResp)
val resp = ValidIO(new MissResp)
val finish = Flipped(DecoupledIO(new MissFinish))
val mem_acquire = Decoupled(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(Decoupled(new TLBundleD(cfg.busParams)))
val mem_finish = Decoupled(new TLBundleE(cfg.busParams))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Output(Vec(nWays, new L1Metadata))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
val meta_write = Decoupled(new L1MetaWriteReq)
val refill = Decoupled(new L1DataWriteReq)
val wb_req = Decoupled(new WritebackReq)
val wb_resp = Input(Bool())
val inflight_req_idxes = Output(Vec(cfg.nMissEntries, Valid(UInt())))
val inflight_req_block_addrs = Output(Vec(cfg.nMissEntries, Valid(UInt())))
val inflight_req_idxes = Output(Vec(cfg.nMissEntries, Valid(UInt())))
val inflight_req_block_addrs = Output(Vec(cfg.nMissEntries, Valid(UInt())))
})
val resp_arb = Module(new Arbiter(new MissResp, cfg.nMissEntries))
val finish_arb = Module(new Arbiter(new MissFinish, cfg.nMissEntries))
val resp_arb = Module(new Arbiter(new MissResp, cfg.nMissEntries))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, cfg.nMissEntries))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, cfg.nMissEntries))
val refill_arb = Module(new Arbiter(new L1DataWriteReq, cfg.nMissEntries))
......@@ -384,7 +384,7 @@ class MissQueue extends DCacheModule
}
// entry resp
resp_arb.io.in(i) <> entry.io.resp
resp_arb.io.in(i) <> entry.io.resp
// entry finish
entry.io.finish.valid := (i.U === io.finish.bits.entry_id) && io.finish.valid
......@@ -405,16 +405,19 @@ class MissQueue extends DCacheModule
entry.io.mem_grant <> io.mem_grant
}
io.inflight_req_idxes(i) <> entry.io.block_idx
io.inflight_req_idxes(i) <> entry.io.block_idx
io.inflight_req_block_addrs(i) <> entry.io.block_addr
entry
}
entry_alloc_idx := RegNext(PriorityEncoder(entries.map(m=>m.io.req.ready)))
entry_alloc_idx := PriorityEncoder(entries.map(m=>m.io.req.ready))
io.req.ready := req_ready
io.resp <> resp_arb.io.out
io.resp.valid := resp_arb.io.out.valid
io.resp.bits := resp_arb.io.out.bits
resp_arb.io.out.ready := true.B
io.meta_read <> meta_read_arb.io.out
io.meta_write <> meta_write_arb.io.out
io.refill <> refill_arb.io.out
......
src/main/scala/xiangshan/cache/storeMissQueue.scala
浏览文件 @ fc5cbad8
......@@ -13,15 +13,14 @@ class StoreMissEntry extends DCacheModule
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req = Flipped(new DCacheStoreReq)
val req = Input(new DCacheStoreReq)
val replay = DecoupledIO(new DCacheStoreReq)
val miss_req = DecoupledIO(new MissReq)
val miss_resp = ValidIO(new MissResp)
val miss_finish = Flipped(DecoupledIO(new MissFinish))
val miss_resp = Flipped(ValidIO(new MissResp))
val miss_finish = DecoupledIO(new MissFinish)
val idx = Output(Valid(UInt()))
val way = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
})
......@@ -35,7 +34,10 @@ class StoreMissEntry extends DCacheModule
val reg_miss_resp = Reg(new MissResp)
// assign default values to output signals
io.req_pri_rdy := false.B
io.req_pri_rdy := state === s_invalid
when (io.req_pri_val && io.req_pri_rdy) {
assert(req.cmd === M_XWR)
}
io.replay.valid := false.B
io.replay.bits := DontCare
......@@ -47,19 +49,15 @@ class StoreMissEntry extends DCacheModule
io.idx.valid := state =/= s_invalid
io.tag.valid := state =/= s_invalid
io.way.valid := state =/= s_invalid
io.idx.bits := req_idx
io.tag.bits := req_tag
io.way.bits := DontCare
XSDebug("entry: %d state: %d\n", io.id, state)
// --------------------------------------------
// s_invalid: receive requests
when (state === s_invalid) {
io.req_pri_rdy := true.B
when (io.req_pri_val && io.req_pri_rdy) {
assert(req.cmd === M_XRD)
req := io.req
state := s_miss_req
}
......@@ -96,6 +94,11 @@ class StoreMissEntry extends DCacheModule
}
}
//
// we must wait for response here,
// if we do'not wait for response here,
// this entry may be freed before it's response comes back
//
when (state === s_replay_resp) {
replay_resp_ctr := replay_resp_ctr + 1.U
when (replay_resp_ctr === storePipelineLatency.U) {
......@@ -121,24 +124,35 @@ class StoreMissQueue extends DCacheModule
val replay = new DCacheStoreIO
val miss_req = DecoupledIO(new MissReq)
val miss_resp = ValidIO(new MissResp)
val miss_finish = Flipped(DecoupledIO(new MissFinish))
val miss_resp = Flipped(ValidIO(new MissResp))
val miss_finish = DecoupledIO(new MissFinish)
})
val miss_req_arb = Module(new Arbiter(new MissReq, cfg.nStoreMissEntries))
val miss_finish_arb = Module(new Arbiter(new MissFinish, cfg.nStoreMissEntries))
val replay_arb = Module(new Arbiter(new DCacheStoreReq, cfg.nStoreMissEntries))
val idx_matches = Wire(Vec(cfg.nLoadMissEntries, Bool()))
val tag_matches = Wire(Vec(cfg.nLoadMissEntries, Bool()))
val tag_match = Mux1H(idx_matches, tag_matches)
val idx_match = idx_matches.reduce(_||_)
val req = io.lsu.req
val entry_alloc_idx = Wire(UInt())
val pri_rdy = WireInit(false.B)
val pri_val = req.valid
val pri_val = req.valid && !idx_match
assert(!(req.valid && idx_match))
val entries = (0 until cfg.nStoreMissEntries) map { i =>
val entry = Module(new StoreMissEntry)
entry.io.id := i.U(log2Up(cfg.nStoreMissEntries).W)
idx_matches(i) := entry.io.idx.valid && entry.io.idx.bits === get_idx(req.bits.addr)
tag_matches(i) := entry.io.tag.valid && entry.io.tag.bits === get_tag(req.bits.addr)
// entry req
entry.io.req_pri_val := (i.U === entry_alloc_idx) && pri_val
when (i.U === entry_alloc_idx) {
......@@ -148,20 +162,20 @@ class StoreMissQueue extends DCacheModule
replay_arb.io.in(i) <> entry.io.replay
miss_req_arb.io.in(i) <> entry.io.miss_req
when ((i.U === io.miss_resp.bits.client_id) && io.miss_resp.valid) {
entry.io.miss_resp.valid := true.B
entry.io.miss_resp.bits := io.miss_resp.bits
}
entry.io.miss_resp.valid := (i.U === io.miss_resp.bits.client_id) && io.miss_resp.valid
entry.io.miss_resp.bits := io.miss_resp.bits
miss_finish_arb.io.in(i) <> entry.io.miss_finish
entry
}
entry_alloc_idx := RegNext(PriorityEncoder(entries.map(m=>m.io.req_pri_rdy)))
entry_alloc_idx := PriorityEncoder(entries.map(m=>m.io.req_pri_rdy))
req.ready := pri_rdy
io.replay.req <> replay_arb.io.out
io.lsu.resp <> io.replay.resp
io.miss_resp <> miss_req_arb.io.out
io.miss_req <> miss_req_arb.io.out
io.miss_finish <> miss_finish_arb.io.out
}
src/main/scala/xiangshan/cache/stu.scala
浏览文件 @ fc5cbad8
......@@ -9,13 +9,13 @@ class StorePipe extends DCacheModule
{
val io = IO(new DCacheBundle{
val lsu = Flipped(new DCacheStoreIO)
val data_read = Decoupled(new L1DataReadReq)
val data_resp = Output(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val data_write = Output(Decoupled(new L1DataWriteReq))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Output(Vec(nWays, new L1Metadata))
val inflight_req_idxes = Output(Vec(3, Valid(UInt())))
val inflight_req_block_addrs = Output(Vec(3, Valid(UInt())))
val data_read = DecoupledIO(new L1DataReadReq)
val data_resp = Input(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val data_write = DecoupledIO(new L1DataWriteReq)
val meta_read = DecoupledIO(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
val inflight_req_idxes = Output(Vec(3, Valid(UInt())))
val inflight_req_block_addrs = Output(Vec(3, Valid(UInt())))
})
......@@ -68,7 +68,7 @@ class StorePipe extends DCacheModule
val s2_tag_match_way = RegNext(s1_tag_match_way)
val s2_tag_match = s2_tag_match_way.orR
val s2_hit_way = OHToUInt(s2_tag_match_way)
val s2_hit_way = OHToUInt(s2_tag_match_way, nWays)
val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegNext(meta_resp(w).coh)))
val s2_has_permission = s2_hit_state.onAccess(s2_req.cmd)._1
val s2_new_hit_state = s2_hit_state.onAccess(s2_req.cmd)._3
......@@ -132,7 +132,9 @@ class StorePipe extends DCacheModule
resp.bits.miss := !s2_hit
resp.bits.nack := s2_nack
io.lsu.resp <> resp
io.lsu.resp.valid := resp.valid
io.lsu.resp.bits := resp.bits
assert(!(resp.valid && !io.lsu.resp.ready))
when (resp.valid) {
XSDebug(s"StorePipe resp: data: %x id: %d replay: %b miss: %b nack: %b\n",
......
src/main/scala/xiangshan/cache/wbu.scala
浏览文件 @ fc5cbad8
......@@ -19,11 +19,11 @@ class WritebackReq extends DCacheBundle {
class WritebackUnit extends DCacheModule {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new WritebackReq()))
val req = Flipped(DecoupledIO(new WritebackReq()))
val resp = Output(Bool())
val data_req = Decoupled(new L1DataReadReq)
val data_resp = Input(Vec(nWays, Bits(encRowBits.W)))
val release = Decoupled(new TLBundleC(cfg.busParams))
val data_req = DecoupledIO(new L1DataReadReq)
val data_resp = Input(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val release = DecoupledIO(new TLBundleC(cfg.busParams))
val mem_grant = Input(Bool())
})
......
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