1. fix a bug about Instruction splitting of UopDivType.VEC_VMV
2. fix a bug decode of viota_m/vid_v

* func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN

* pom(yunsuan): add isVsilde in VpermType & fix bugs of Permutation

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx & add some test for VPERM

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan):add vfslide1up & vfslide1down

1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports
2. func(VpermType): add vfslide1up & vfslide1down

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

* fix(decode): fix decode bug of selImm

1. fix decode bug of selImm
2. change VipuType to VpermType

* func(yunsuan): add VIAlu code v3

1. add VIAlu code v3
2. Update the IO of VFPU

* pom(yunsuan): add IALU V3

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include <algorithm>
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

* func(decode+VIPU): support vslide1up instruction

* bump(yunsuan): func(VFADD) & VIPU type & test(VPERM)

1. Some logic moves from VIPU.scala to VPUSubModule.scala
2. add VIAluFix

1. rename UopDivType
2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV
3. add UopDivType.VEC_MMM for decode of VMAND_MM VMANDN_MM ... VMXOR_MM

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.

This will reduce the number of replays of the load instruction which cannot
enter the missqueue

1. fix vset related bugs
2. modifiy the update logic of vxsat
3. modify numFpRfPorts parameter in the ReservationStationBase

* MMU: Add sector tlb for larger capacity

* MMU: Update difftest for sector tlb

This commit aims to fix dcache plru access logic

In the previous version, when a cacheline not in l1 is accessed, a replace way
is picked and used to update l1 plru (set the way as lru). However, if the same
missed cacheline is accessed multiple times before l1 refill, l1 will pick a new
replace way and use it to update plru for each time the missed cacheline is
accessed. It makes the plru totally a mess.

To fix that problem, extra condition check is added for a missed load plru
update. Now plru is updated on:

* load/store hit (touch hit way)
* load/store primary miss (touch replacement way)
* load/store secondary miss (touch replacement way)

`updateReplaceOn2ndmiss` is enabled. Disable it if the timing is bad.

1. fix bug that connection of fuOpType in VIPU
2. vadd vmin vminu vmax vmaxu vand vor vxor vsub vrsub test pass