func(DecodeUnitComp): support VEC_VRED (#2017)

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx & add some test for VPERM

src/main/scala/xiangshan/Parameters.scala

@@ -133,7 +133,7 @@ case class XSCoreParameters
   IssQueSize: Int = 16,
   IntLogicRegs: Int = 33,
   FpLogicRegs: Int = 33,
-  VecLogicRegs: Int = 33,
+  VecLogicRegs: Int = 39,
   NRPhyRegs: Int = 192,
   IntPhyRegs: Int = 192,
   VfPhyRegs: Int = 192,

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -34,7 +34,7 @@ trait VectorConstants {
   val MAX_VLMUL = 8
   val INT_VCONFIG = 32
   val FP_TMP_REG_MV = 32
-  val VECTOR_TMP_REG_LMUL = 32
+  val VECTOR_TMP_REG_LMUL = 32 // 32~38  ->  7
 }
 
 class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle {
@@ -106,6 +106,7 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
     UopDivType.VEC_FSLIDE1UP   -> lmul,
     UopDivType.VEC_SLIDE1DOWN  -> Cat(lmul, 0.U(1.W)),
     UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U),
+    UopDivType.VEC_VRED        -> lmul,
   ))
 
   val src1 = ctrl_flow.instr(19, 15)
@@ -571,6 +572,61 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
       csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1
       csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U
     }
+    is(UopDivType.VEC_VRED) {
+      when(simple.io.vconfig.vtype.vlmul === "b001".U){
+          csBundle(0).ctrl.srcType(2) := SrcType.DC
+          csBundle(0).ctrl.lsrc(0) := src2 + 1.U
+          csBundle(0).ctrl.lsrc(1) := src2
+          csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
+          csBundle(0).ctrl.uopIdx := 0.U
+      }
+      when(simple.io.vconfig.vtype.vlmul === "b010".U) {
+        csBundle(0).ctrl.srcType(2) := SrcType.DC
+        csBundle(0).ctrl.lsrc(0) := src2 + 1.U
+        csBundle(0).ctrl.lsrc(1) := src2
+        csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
+        csBundle(0).ctrl.uopIdx := 0.U
+
+        csBundle(1).ctrl.srcType(2) := SrcType.DC
+        csBundle(1).ctrl.lsrc(0) := src2 + 3.U
+        csBundle(1).ctrl.lsrc(1) := src2 + 2.U
+        csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U
+        csBundle(1).ctrl.uopIdx := 1.U
+
+        csBundle(2).ctrl.srcType(2) := SrcType.DC
+        csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U
+        csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U
+        csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U
+        csBundle(2).ctrl.uopIdx := 2.U
+      }
+      when(simple.io.vconfig.vtype.vlmul === "b011".U) {
+        for(i <- 0 until MAX_VLMUL){
+          if(i < MAX_VLMUL - MAX_VLMUL/2){
+            csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U
+            csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U
+            csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U
+          } else if (i < MAX_VLMUL - MAX_VLMUL/4) {
+            csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U
+            csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U
+            csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U
+          }else if (i < MAX_VLMUL - MAX_VLMUL/8) {
+            csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U
+            csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U
+            csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U
+          }
+          csBundle(i).ctrl.srcType(2) := SrcType.DC
+          csBundle(i).ctrl.uopIdx := i.U
+        }
+      }
+      when (simple.io.vconfig.vtype.vlmul.orR()){
+        csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp
+        csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1
+        csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U
+        csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest
+        csBundle(numOfUop - 1.U).ctrl.ldest := dest
+        csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U
+      }
+    }
   }
 
   //uops dispatch

src/main/scala/xiangshan/backend/decode/VecDecoder.scala

@@ -307,14 +307,14 @@ object VecDecoder extends DecodeConstants {
     VMV_X_S      -> OPMVV(T, FuType.vipu, VipuType.dummy, T, F, F),
     VNMSAC_VV    -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
     VNMSUB_VV    -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
-    VREDAND_VS   -> OPMVV(T, FuType.vipu, VipuType.vredand_vs, F, T, F),
-    VREDMAX_VS   -> OPMVV(T, FuType.vipu, VipuType.vredmax_vs, F, T, F),
-    VREDMAXU_VS  -> OPMVV(T, FuType.vipu, VipuType.vredmaxu_vs, F, T, F),
-    VREDMIN_VS   -> OPMVV(T, FuType.vipu, VipuType.vredmin_vs, F, T, F),
-    VREDMINU_VS  -> OPMVV(T, FuType.vipu, VipuType.vredminu_vs, F, T, F),
-    VREDOR_VS    -> OPMVV(T, FuType.vipu, VipuType.vredor_vs, F, T, F),
-    VREDSUM_VS   -> OPMVV(T, FuType.vipu, VipuType.vredsum_vs, F, T, F),
-    VREDXOR_VS   -> OPMVV(T, FuType.vipu, VipuType.vredxor_vs, F, T, F),
+    VREDAND_VS   -> OPMVV(T, FuType.vipu, VipuType.vredand_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDMAX_VS   -> OPMVV(T, FuType.vipu, VipuType.vredmax_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDMAXU_VS  -> OPMVV(T, FuType.vipu, VipuType.vredmaxu_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDMIN_VS   -> OPMVV(T, FuType.vipu, VipuType.vredmin_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDMINU_VS  -> OPMVV(T, FuType.vipu, VipuType.vredminu_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDOR_VS    -> OPMVV(T, FuType.vipu, VipuType.vredor_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDSUM_VS   -> OPMVV(T, FuType.vipu, VipuType.vredsum_vs, F, T, F, UopDivType.VEC_VRED),
+    VREDXOR_VS   -> OPMVV(T, FuType.vipu, VipuType.vredxor_vs, F, T, F, UopDivType.VEC_VRED),
     VREM_VV      -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
     VREMU_VV     -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
     VSEXT_VF2    -> OPMVV(T, FuType.vialuF, VialuFixType.vsext_vf2, F, T, F, UopDivType.VEC_EXT2),

src/main/scala/xiangshan/backend/exu/ExeUnit.scala

@@ -106,8 +106,16 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) {
     vipuModules.map(_._1.asInstanceOf[VPUSubModule]).foreach(mod => {
       mod.vxrm := csr_vxrm
       mod.vstart := csr_vstart
-      io.out.bits.vxsat := mod.vxsat
     })
+    // vxsat is selected by arbSelReg
+    require(config.hasFastUopOut, "non-fast not implemented")
+    val vxsatSel = vipuModules.map{ case (fu, (cfg, i)) =>
+      val vxsatValid = arbSelReg(i)
+      val vxsat = fu.asInstanceOf[VPUSubModule].vxsat
+      val vxsatBits = if (cfg.fastImplemented) vxsat else RegNext(vxsat)
+      (vxsatValid, vxsatBits)
+    }
+    io.out.bits.vxsat := Mux1H(vxsatSel.map(_._1), vxsatSel.map(_._2))
   }
   val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA])
   if (fmaModules.nonEmpty) {

src/main/scala/xiangshan/package.scala

@@ -578,6 +578,7 @@ package object xiangshan {
     def VEC_FSLIDE1UP    = "b100001".U // vfslide1up.vf
     def VEC_SLIDE1DOWN   = "b100010".U // vslide1down.vx
     def VEC_FSLIDE1DOWN  = "b100011".U // vfslide1down.vf
+    def VEC_VRED         = "b100100".U // VEC_VRED
     def VEC_MMM          = "b000000".U // VEC_MMM
     def dummy     = "b111111".U
 

yunsuan @ a70a08c4

-Subproject commit 3f473fe929b5f05a2e3821717981bdb6cf548d7f
+Subproject commit a70a08c4012462302e249ad063a8e38df3baab99