func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012)

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan):add vfslide1up & vfslide1down

1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports
2. func(VpermType): add vfslide1up & vfslide1down

src/main/scala/xiangshan/Parameters.scala

@@ -127,7 +127,7 @@ case class XSCoreParameters
   DecodeWidth: Int = 6,
   RenameWidth: Int = 6,
   CommitWidth: Int = 6,
-  MaxUopSize: Int = 10,
+  MaxUopSize: Int = 16,
   FtqSize: Int = 64,
   EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
   IssQueSize: Int = 16,

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -115,7 +115,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule with HasPerfEvents {
     val robCommits = Input(new RobCommitIO)
   })
 
-  val decoderComp = Module(new DecodeUnitComp(10))
+  val decoderComp = Module(new DecodeUnitComp(MaxUopSize))
   val decoders = Seq.fill(DecodeWidth - 1)(Module(new DecodeUnit))
   val debug_globalCounter = RegInit(0.U(XLEN.W))
   val vconfigGen = Module(new VConfigGen)

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -80,29 +80,32 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
   val typeOfDiv = cf_ctrl_u.ctrl.uopDivType
 
   //LMUL
-  val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array(
+  val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array(
     "b001".U -> 2.U,
     "b010".U -> 4.U,
     "b011".U -> 8.U
   ))
   //number of uop
-  val numOfUop = MuxLookup(typeOfDiv, 1.U, Array(
-    UopDivType.VEC_0XV -> 2.U,
-    UopDivType.DIR -> 2.U,
-    UopDivType.VEC_VVV -> lmul,
-    UopDivType.VEC_EXT2 -> lmul,
-    UopDivType.VEC_EXT4 -> lmul,
-    UopDivType.VEC_EXT8 -> lmul,
-    UopDivType.VEC_VVM -> lmul,
-    UopDivType.VEC_VXM -> (lmul + 1.U),
-    UopDivType.VEC_VXV -> (lmul + 1.U),
-    UopDivType.VEC_VVW -> (lmul + lmul),           // lmul <= 4
-    UopDivType.VEC_WVW -> (lmul + lmul),           // lmul <= 4
-    UopDivType.VEC_VXW -> (lmul + lmul + 1.U),     // lmul <= 4
-    UopDivType.VEC_WXW -> (lmul + lmul + 1.U),     // lmul <= 4
-    UopDivType.VEC_WVV -> (lmul + lmul),           // lmul <= 4
-    UopDivType.VEC_WXV -> (lmul + lmul + 1.U),     // lmul <= 4
-    UopDivType.VEC_SLIDE1UP -> (lmul + 1.U)
+  val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array(
+    UopDivType.VEC_0XV         -> 2.U,
+    UopDivType.DIR             -> 2.U,
+    UopDivType.VEC_VVV         -> lmul,
+    UopDivType.VEC_EXT2        -> lmul,
+    UopDivType.VEC_EXT4        -> lmul,
+    UopDivType.VEC_EXT8        -> lmul,
+    UopDivType.VEC_VVM         -> lmul,
+    UopDivType.VEC_VXM         -> (lmul +& 1.U),
+    UopDivType.VEC_VXV         -> (lmul +& 1.U),
+    UopDivType.VEC_VVW         -> Cat(lmul, 0.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_WVW         -> Cat(lmul, 0.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_VXW         -> Cat(lmul, 1.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_WXW         -> Cat(lmul, 1.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_WVV         -> Cat(lmul, 0.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_WXV         -> Cat(lmul, 1.U(1.W)),     // lmul <= 4
+    UopDivType.VEC_SLIDE1UP    -> (lmul +& 1.U),
+    UopDivType.VEC_FSLIDE1UP   -> lmul,
+    UopDivType.VEC_SLIDE1DOWN  -> Cat(lmul, 0.U(1.W)),
+    UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U),
   ))
 
   val src1 = ctrl_flow.instr(19, 15)
@@ -488,6 +491,86 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
         csBundle(i + 1).ctrl.uopIdx := i.U
       }
     }
+    is(UopDivType.VEC_FSLIDE1UP) {
+      //LMUL
+      csBundle(0).ctrl.srcType(0) := SrcType.fp
+      csBundle(0).ctrl.lsrc(0) := src1
+      csBundle(0).ctrl.lsrc(1) := src2
+      csBundle(0).ctrl.lsrc(2) := dest
+      csBundle(0).ctrl.ldest := dest
+      csBundle(0).ctrl.uopIdx := 0.U
+      for (i <- 1 until MAX_VLMUL) {
+        csBundle(i).ctrl.srcType(0) := SrcType.vp
+        csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U
+        csBundle(i).ctrl.lsrc(1) := src2 + i.U
+        csBundle(i).ctrl.lsrc(2) := dest + i.U
+        csBundle(i).ctrl.ldest := dest + i.U
+        csBundle(i).ctrl.uopIdx := i.U
+      }
+    }
+    is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16
+      /*
+      FMV.D.X
+       */
+      csBundle(0).ctrl.srcType(0) := SrcType.reg
+      csBundle(0).ctrl.srcType(1) := SrcType.imm
+      csBundle(0).ctrl.lsrc(1) := 0.U
+      csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U
+      csBundle(0).ctrl.fuType := FuType.i2f
+      csBundle(0).ctrl.rfWen := false.B
+      csBundle(0).ctrl.fpWen := true.B
+      csBundle(0).ctrl.vecWen := false.B
+      csBundle(0).ctrl.fpu.isAddSub := false.B
+      csBundle(0).ctrl.fpu.typeTagIn := FPU.D
+      csBundle(0).ctrl.fpu.typeTagOut := FPU.D
+      csBundle(0).ctrl.fpu.fromInt := true.B
+      csBundle(0).ctrl.fpu.wflags := false.B
+      csBundle(0).ctrl.fpu.fpWen := true.B
+      csBundle(0).ctrl.fpu.div := false.B
+      csBundle(0).ctrl.fpu.sqrt := false.B
+      csBundle(0).ctrl.fpu.fcvt := false.B
+      //LMUL
+      for (i <- 0 until MAX_VLMUL) {
+        csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp
+        csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp
+        csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U
+        csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U
+        csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U
+        csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
+        csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U
+        if (2 * i + 2 < MAX_VLMUL * 2 ){
+          csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp
+          csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U
+          // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U         // DontCare
+          csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
+          csBundle(2 * i + 2).ctrl.ldest := dest + i.U
+          csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U
+        }
+      }
+      csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp
+      csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U
+      csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U
+    }
+    is(UopDivType.VEC_FSLIDE1DOWN) {
+      //LMUL
+      for (i <- 0 until MAX_VLMUL) {
+        csBundle(2 * i).ctrl.srcType(0) := SrcType.vp
+        csBundle(2 * i).ctrl.srcType(1) := SrcType.vp
+        csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U
+        csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U
+        csBundle(2 * i).ctrl.lsrc(2) := dest + i.U
+        csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
+        csBundle(2 * i).ctrl.uopIdx := (2 * i).U
+        csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp
+        csBundle(2 * i + 1).ctrl.lsrc(0) := src1
+        csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
+        csBundle(2 * i + 1).ctrl.ldest := dest + i.U
+        csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U
+      }
+      csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp
+      csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1
+      csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U
+    }
   }
 
   //uops dispatch

src/main/scala/xiangshan/backend/decode/VecDecoder.scala

@@ -359,7 +359,7 @@ object VecDecoder extends DecodeConstants {
     VREM_VX        -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F),
     VREMU_VX       -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F),
 
-    VSLIDE1DOWN_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F),
+    VSLIDE1DOWN_VX -> OPMVX(T, FuType.vppu, VpermType.vslide1down, F, T, F, UopDivType.VEC_SLIDE1DOWN),
     VSLIDE1UP_VX   -> OPMVX(T, FuType.vppu, VpermType.vslide1up, F, T, F, UopDivType.VEC_SLIDE1UP),
     VWADD_VX       -> OPMVX(T, FuType.vialuF, VialuFixType.vwadd_vv, F, T, F, UopDivType.VEC_VXW),
     VWADD_WX       -> OPMVX(T, FuType.vialuF, VialuFixType.vwadd_wv, F, T, F, UopDivType.VEC_WXW),
@@ -548,11 +548,11 @@ object VecDecoder extends DecodeConstants {
     VFMV_S_F           -> OPFVF(SrcType.fp, SrcType.vp, FuType.vppu, VpermType.vfmv_s_f, F, T, F),// vs2=0 // vs3 = vd
 
     // 16.3.3. Vector Slide1up
-    VFSLIDE1UP_VF      -> OPFVF(SrcType.fp, SrcType.X , FuType.vppu, VpermType.vfslide1up, F, T, F),// vd[0]=f[rs1], vd[i+1] = vs2[i]
+    VFSLIDE1UP_VF      -> OPFVF(SrcType.fp, SrcType.vp , FuType.vppu, VpermType.vfslide1up, F, T, F, UopDivType.VEC_FSLIDE1UP),// vd[0]=f[rs1], vd[i+1] = vs2[i]
 
     // 16.3.4. Vector Slide1down Instruction
     // vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
-    VFSLIDE1DOWN_VF    -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
+    VFSLIDE1DOWN_VF    -> OPFVF(SrcType.fp, SrcType.vp , FuType.vppu, VpermType.vfslide1down, F, T, F, UopDivType.VEC_FSLIDE1DOWN),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
   )
 
   val vset: Array[(BitPat, XSDecodeBase)] = Array(

src/main/scala/xiangshan/backend/fu/vector/VFPU.scala

@@ -249,6 +249,9 @@ class VfmaccWrapper(implicit p: Parameters)  extends XSModule{
     vfmacc(i).io.fp_a := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U)
     vfmacc(i).io.fp_b := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U)
     vfmacc(i).io.fp_c := Mux(inHs, src3(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U)
+    vfmacc(i).io.uop_idx := in.uopIdx
+    vfmacc(i).io.widen_a := 0.U // TODO :
+    vfmacc(i).io.widen_b := 0.U // TODO :
     vfmacc(i).io.frs1 := in.src(2)(63,0)
     vfmacc(i).io.is_frs1 := false.B // TODO: support vf inst
     vfmacc(i).io.op_code := in.op_code

src/main/scala/xiangshan/backend/fu/vector/VPerm.scala

@@ -108,7 +108,7 @@ class VPerm(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN
     Module(new VPPUWrapper),
     Module(new VPermWrapper)
   )
-  val select0 = io.in.bits.uop.ctrl.fuOpType === VpermType.vfmv_s_f || io.in.bits.uop.ctrl.fuOpType === VpermType.vfslide1up
+  val select0 = io.in.bits.uop.ctrl.fuOpType === VpermType.vfmv_s_f
   override val select = Seq(
     io.in.bits.uop.ctrl.fuType === FuType.vppu && select0,
     io.in.bits.uop.ctrl.fuType === FuType.vppu && !select0

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -436,8 +436,8 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   // writeback status
 //  val writebackedCounter = Mem(RobSize, UInt(log2Up(MaxUopSize * 2).W))
 //  val realDestSize = Mem(RobSize, UInt(log2Up(MaxUopSize).W))
-  val writebackedCounter = RegInit(VecInit(Seq.fill(RobSize)(0.U(log2Up(MaxUopSize).W))))
-  val realDestSize = RegInit(VecInit(Seq.fill(RobSize)(0.U(log2Up(MaxUopSize).W))))
+  val writebackedCounter = RegInit(VecInit(Seq.fill(RobSize)(0.U(log2Up(MaxUopSize+1).W))))
+  val realDestSize = RegInit(VecInit(Seq.fill(RobSize)(0.U(log2Up(MaxUopSize+1).W))))
   val fflagsDataModule = RegInit(VecInit(Seq.fill(RobSize)(0.U(5.W))))
   val vxsatDataModule = RegInit(VecInit(Seq.fill(RobSize)(false.B)))
 
@@ -1007,7 +1007,9 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
     val instCanEnqSeq = instEnqValidSeq.zip(robIdxMatchSeq).map{ case(valid, isMatch) => valid && isMatch }
     val instCanEnqFlag = Cat(instCanEnqSeq).orR
 
-    realDestSize(i) := Mux(!valid(i) && instCanEnqFlag || valid(i), realDestSize(i) + PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map{ case(writeFlag, valid) => writeFlag && valid }), 0.U)
+    realDestSize(i) := Mux(!valid(i) && instCanEnqFlag || valid(i), 
+                         realDestSize(i) + PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map{ case(writeFlag, valid) => writeFlag && valid }), 
+                         0.U)
 
 
     val enqCnt = ParallelPriorityMux(uopCanEnqSeq.reverse :+ true.B, enqWbSizeSumSeq.reverse :+ 0.U)
@@ -1017,7 +1019,11 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
     val canStuWbSeq = stdWriteback.map(writeback => writeback.valid && writeback.bits.uop.robIdx.value === i.U)
     val wbCnt = PopCount(canWbNoBlockSeq ++ canStuWbSeq)
 
-    writebackedCounter(i) := Mux(!valid(i) && instCanEnqFlag || valid(i), Mux(exceptionGen.io.out.valid && exceptionGen.io.out.bits.robIdx.value === i.U, 0.U, writebackedCounter(i) + enqCnt - wbCnt), 0.U)
+    writebackedCounter(i) := Mux(!valid(i) && instCanEnqFlag || valid(i), 
+                              Mux(exceptionGen.io.out.valid && exceptionGen.io.out.bits.robIdx.value === i.U, 
+                                0.U, 
+                                writebackedCounter(i) + enqCnt - wbCnt), 
+                              0.U)
 
     val fflagsCanWbSeq = fflags_wb.map(writeback => writeback.valid && writeback.bits.uop.robIdx.value === i.U)
     val fflagsRes = fflagsCanWbSeq.zip(fflags_wb).map{ case(canWb, wb) => Mux(canWb, wb.bits.fflags, 0.U)}.reduce(_ | _)

src/main/scala/xiangshan/package.scala

@@ -558,24 +558,27 @@ package object xiangshan {
   }
 
   object UopDivType {
-    def SCA_SIM        = "b000000".U //
-    def DIR            = "b010001".U // dirty: vset
-    def VEC_VVV        = "b010010".U // VEC_VVV
-    def VEC_VXV        = "b010011".U // VEC_VXV
-    def VEC_0XV        = "b010100".U // VEC_0XV
-    def VEC_VVW        = "b010101".U // VEC_VVW
-    def VEC_WVW        = "b010110".U // VEC_WVW
-    def VEC_VXW        = "b010111".U // VEC_VXW
-    def VEC_WXW        = "b011000".U // VEC_WXW
-    def VEC_WVV        = "b011001".U // VEC_WVV
-    def VEC_WXV        = "b011010".U // VEC_WXV
-    def VEC_EXT2       = "b011011".U // VF2 0 -> V
-    def VEC_EXT4       = "b011100".U // VF4 0 -> V
-    def VEC_EXT8       = "b011101".U // VF8 0 -> V
-    def VEC_VVM        = "b011110".U // VEC_VVM
-    def VEC_VXM        = "b011111".U // VEC_VXM
-    def VEC_SLIDE1UP   = "b100000".U // slide1up.vx
-    def VEC_MMM        = "b000000".U // VEC_MMM
+    def SCA_SIM          = "b000000".U //
+    def DIR              = "b010001".U // dirty: vset
+    def VEC_VVV          = "b010010".U // VEC_VVV
+    def VEC_VXV          = "b010011".U // VEC_VXV
+    def VEC_0XV          = "b010100".U // VEC_0XV
+    def VEC_VVW          = "b010101".U // VEC_VVW
+    def VEC_WVW          = "b010110".U // VEC_WVW
+    def VEC_VXW          = "b010111".U // VEC_VXW
+    def VEC_WXW          = "b011000".U // VEC_WXW
+    def VEC_WVV          = "b011001".U // VEC_WVV
+    def VEC_WXV          = "b011010".U // VEC_WXV
+    def VEC_EXT2         = "b011011".U // VF2 0 -> V
+    def VEC_EXT4         = "b011100".U // VF4 0 -> V
+    def VEC_EXT8         = "b011101".U // VF8 0 -> V
+    def VEC_VVM          = "b011110".U // VEC_VVM
+    def VEC_VXM          = "b011111".U // VEC_VXM
+    def VEC_SLIDE1UP     = "b100000".U // vslide1up.vx
+    def VEC_FSLIDE1UP    = "b100001".U // vfslide1up.vf
+    def VEC_SLIDE1DOWN   = "b100010".U // vslide1down.vx
+    def VEC_FSLIDE1DOWN  = "b100011".U // vfslide1down.vf
+    def VEC_MMM          = "b000000".U // VEC_MMM
     def dummy     = "b111111".U
 
     def X = BitPat("b000000")

yunsuan @ 1738376c

-Subproject commit f87d8de6dd68d65ce4645d2f40355575abc57b65
+Subproject commit 1738376cf8b4df1b4af91b3bebce784fd0a7135c