未验证 提交 397c4261 编写于 作者: Z zhanglyGit 提交者: GitHub

decode: parameter style optimization (#1985)

上级 19d2cf8f
......@@ -32,6 +32,7 @@ import scala.collection.Seq
trait VectorConstants {
val MAX_VLMUL = 8
val XP_TMP_REG_VCONFIG = 32
val FP_TMP_REG_MV = 32
val VECTOR_TMP_REG_LMUL = 32
}
......@@ -103,6 +104,10 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
UopDivType.VEC_WXV -> (lmul + lmul + 1.U) // lmul <= 4
))
val src1 = ctrl_flow.instr(19, 15)
val src2 = ctrl_flow.instr(24, 20)
val dest = ctrl_flow.instr(11, 7)
//uop div up to maxNumOfUop
val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl))
csBundle.map { case dst =>
......@@ -119,48 +124,48 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
when(isVset_u) {
csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR
csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType)
csBundle(1).ctrl.ldest := 32.U
csBundle(1).ctrl.ldest := XP_TMP_REG_VCONFIG.U
csBundle(1).ctrl.flushPipe := false.B
}
}
is(UopDivType.VEC_VVV) {
for (i <- 0 until MAX_VLMUL) {
csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
csBundle(i).ctrl.lsrc(0) := src1 + i.U
csBundle(i).ctrl.lsrc(1) := src2 + i.U
csBundle(i).ctrl.ldest := dest + i.U
csBundle(i).ctrl.uopIdx := i.U
}
}
is(UopDivType.VEC_EXT2) {
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U
csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i).ctrl.ldest := dest + (2 * i).U
csBundle(2 * i).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U
}
}
is(UopDivType.VEC_EXT4) {
for (i <- 0 until MAX_VLMUL / 4) {
csBundle(4 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(4 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i).U
csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U
csBundle(4 * i).ctrl.ldest := dest + (4 * i).U
csBundle(4 * i).ctrl.uopIdx := (4 * i).U
csBundle(4 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(4 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 1).U
csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U
csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U
csBundle(4 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(4 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 2).U
csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U
csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U
csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U
csBundle(4 * i + 3).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(4 * i + 3).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 3).U
csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U
csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U
csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U
}
}
is(UopDivType.VEC_EXT8) {
for (i <- 0 until MAX_VLMUL) {
csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20)
csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
csBundle(i).ctrl.lsrc(1) := src2
csBundle(i).ctrl.ldest := dest + i.U
csBundle(i).ctrl.uopIdx := i.U
}
}
......@@ -193,8 +198,8 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
csBundle(1).ctrl.srcType(2) := SrcType.vp
csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(1).ctrl.lsrc(1) := 0.U
csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7)
csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7)
csBundle(1).ctrl.lsrc(2) := dest
csBundle(1).ctrl.ldest := dest
csBundle(1).ctrl.fuType := FuType.vppu
csBundle(1).ctrl.fuOpType := VppuType.f2s
csBundle(1).ctrl.rfWen := false.B
......@@ -228,32 +233,32 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
for (i <- 0 until MAX_VLMUL) {
csBundle(i + 1).ctrl.srcType(0) := SrcType.fp
csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(i + 1).ctrl.ldest := dest + i.U
csBundle(i + 1).ctrl.uopIdx := i.U
}
}
is(UopDivType.VEC_VVW) {
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U
csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i).ctrl.ldest := dest + (2 * i).U
csBundle(2 * i).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U
}
}
is(UopDivType.VEC_WVW) {
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U
csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U
csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U
csBundle(2 * i).ctrl.ldest := dest + (2 * i).U
csBundle(2 * i).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U
}
}
......@@ -282,13 +287,13 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U
csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U
}
}
......@@ -317,28 +322,28 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U
csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U
}
}
is(UopDivType.VEC_WVV) {
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U
csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U
csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(2 * i).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp
csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U
csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
csBundle(2 * i + 1).ctrl.ldest := dest + i.U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U
}
}
......@@ -367,32 +372,32 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
for (i <- 0 until MAX_VLMUL / 2) {
csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U
csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U
csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U
csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp
csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp
csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U
csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
csBundle(2 * i + 2).ctrl.ldest := dest + i.U
csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U
}
}
is(UopDivType.VEC_VVM) {
csBundle(0).ctrl.srcType(2) := SrcType.vp
csBundle(0).ctrl.lsrc(2) := ctrl_flow.instr(11, 7)
csBundle(0).ctrl.lsrc(2) := dest
csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(0).ctrl.uopIdx := 0.U
for(i <- 1 until MAX_VLMUL) {
csBundle(i).ctrl.srcType(2) := SrcType.vp
csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U
csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(i).ctrl.lsrc(0) := src1 + i.U
csBundle(i).ctrl.lsrc(1) := src2 + i.U
csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(i).ctrl.uopIdx := i.U
}
csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11, 7)
csBundle(numOfUop - 1.U).ctrl.ldest := dest
}
is(UopDivType.VEC_VXM) {
/*
......@@ -419,19 +424,19 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
csBundle(1).ctrl.srcType(0) := SrcType.fp
csBundle(1).ctrl.srcType(2) := SrcType.vp
csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7)
csBundle(1).ctrl.lsrc(2) := dest
csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(1).ctrl.uopIdx := 0.U
for (i <- 1 until MAX_VLMUL) {
csBundle(i + 1).ctrl.srcType(0) := SrcType.fp
csBundle(i + 1).ctrl.srcType(2) := SrcType.vp
csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U
csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U
csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U
csBundle(i + 1).ctrl.uopIdx := i.U
}
csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11,7)
csBundle(numOfUop - 1.U).ctrl.ldest := dest
}
}
......
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