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80f76ebc
编写于
3月 15, 2023
作者:
C
czw
浏览文件
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电子邮件补丁
差异文件
func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder
上级
38c6e8e8
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
13 addition
and
13 deletion
+13
-13
src/main/scala/xiangshan/backend/decode/VecDecoder.scala
src/main/scala/xiangshan/backend/decode/VecDecoder.scala
+4
-4
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+1
-1
src/main/scala/xiangshan/backend/fu/vector/VFPU.scala
src/main/scala/xiangshan/backend/fu/vector/VFPU.scala
+8
-8
未找到文件。
src/main/scala/xiangshan/backend/decode/VecDecoder.scala
浏览文件 @
80f76ebc
...
...
@@ -426,8 +426,8 @@ object VecDecoder extends DecodeConstants {
VFREC7_V
->
OPFVV
(
SrcType
.
X
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
// 13.11. Vector Floating-Point MIN/MAX Instructions
VFMIN_VV
->
OPFVV
(
SrcType
.
vp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
VFMAX_VV
->
OPFVV
(
SrcType
.
vp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
VFMIN_VV
->
OPFVV
(
SrcType
.
vp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
fmin
,
F
,
T
,
F
),
VFMAX_VV
->
OPFVV
(
SrcType
.
vp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
fmax
,
F
,
T
,
F
),
// 13.12. Vector Floating-Point Sign-Injection Instructions
VFSGNJ_VV
->
OPFVV
(
SrcType
.
vp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
...
...
@@ -522,8 +522,8 @@ object VecDecoder extends DecodeConstants {
VFWNMSAC_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
vp
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
// 13.11. Vector Floating-Point MIN/MAX Instructions
VFMIN_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
VFMAX_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
VFMIN_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
fmin
,
F
,
T
,
F
),
VFMAX_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
fmax
,
F
,
T
,
F
),
// 13.12. Vector Floating-Point Sign-Injection Instructions
VFSGNJ_VF
->
OPFVF
(
SrcType
.
fp
,
SrcType
.
X
,
FuType
.
vfpu
,
VfpuType
.
dummy
,
F
,
T
,
F
),
...
...
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
80f76ebc
...
...
@@ -64,7 +64,7 @@ case class ExuConfig
val
intSrcCnt
=
max
(
fuConfigs
.
map
(
_
.
numIntSrc
))
private
val
fpSrcCnt
=
max
(
fuConfigs
.
map
(
_
.
numFpSrc
))
private
val
vecSrcCnt
=
max
(
fuConfigs
.
map
(
_
.
numVecSrc
))
val
fpVecSrcCnt
=
max
(
Seq
(
fpSrcCnt
,
vecSrcCnt
))
val
fpVecSrcCnt
=
max
(
fuConfigs
.
map
(
x
=>
x
.
numFpSrc
+
x
.
numVecSrc
))
val
readIntRf
=
intSrcCnt
>
0
val
readFpRf
=
fpSrcCnt
>
0
val
readVecRf
=
vecSrcCnt
>
0
...
...
src/main/scala/xiangshan/backend/fu/vector/VFPU.scala
浏览文件 @
80f76ebc
...
...
@@ -117,6 +117,8 @@ class VFPU(implicit p: Parameters) extends FPUSubModule(p(XSCoreParamsKey).VLEN)
fflagsWire
:=
LookupTree
(
s0_uopReg
.
ctrl
.
fuOpType
,
List
(
VfpuType
.
fadd
->
vfalu
.
io
.
out
.
bits
.
fflags
,
VfpuType
.
fsub
->
vfalu
.
io
.
out
.
bits
.
fflags
,
VfpuType
.
fmin
->
vfalu
.
io
.
out
.
bits
.
fflags
,
VfpuType
.
fmax
->
vfalu
.
io
.
out
.
bits
.
fflags
,
VfpuType
.
fmacc
->
vfmacc
.
io
.
out
.
bits
.
fflags
,
VfpuType
.
fdiv
->
vfdiv
.
io
.
out
.
bits
.
fflags
,
))
...
...
@@ -124,6 +126,8 @@ class VFPU(implicit p: Parameters) extends FPUSubModule(p(XSCoreParamsKey).VLEN)
dataWire
:=
LookupTree
(
s0_uopReg
.
ctrl
.
fuOpType
,
List
(
VfpuType
.
fadd
->
vfalu
.
io
.
out
.
bits
.
result
,
VfpuType
.
fsub
->
vfalu
.
io
.
out
.
bits
.
result
,
VfpuType
.
fmin
->
vfalu
.
io
.
out
.
bits
.
result
,
VfpuType
.
fmax
->
vfalu
.
io
.
out
.
bits
.
result
,
VfpuType
.
fmacc
->
vfmacc
.
io
.
out
.
bits
.
result
,
VfpuType
.
fdiv
->
vfdiv
.
io
.
out
.
bits
.
result
,
))
...
...
@@ -183,8 +187,8 @@ class VfdivWrapper(implicit p: Parameters) extends XSModule{
val
src1
=
Mux
(
in
.
srcType
(
0
)
===
SrcType
.
vp
,
in
.
src
(
0
),
VecExtractor
(
in
.
fp_format
,
in
.
src
(
0
)))
val
src2
=
Mux
(
in
.
srcType
(
1
)
===
SrcType
.
vp
,
in
.
src
(
1
),
VecExtractor
(
in
.
fp_format
,
in
.
src
(
1
)))
for
(
i
<-
0
until
NumAdder
)
{
vfdiv
(
i
).
io
.
opa_i
:=
Mux
(
inHs
,
src2
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfdiv
(
i
).
io
.
opb_i
:=
Mux
(
inHs
,
src1
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfdiv
(
i
).
io
.
opa_i
:=
Mux
(
inHs
,
src2
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfdiv
(
i
).
io
.
is_vec_i
:=
true
.
B
// If you can enter, it must be vector
vfdiv
(
i
).
io
.
rm_i
:=
in
.
round_mode
vfdiv
(
i
).
io
.
fp_format_i
:=
Mux
(
inHs
,
in
.
fp_format
,
3.
U
(
2.
W
))
...
...
@@ -292,8 +296,8 @@ class VfaluWrapper(implicit p: Parameters) extends XSModule{
val
src1
=
Mux
(
in
.
srcType
(
0
)
===
SrcType
.
vp
,
in
.
src
(
0
),
VecExtractor
(
in
.
fp_format
,
in
.
src
(
0
)))
val
src2
=
Mux
(
in
.
srcType
(
1
)
===
SrcType
.
vp
,
in
.
src
(
1
),
VecExtractor
(
in
.
fp_format
,
in
.
src
(
1
)))
for
(
i
<-
0
until
NumAdder
)
{
vfalu
(
i
).
io
.
fp_
a
:=
Mux
(
inHs
,
src1
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfalu
(
i
).
io
.
fp_
b
:=
Mux
(
inHs
,
src2
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfalu
(
i
).
io
.
fp_
b
:=
Mux
(
inHs
,
src1
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfalu
(
i
).
io
.
fp_
a
:=
Mux
(
inHs
,
src2
(
AdderWidth
*
(
i
+
1
)
-
1
,
AdderWidth
*
i
),
0.
U
)
vfalu
(
i
).
io
.
is_vec
:=
true
.
B
// If you can enter, it must be vector
vfalu
(
i
).
io
.
round_mode
:=
in
.
round_mode
vfalu
(
i
).
io
.
fp_format
:=
Mux
(
inHs
,
in
.
fp_format
,
3.
U
(
2.
W
))
...
...
@@ -315,11 +319,7 @@ class VfaluWrapper(implicit p: Parameters) extends XSModule{
val
s1_fflags
=
RegEnable
(
s0_fflags
,
validPipe
(
Latency
-
2
))
out
.
fflags
:=
s1_fflags
val
s0_result
=
LookupTree
(
s0_sew
(
1
,
0
),
List
(
"b01"
.
U
->
VecInit
(
vfalu
.
map
(
_
.
io
.
fp_f16_result
)).
asUInt
(),
"b10"
.
U
->
VecInit
(
vfalu
.
map
(
_
.
io
.
fp_f32_result
)).
asUInt
(),
"b11"
.
U
->
VecInit
(
vfalu
.
map
(
_
.
io
.
fp_f64_result
)).
asUInt
(),
))
val
s0_result
=
VecInit
(
vfalu
.
map
(
_
.
io
.
fp_result
)).
asUInt
()
val
s1_result
=
RegEnable
(
s0_result
,
validPipe
(
Latency
-
2
))
out
.
result
:=
s1_result
...
...
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