func(vslide1up): support vslide1up instruction (#1990)

* func(decode+VIPU): support vslide1up instruction

* bump(yunsuan): func(VFADD) & VIPU type & test(VPERM)

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -101,7 +101,8 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
     UopDivType.VEC_VXW -> (lmul + lmul + 1.U),     // lmul <= 4
     UopDivType.VEC_WXW -> (lmul + lmul + 1.U),     // lmul <= 4
     UopDivType.VEC_WVV -> (lmul + lmul),           // lmul <= 4
-    UopDivType.VEC_WXV -> (lmul + lmul + 1.U)      // lmul <= 4
+    UopDivType.VEC_WXV -> (lmul + lmul + 1.U),     // lmul <= 4
+    UopDivType.VEC_SLIDE1UP -> (lmul + 1.U)
   ))
 
   val src1 = ctrl_flow.instr(19, 15)
@@ -438,6 +439,42 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
       }
       csBundle(numOfUop - 1.U).ctrl.ldest := dest
     }
+    is(UopDivType.VEC_SLIDE1UP) {
+      /*
+      FMV.D.X
+       */
+      csBundle(0).ctrl.srcType(0) := SrcType.reg
+      csBundle(0).ctrl.srcType(1) := SrcType.imm
+      csBundle(0).ctrl.lsrc(1) := 0.U
+      csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U
+      csBundle(0).ctrl.fuType := FuType.i2f
+      csBundle(0).ctrl.rfWen := false.B
+      csBundle(0).ctrl.fpWen := true.B
+      csBundle(0).ctrl.vecWen := false.B
+      csBundle(0).ctrl.fpu.isAddSub := false.B
+      csBundle(0).ctrl.fpu.typeTagIn := FPU.D
+      csBundle(0).ctrl.fpu.typeTagOut := FPU.D
+      csBundle(0).ctrl.fpu.fromInt := true.B
+      csBundle(0).ctrl.fpu.wflags := false.B
+      csBundle(0).ctrl.fpu.fpWen := true.B
+      csBundle(0).ctrl.fpu.div := false.B
+      csBundle(0).ctrl.fpu.sqrt := false.B
+      csBundle(0).ctrl.fpu.fcvt := false.B
+      //LMUL
+      csBundle(1).ctrl.srcType(0) := SrcType.fp
+      csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U
+      csBundle(1).ctrl.lsrc(2) := dest
+      csBundle(1).ctrl.ldest := dest
+      csBundle(1).ctrl.uopIdx := 0.U
+      for (i <- 1 until MAX_VLMUL) {
+        csBundle(i + 1).ctrl.srcType(0) := SrcType.vp
+        csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U
+        csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U
+        csBundle(i + 1).ctrl.lsrc(2) := dest + i.U
+        csBundle(i + 1).ctrl.ldest := dest + i.U
+        csBundle(i + 1).ctrl.uopIdx := i.U
+      }
+    }
   }
 
   //uops dispatch

src/main/scala/xiangshan/backend/decode/VecDecoder.scala

@@ -360,7 +360,7 @@ object VecDecoder extends DecodeConstants {
     VREMU_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
 
     VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
-    VSLIDE1UP_VX   -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
+    VSLIDE1UP_VX   -> OPMVX(T, FuType.vipu, VipuType.vslide1up, F, T, F, UopDivType.VEC_SLIDE1UP),
     VWADD_VX       -> OPMVX(F, FuType.vialuF, VialuFixType.vwadd_vv, F, T, F, UopDivType.VEC_VXW),
     VWADD_WX       -> OPMVX(F, FuType.vialuF, VialuFixType.vwadd_wv, F, T, F, UopDivType.VEC_WXW),
     VWADDU_VX      -> OPMVX(F, FuType.vialuF, VialuFixType.vwaddu_vv, F, T, F, UopDivType.VEC_VXW),

src/main/scala/xiangshan/backend/fu/vector/VIPU.scala

@@ -80,6 +80,7 @@ class VIAluDecoder (implicit p: Parameters) extends XSModule {
 
     VipuType.viota_m -> Cat(VAluOpcode.viota, mask, mask, uSew).asUInt(),
     VipuType.vid_v -> Cat(VAluOpcode.vid, uSew, uSew, uSew).asUInt(),
+    VipuType.vslide1up -> Cat(VAluOpcode.vslide1up, uSew, uSew, uSew).asUInt()
 
   )).asTypeOf(new VIAluDecodeResultBundle)
 

src/main/scala/xiangshan/package.scala

@@ -558,29 +558,30 @@ package object xiangshan {
   }
 
   object UopDivType {
-    def SCA_SIM        = "b00000".U // 
-    def DIR            = "b10001".U // dirty: vset
-    def VEC_VVV        = "b10010".U // VEC_VVV
-    def VEC_VXV        = "b10011".U // VEC_VXV
-    def VEC_0XV        = "b10100".U // VEC_0XV
-    def VEC_VVW        = "b10101".U // VEC_VVW
-    def VEC_WVW        = "b10110".U // VEC_WVW
-    def VEC_VXW        = "b10111".U // VEC_VXW
-    def VEC_WXW        = "b11000".U // VEC_WXW
-    def VEC_WVV        = "b11001".U // VEC_WVV
-    def VEC_WXV        = "b11010".U // VEC_WXV
-    def VEC_EXT2       = "b11011".U // VF2 0 -> V
-    def VEC_EXT4       = "b11100".U // VF4 0 -> V
-    def VEC_EXT8       = "b11101".U // VF8 0 -> V
-    def VEC_VVM        = "b11110".U // VEC_VVM
-    def VEC_VXM        = "b11111".U // VEC_VXM
-    def VEC_MMM        = "b00000".U // VEC_MMM
-    def dummy = "b11111".U
-
-    def X = BitPat("b00000")
-
-    def apply() = UInt(5.W)
-    def needSplit(UopDivType: UInt) = UopDivType(4)
+    def SCA_SIM        = "b000000".U //
+    def DIR            = "b010001".U // dirty: vset
+    def VEC_VVV        = "b010010".U // VEC_VVV
+    def VEC_VXV        = "b010011".U // VEC_VXV
+    def VEC_0XV        = "b010100".U // VEC_0XV
+    def VEC_VVW        = "b010101".U // VEC_VVW
+    def VEC_WVW        = "b010110".U // VEC_WVW
+    def VEC_VXW        = "b010111".U // VEC_VXW
+    def VEC_WXW        = "b011000".U // VEC_WXW
+    def VEC_WVV        = "b011001".U // VEC_WVV
+    def VEC_WXV        = "b011010".U // VEC_WXV
+    def VEC_EXT2       = "b011011".U // VF2 0 -> V
+    def VEC_EXT4       = "b011100".U // VF4 0 -> V
+    def VEC_EXT8       = "b011101".U // VF8 0 -> V
+    def VEC_VVM        = "b011110".U // VEC_VVM
+    def VEC_VXM        = "b011111".U // VEC_VXM
+    def VEC_SLIDE1UP   = "b100000".U // slide1up.vx
+    def VEC_MMM        = "b000000".U // VEC_MMM
+    def dummy     = "b111111".U
+
+    def X = BitPat("b000000")
+
+    def apply() = UInt(6.W)
+    def needSplit(UopDivType: UInt) = UopDivType(4) || UopDivType(5)
   }
 
   object ExceptionNO {

yunsuan @ 8a8b932f

-Subproject commit 52319b8a748f6ddf4ff7f431f0fc4ef22ca28ac2
+Subproject commit 8a8b932fd36d0721bfe93f8f482340307e684fa6