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提交 75f001f9 编写于 作者: C czw
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func(UopDivType): support VEC_0MX/VEC_VMV/VEC_0MM

上级 7720a376
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Showing with 77 addition and 11 deletion
src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
浏览文件 @ 75f001f9
......@@ -116,6 +116,8 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
UopDivType.VEC_ISLIDEUP -> numOfUopVslide,
UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U),
UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide,
UopDivType.VEC_0MX -> (lmul +& 1.U),
UopDivType.VEC_VMV -> (Cat(lmul, 0.U(1.W)) -1.U),
))
val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15))
......@@ -732,6 +734,67 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
}
}
}
is(UopDivType.VEC_0MX) {
// LMUL
for (i <- 0 until MAX_VLMUL) {
val lsrc0 = if (i==0) 0.U else (VECTOR_TMP_REG_LMUL + i - 1).U
val ldest = (VECTOR_TMP_REG_LMUL + i).U
csBundle(i).ctrl.srcType(0) := SrcType.vp
csBundle(i).ctrl.srcType(1) := SrcType.vp
csBundle(i).ctrl.rfWen := false.B
csBundle(i).ctrl.vecWen := true.B
csBundle(i).ctrl.lsrc(0) := lsrc0
csBundle(i).ctrl.lsrc(1) := src2
// csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare
csBundle(i).ctrl.ldest := ldest
csBundle(i).ctrl.uopIdx := i.U
}
csBundle(lmul-1.U).ctrl.vecWen := false.B
csBundle(lmul-1.U).ctrl.fpWen := true.B
csBundle(lmul-1.U).ctrl.ldest := FP_TMP_REG_MV.U
// FMV_X_D
csBundle(lmul).ctrl.srcType(0) := SrcType.fp
csBundle(lmul).ctrl.srcType(1) := SrcType.imm
csBundle(lmul).ctrl.lsrc(0) := FP_TMP_REG_MV.U
csBundle(lmul).ctrl.lsrc(1) := 0.U
csBundle(lmul).ctrl.ldest := dest
csBundle(lmul).ctrl.fuType := FuType.fmisc
csBundle(lmul).ctrl.rfWen := true.B
csBundle(lmul).ctrl.fpWen := false.B
csBundle(lmul).ctrl.vecWen := false.B
csBundle(lmul).ctrl.fpu.isAddSub := false.B
csBundle(lmul).ctrl.fpu.typeTagIn := FPU.D
csBundle(lmul).ctrl.fpu.typeTagOut := FPU.D
csBundle(lmul).ctrl.fpu.fromInt := false.B
csBundle(lmul).ctrl.fpu.wflags := false.B
csBundle(lmul).ctrl.fpu.fpWen := false.B
csBundle(lmul).ctrl.fpu.div := false.B
csBundle(lmul).ctrl.fpu.sqrt := false.B
csBundle(lmul).ctrl.fpu.fcvt := false.B
}
is(UopDivType.VEC_VMV) {
// LMUL
for (i <- 0 until MAX_VLMUL) {
val lsrc0 = if (i==0) 0.U else (VECTOR_TMP_REG_LMUL + i - 1).U
csBundle(i*2+0).ctrl.srcType(0) := SrcType.vp
csBundle(i*2+0).ctrl.srcType(1) := SrcType.vp
csBundle(i*2+0).ctrl.lsrc(0) := lsrc0
csBundle(i*2+0).ctrl.lsrc(1) := src2
csBundle(i).ctrl.lsrc(2) := dest + i.U
csBundle(i*2+0).ctrl.ldest := dest + i.U
csBundle(i*2+0).ctrl.uopIdx := (i*2+0).U
csBundle(i*2+1).ctrl.srcType(0) := SrcType.vp
csBundle(i*2+1).ctrl.srcType(1) := SrcType.vp
csBundle(i*2+1).ctrl.lsrc(0) := lsrc0
csBundle(i*2+1).ctrl.lsrc(1) := src2
// csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare
csBundle(i*2+1).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U
csBundle(i*2+1).ctrl.uopIdx := (i*2+1).U
}
}
}
//uops dispatch
......
src/main/scala/xiangshan/backend/decode/VecDecoder.scala
浏览文件 @ 75f001f9
......@@ -273,17 +273,17 @@ object VecDecoder extends DecodeConstants {
)
val opmvv: Array[(BitPat, XSDecodeBase)] = Array(
VAADD_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vaadd_vv, F, T, F),
VAADDU_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vaaddu_vv, F, T, F),
VASUB_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vasub_vv, F, T, F),
VASUBU_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vasubu_vv, F, T, F),
VAADD_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vaadd_vv, F, T, F, UopDivType.VEC_VVV),
VAADDU_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vaaddu_vv, F, T, F, UopDivType.VEC_VVV),
VASUB_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vasub_vv, F, T, F, UopDivType.VEC_VVV),
VASUBU_VV -> OPMVV(T, FuType.vialuF, VialuFixType.vasubu_vv, F, T, F, UopDivType.VEC_VVV),
VCOMPRESS_VM -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
VCPOP_M -> OPMVV(T, FuType.vipu, VipuType.vcpop_m, T, F, F),
VCPOP_M -> OPMVV(T, FuType.vipu, VipuType.vcpop_m, T, F, F, UopDivType.VEC_0MX),
VDIV_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
VDIVU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
VFIRST_M -> OPMVV(T, FuType.vipu, VipuType.vfirst_m, T, F, F),
VID_V -> OPMVV(T, FuType.vipu, VipuType.vid_v, F, T, F),
VIOTA_M -> OPMVV(T, FuType.vipu, VipuType.viota_m, F, T, F),
VFIRST_M -> OPMVV(T, FuType.vipu, VipuType.vfirst_m, T, F, F, UopDivType.VEC_0MX),
VID_V -> OPMVV(T, FuType.vipu, VipuType.vid_v, F, T, F, UopDivType.VEC_VMV),
VIOTA_M -> OPMVV(T, FuType.vipu, VipuType.viota_m, F, T, F, UopDivType.VEC_VMV),
// VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
......@@ -296,9 +296,9 @@ object VecDecoder extends DecodeConstants {
VMORN_MM -> OPMVV(T, FuType.vialuF, VialuFixType.vmorn_mm, F, T, F, UopDivType.VEC_MMM),
VMXNOR_MM -> OPMVV(T, FuType.vialuF, VialuFixType.vmxnor_mm, F, T, F, UopDivType.VEC_MMM),
VMXOR_MM -> OPMVV(T, FuType.vialuF, VialuFixType.vmxor_mm, F, T, F, UopDivType.VEC_MMM),
VMSBF_M -> OPMVV(T, FuType.vipu, VipuType.vmsbf_m, F, T, F),
VMSIF_M -> OPMVV(T, FuType.vipu, VipuType.vmsif_m, F, T, F),
VMSOF_M -> OPMVV(T, FuType.vipu, VipuType.vmsof_m, F, T, F),
VMSBF_M -> OPMVV(T, FuType.vipu, VipuType.vmsbf_m, F, T, F, UopDivType.VEC_0MM),
VMSIF_M -> OPMVV(T, FuType.vipu, VipuType.vmsif_m, F, T, F, UopDivType.VEC_0MM),
VMSOF_M -> OPMVV(T, FuType.vipu, VipuType.vmsof_m, F, T, F, UopDivType.VEC_0MM),
VMUL_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
VMULH_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
VMULHSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F),
......
src/main/scala/xiangshan/package.scala
浏览文件 @ 75f001f9
......@@ -583,6 +583,9 @@ package object xiangshan {
def VEC_ISLIDEUP = "b100110".U // VEC_ISLIDEUP
def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN
def VEC_ISLIDEDOWN = "b101000".U // VEC_ISLIDEDOWN
def VEC_0MX = "b101001".U // VEC_0MX 0MV
def VEC_VMV = "b101010".U // VEC_VMV VMV
def VEC_0MM = "b000000".U // VEC_0MM
def VEC_MMM = "b000000".U // VEC_MMM
def dummy = "b111111".U
......
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