uop.ctrl.replayInst in lq should be replayed when load_s2 update lq
i.e. load_s2.io.out.valid

It will save time for store_req generation in dcache Mainpipe, which is
at the beginning of a critical path

It should fix the timing problem caused by ldld violation check and
forward error check

Now we update data field (fwd data, uop) in load queue when load_s2
is valid. It will help to on lq wen fanout problem.

State flags will be treated differently. They are still updated
accurately according to loadIn.valid

Co-authored-by: NZiyue Zhang <zhangziyue21b@ict.ac.cn>

In previous design, sbuffer valid entry select and
sbuffer data write are in the same cycle, which
caused huge fanout. An extra write stage is added to
solve this problem.

Now sbuffer enq logic is divided into 3 stages:

sbuffer_in_s0:
* read data and meta from store queue
* store them in 2 entry fifo queue

sbuffer_in_s1:
* read data and meta from fifo queue
* update sbuffer meta (vtag, ptag, flag)
* prevert that line from being sent to dcache (add a block condition)
* prepare cacheline level write enable signal, RegNext() data and mask

sbuffer_in_s2:
* use cacheline level buffer to update sbuffer data and mask
* remove dcache write block (if there is)

* MainPipe: reduce fanout by duplicating registers

* MainPipe: fix wrong assert
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

Now sbuffer deq logic is divided into 2 stages:

sbuffer_out_s0:
* read data and meta from sbuffer
* RegNext() them
* set line state to inflight

sbuffer_out_s1:
* send write req to dcache

sbuffer_out_extra:
* receive write result from dcache
* update line state

misc: bump chisel-circt

frontend: Add ChiselDB records

frontend bump nanhu

* add 1 stage for mmio_state before sending request to MMIO bus
* check whether the last fetch packet commit all its intructions (the
result of execution path has been decided)
* avoid speculative execution to MMIO bus

* when f3_flush is enabled, f3_lastHalf_disable is still set and
influence the next packet

* Under the circumstance that 2 continuous ftq reqs both have last half
RVI, but the f3_lastHalf.valid cancel condition in wb-stage is set by
!f3_lastHalf.valid， which makes the miss pred f3_lastHalf req has not
been flushed.

* reset state_vec register in replacement

* latch arbiter out before entering dataArray, without which will causes
write valid ( state_reg ) fanout to every bit of WEM and D of SRAM