- 17 11月, 2020 6 次提交
- 16 11月, 2020 4 次提交
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由 LinJiawei 提交于
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由 ZhangZifei 提交于
the log in Alu will not have different name, so move it into AluExeUnit module
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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- 15 11月, 2020 1 次提交
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由 LinJiawei 提交于
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- 14 11月, 2020 1 次提交
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由 ZhangZifei 提交于
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- 13 11月, 2020 2 次提交
- 12 11月, 2020 3 次提交
- 11 11月, 2020 4 次提交
- 10 11月, 2020 3 次提交
- 09 11月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 08 11月, 2020 4 次提交
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
The roqIdx produced by storeQueue may not always be older than roq since store instructions writeback to store queue and roq at the same cycle. After that, if roq commits some instructions after the store, roqIdx given by Roq will be older than that given by the store queue. Thus, we set valid for roq.io.commitRoqIndex when roq is not in walking to ensure that roq always gives the oldest roqIdx
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由 LinJiawei 提交于
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- 07 11月, 2020 1 次提交
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由 LinJiawei 提交于
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- 06 11月, 2020 2 次提交
- 05 11月, 2020 3 次提交
- 04 11月, 2020 1 次提交
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由 zoujr 提交于
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- 03 11月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 02 11月, 2020 3 次提交
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由 ZhangZifei 提交于
This reverts commit 58fca539.
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由 Yinan Xu 提交于
Previously, CSR determines interrupt by redirect.valid && interruptBitEnable. However, interruptBitEnable does not mean the redirect is an interrupt. We reuse isFlushPipe in Roq to represent an interrupt for CSR.
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由 Yinan Xu 提交于
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