[WIP] fix bug in FloatBlock and MemBlock io

src/main/scala/xiangshan/XSCore.scala

@@ -276,47 +276,50 @@ class XSCore()(implicit p: config.Parameters) extends LazyModule {
   lazy val module = new XSCoreImp(this)
 }
 
-class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter {
+class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
+  with HasXSParameter
+  with HasExeBlockHelper
+{
   val io = IO(new Bundle {
     val externalInterrupt = new ExternalInterruptIO
   })
 
   // to fast wake up fp, mem rs
-  val intBlockFastWakeUpFp = intExuConfigs.count(cfg => cfg.hasCertainLatency && cfg.writeFpRf)
-  val intBlockSlowWakeUpFp = intExuConfigs.count(cfg => cfg.hasUncertainlatency && cfg.writeFpRf)
-  val intBlockFastWakeUpInt = intExuConfigs.count(cfg => cfg.hasCertainLatency && cfg.writeIntRf)
-  val intBlockSlowWakeUpInt = intExuConfigs.count(cfg => cfg.hasUncertainlatency && cfg.writeIntRf)
+  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
+  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
+  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
+  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
 
-  val fpBlockFastWakeUpFp = fpExuConfigs.count(cfg => cfg.hasCertainLatency && cfg.writeFpRf)
-  val fpBlockSlowWakeUpFp = fpExuConfigs.count(cfg => cfg.hasUncertainlatency && cfg.writeFpRf)
-  val fpBlockFastWakeUpInt = fpExuConfigs.count(cfg => cfg.hasCertainLatency && cfg.writeIntRf)
-  val fpBlockSlowWakeUpInt = fpExuConfigs.count(cfg => cfg.hasUncertainlatency && cfg.writeIntRf)
+  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
+  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
+  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
+  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
 
   val frontend = Module(new Frontend)
   val ctrlBlock = Module(new CtrlBlock)
   val integerBlock = Module(new IntegerBlock(
-    fastWakeUpInCnt = fpBlockFastWakeUpInt,
-    slowWakeUpInCnt = fpBlockSlowWakeUpInt + exuParameters.LduCnt,
-    fastFpOutCnt = intBlockFastWakeUpFp,
-    slowFpOutCnt = intBlockSlowWakeUpFp,
-    fastIntOutCnt = intBlockFastWakeUpInt,
-    slowIntOutCnt = intBlockSlowWakeUpInt
+    fastWakeUpIn = fpBlockFastWakeUpInt,
+    slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs,
+    fastFpOut = intBlockFastWakeUpFp,
+    slowFpOut = intBlockSlowWakeUpFp,
+    fastIntOut = intBlockFastWakeUpInt,
+    slowIntOut = intBlockSlowWakeUpInt
   ))
   val floatBlock = Module(new FloatBlock(
-    fastWakeUpInCnt = intBlockFastWakeUpFp,
-    slowWakeUpInCnt = intBlockSlowWakeUpFp + exuParameters.LduCnt,
-    fastFpOutCnt = fpBlockFastWakeUpFp,
-    slowFpOutCnt = fpBlockSlowWakeUpFp,
-    fastIntOutCnt = fpBlockFastWakeUpInt,
-    slowIntOutCnt = fpBlockSlowWakeUpInt
+    fastWakeUpIn = intBlockFastWakeUpFp,
+    slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs,
+    fastFpOut = fpBlockFastWakeUpFp,
+    slowFpOut = fpBlockSlowWakeUpFp,
+    fastIntOut = fpBlockFastWakeUpInt,
+    slowIntOut = fpBlockSlowWakeUpInt
   ))
   val memBlock = Module(new MemBlock(
-    fastWakeUpInCnt = intBlockFastWakeUpInt + intBlockFastWakeUpFp + fpBlockFastWakeUpInt + fpBlockFastWakeUpFp,
-    slowWakeUpInCnt = intBlockSlowWakeUpInt + intBlockSlowWakeUpFp + fpBlockSlowWakeUpInt + fpBlockSlowWakeUpFp,
-    fastFpOutCnt = 0,
-    slowFpOutCnt = exuParameters.LduCnt,
-    fastIntOutCnt = 0,
-    slowIntOutCnt = exuParameters.LduCnt
+    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
+    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
+    fastFpOut = Seq(),
+    slowFpOut = loadExuConfigs,
+    fastIntOut = Seq(),
+    slowIntOut = loadExuConfigs
   ))
 
   val dcache = outer.dcache.module

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -15,19 +15,19 @@ class FpBlockToCtrlIO extends XSBundle {
 
 class FloatBlock
 (
-  fastWakeUpInCnt: Int,
-  slowWakeUpInCnt: Int,
-  fastFpOutCnt: Int,
-  slowFpOutCnt: Int,
-  fastIntOutCnt: Int,
-  slowIntOutCnt: Int
+  fastWakeUpIn: Seq[ExuConfig],
+  slowWakeUpIn: Seq[ExuConfig],
+  fastFpOut: Seq[ExuConfig],
+  slowFpOut: Seq[ExuConfig],
+  fastIntOut: Seq[ExuConfig],
+  slowIntOut: Seq[ExuConfig]
 ) extends XSModule with NeedImpl {
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToFpBlockIO)
     val toCtrlBlock = new FpBlockToCtrlIO
 
-    val wakeUpIn = new WakeUpBundle(fastWakeUpInCnt, slowWakeUpInCnt)
-    val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOutCnt, slowFpOutCnt))
-    val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOutCnt, slowIntOutCnt))
+    val wakeUpIn = new WakeUpBundle(fastWakeUpIn.size, slowWakeUpIn.size)
+    val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOut.size, slowFpOut.size))
+    val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOut.size, slowIntOut.size))
   })
 }

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -36,21 +36,21 @@ class MemBlockCSRIO extends XSBundle {
 
 class MemBlock
 (
-  fastWakeUpInCnt: Int,
-  slowWakeUpInCnt: Int,
-  fastFpOutCnt: Int,
-  slowFpOutCnt: Int,
-  fastIntOutCnt: Int,
-  slowIntOutCnt: Int
+  fastWakeUpIn: Seq[ExuConfig],
+  slowWakeUpIn: Seq[ExuConfig],
+  fastFpOut: Seq[ExuConfig],
+  slowFpOut: Seq[ExuConfig],
+  fastIntOut: Seq[ExuConfig],
+  slowIntOut: Seq[ExuConfig]
 ) extends XSModule with NeedImpl {
 
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToLsBlockIO)
     val toCtrlBlock = new LsBlockToCtrlIO
 
-    val wakeUpIn = new WakeUpBundle(fastWakeUpInCnt, slowWakeUpInCnt)
-    val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOutCnt, slowFpOutCnt))
-    val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOutCnt, slowIntOutCnt))
+    val wakeUpIn = new WakeUpBundle(fastWakeUpIn.size, slowWakeUpIn.size)
+    val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOut.size, slowFpOut.size))
+    val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOut.size, slowIntOut.size))
 
     val ptw = new TlbPtwIO
     // TODO: dcache should be inside MemBlock

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -209,6 +209,9 @@ object Exu {
   val ldExeUnitCfg = ExuConfig("LoadExu", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0)
   val stExeUnitCfg = ExuConfig("StoreExu", Seq(stuCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue)
 
+  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(ldExeUnitCfg)
+  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(stExeUnitCfg)
+
   val intExuConfigs = jumpExeUnitCfg +: (
     Seq.fill(exuParameters.AluCnt)(aluExeUnitCfg) ++
       Seq.fill(exuParameters.MduCnt)(mulDivExeUnitCfg)