xscore: use integerBlock,memBlock,floatBlock

src/main/scala/xiangshan/XSCore.scala

@@ -280,9 +280,11 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter
     val externalInterrupt = new ExternalInterruptIO
   })
 
-  val front = Module(new Frontend)
-  val backend = Module(new Backend)
-  val mem = Module(new Memend)
+  val frontend = Module(new Frontend)
+  val ctrlBlock = Module(new CtrlBlock)
+  val integerBlock = Module(new IntegerBlock)
+  val floatBlock = Module(new FloatBlock)
+  val memBlock = Module(new MemBlock)
 
   val dcache = outer.dcache.module
   val uncache = outer.uncache.module
@@ -290,29 +292,35 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter
   val ptw = outer.ptw.module
   val icache = Module(new ICache)
 
-  front.io.backend <> backend.io.frontend
-  front.io.icacheResp <> icache.io.resp
-  front.io.icacheToTlb <> icache.io.tlb
-  icache.io.req <> front.io.icacheReq
-  icache.io.flush <> front.io.icacheFlush
+  frontend.io.backend <> ctrlBlock.io.frontend
+  frontend.io.icacheResp <> icache.io.resp
+  frontend.io.icacheToTlb <> icache.io.tlb
+  icache.io.req <> frontend.io.icacheReq
+  icache.io.flush <> frontend.io.icacheFlush
 
   icache.io.mem_acquire <> l1pluscache.io.req
   l1pluscache.io.resp <> icache.io.mem_grant
   l1pluscache.io.flush := icache.io.l1plusflush
-  icache.io.fencei := backend.io.fencei
-
-  mem.io.backend   <> backend.io.mem
-  io.externalInterrupt <> backend.io.externalInterrupt
-
-  ptw.io.tlb(0) <> mem.io.ptw
-  ptw.io.tlb(1) <> front.io.ptw
-  ptw.io.sfence <> backend.io.sfence
-  ptw.io.csr <> backend.io.tlbCsrIO
-
-  dcache.io.lsu.load    <> mem.io.loadUnitToDcacheVec
-  dcache.io.lsu.lsroq   <> mem.io.loadMiss
-  dcache.io.lsu.atomics <> mem.io.atomics
-  dcache.io.lsu.store   <> mem.io.sbufferToDcache
-  uncache.io.lsroq      <> mem.io.uncache
+  icache.io.fencei := integerBlock.io.fencei
+
+  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
+  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
+  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
+  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
+  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
+  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
+
+  io.externalInterrupt <> integerBlock.io.externalInterrupt
+
+  ptw.io.tlb(0) <> memBlock.io.ptw
+  ptw.io.tlb(1) <> frontend.io.ptw
+  ptw.io.sfence <> integerBlock.io.sfence
+  ptw.io.csr <> integerBlock.io.tlbCsrIO
+
+  dcache.io.lsu.load    <> memBlock.io.dcache.loadUnitToDcacheVec
+  dcache.io.lsu.lsroq   <> memBlock.io.dcache.loadMiss
+  dcache.io.lsu.atomics <> memBlock.io.dcache.atomics
+  dcache.io.lsu.store   <> memBlock.io.dcache.sbufferToDcache
+  uncache.io.lsroq      <> memBlock.io.dcache.uncache
 
 }

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -10,7 +10,7 @@ import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
 import xiangshan.backend.issue.ReservationStationNew
 import xiangshan.backend.regfile.RfReadPort
-import xiangshan.backend.roq.{Roq, RoqPtr}
+import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO}
 import xiangshan.mem._
 import xiangshan.backend.fu.FunctionUnit._
 
@@ -19,6 +19,7 @@ class CtrlToIntBlockIO extends XSBundle {
   val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput))
   val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
   val redirect = ValidIO(new Redirect)
+  val roqToCSR = new RoqCSRIO
 }
 
 class CtrlToFpBlockIO extends XSBundle {
@@ -127,6 +128,7 @@ class CtrlBlock
   dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl
   dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData
 
+  io.toIntBlock.roqToCSR <> roq.io.csr
   // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe)
   // fpBusyTable.flush := flush
   // intBusyTable.flush := flush

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -20,8 +20,11 @@ class FloatBlock extends XSModule {
     val fromCtrlBlock = Flipped(new CtrlToFpBlockIO)
     val toCtrlBlock = new FpBlockToCtrlIO
     // TODO: ramdonly set 5
+    // writeback from other blocks
     val writebackData = Vec(5, Input(UInt(XLEN.W)))
     val extraListenPorts = Vec(5, Flipped(DecoupledIO(new ExuOutput)))
+    // output writeback (wakeup other blocks)
+    // val 
   })
 
   // floating-point regfile

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -17,13 +17,21 @@ class IntBlockToCtrlIO extends XSBundle {
   val tlbCsrIO = Output(new TlbCsrBundle)
 }
 
+
 class IntegerBlock extends XSModule {
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToIntBlockIO)
     val toCtrlBlock = new IntBlockToCtrlIO
     // TODO: ramdonly set 5
+    // writeback from other blocks
     val writebackData = Vec(5, Input(UInt(XLEN.W)))
     val extraListenPorts = Vec(5, Flipped(DecoupledIO(new ExuOutput)))
+    // output writeback (wakeup other blocks)
+    // val 
+    val externalInterrupt = new ExternalInterruptIO
+    val sfence = Output(new SfenceBundle)
+    val fencei = Output(Bool())
+    val tlbCsrIO = Output(new TlbCsrBundle)
   })
 
   // integer regfile
@@ -45,7 +53,6 @@ class IntegerBlock extends XSModule {
   val extraListenPorts = exuConfigs.zip(exeWbReqs).filter(x => x._1.hasUncertainlatency && x._1.writeIntRf).map(_._2)
 
   val rsConfigs = Seq(0, -1, -1, 0, 0, 0, 0)
-
   val reservationStations  = exuConfigs.zipWithIndex.map({ case (cfg, i) =>
     val rs = Module(new ReservationStationNew(cfg, 5, 6, fixedDelay = rsConfigs(i), feedback = false))
 
@@ -68,6 +75,20 @@ class IntegerBlock extends XSModule {
     rs
   })
 
+  // IOs for special execution units
+  // CSR is in jmpExeUnit
+  io.fromCtrlBlock.roqToCSR.intrBitSet := jmpExeUnit.io.csrOnly.interrupt
+  io.fromCtrlBlock.roqToCSR.trapTarget := jmpExeUnit.io.csrOnly.trapTarget
+  jmpExeUnit.fflags := io.fromCtrlBlock.roqToCSR.fflags
+  jmpExeUnit.dirty_fs := io.fromCtrlBlock.roqToCSR.dirty_fs
+
+  jmpExeUnit.io.csrOnly.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException
+  jmpExeUnit.io.csrOnly.exception.bits := roq.io.exception
+
+  jmpExeUnit.io.csrOnly.externalInterrupt := io.externalInterrupt
+  jmpExeUnit.io.csrOnly.memExceptionVAddr := io.mem.exceptionAddr.vaddr
+  jmpExeUnit.fenceToSbuffer <> io.mem.fenceToSbuffer
+
   // TODO: connect writeback
   // val wbArbiter = 
 }

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -44,8 +44,10 @@ class MemBlock extends XSModule {
     // TODO: dcache should be inside MemBlock
     val dcache = new MemBlockToDcacheIO
     val csr = new MemBlockCSRIO
+    // writeback from other blocks
     val writebackData = Vec(5, Input(UInt(XLEN.W)))
     val extraListenPorts = Vec(5, Flipped(DecoupledIO(new ExuOutput)))
+    // output writeback
   })
 
   val loadUnits = Array.tabulate(exuParameters.LduCnt)(_ => Module(new LoadUnit))

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -24,6 +24,13 @@ object RoqPtr extends HasXSParameter {
   }
 }
 
+class RoqCSRIO extends XSBundle {
+  val intrBitSet = Input(Bool())
+  val trapTarget = Input(UInt(VAddrBits.W))
+
+  val fflags = Output(new Fflags)
+  val dirty_fs = Output(Bool())
+}
 
 class Roq extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
@@ -39,11 +46,7 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
     val bcommit = Output(UInt(BrTagWidth.W))
     val commitRoqIndex = Output(Valid(new RoqPtr))
     val roqDeqPtr = Output(new RoqPtr)
-    val intrBitSet = Input(Bool())
-    val trapTarget = Input(UInt(VAddrBits.W))
-
-    val fflags = Output(new Fflags)
-    val dirty_fs = Output(Bool())
+    val csr = new RoqCSRIO
   })
 
   val numWbPorts = io.exeWbResults.length
@@ -133,15 +136,9 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
     }
   }
 
-  // roq redirect only used for exception
-  // val intrBitSet = WireInit(false.B)
-  // ExcitingUtils.addSink(intrBitSet, "intrBitSetIDU")
-  // val trapTarget = WireInit(0.U(VAddrBits.W))
-  // ExcitingUtils.addSink(trapTarget, "trapTarget")
-
   val deqUop = microOp(deqPtr)
   val deqPtrWritebacked = writebacked(deqPtr) && valid(deqPtr)
-  val intrEnable = io.intrBitSet && !isEmpty && !hasNoSpec &&
+  val intrEnable = io.csr.intrBitSet && !isEmpty && !hasNoSpec &&
     deqUop.ctrl.commitType =/= CommitType.STORE && deqUop.ctrl.commitType =/= CommitType.LOAD// TODO: wanna check why has hasCsr(hasNoSpec)
   val exceptionEnable = deqPtrWritebacked && Cat(deqUop.cf.exceptionVec).orR()
   val isFlushPipe = deqPtrWritebacked && deqUop.ctrl.flushPipe
@@ -150,9 +147,12 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
   io.redirect.bits.isException := intrEnable || exceptionEnable
   // reuse isFlushPipe to represent interrupt for CSR
   io.redirect.bits.isFlushPipe := isFlushPipe || intrEnable
-  io.redirect.bits.target := Mux(isFlushPipe, deqUop.cf.pc + 4.U, io.trapTarget)
+  io.redirect.bits.target := Mux(isFlushPipe, deqUop.cf.pc + 4.U, io.csr.trapTarget)
   io.exception := deqUop
-  XSDebug(io.redirect.valid, "generate redirect: pc 0x%x intr %d excp %d flushpp %d target:0x%x Traptarget 0x%x exceptionVec %b\n", io.exception.cf.pc, intrEnable, exceptionEnable, isFlushPipe, io.redirect.bits.target, io.trapTarget, Cat(microOp(deqPtr).cf.exceptionVec))
+  XSDebug(io.redirect.valid,
+    "generate redirect: pc 0x%x intr %d excp %d flushpp %d target:0x%x Traptarget 0x%x exceptionVec %b\n",
+    io.exception.cf.pc, intrEnable, exceptionEnable, isFlushPipe, io.redirect.bits.target, io.csr.trapTarget,
+    Cat(microOp(deqPtr).cf.exceptionVec))
 
   // Commit uop to Rename (walk)
   val shouldWalkVec = Wire(Vec(CommitWidth, Bool()))
@@ -259,8 +259,8 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
     io.commits(i).bits.isWalk := state =/= s_idle
   }
 
-  io.fflags := fflags
-  io.dirty_fs := dirty_fs
+  io.csr.fflags := fflags
+  io.csr.dirty_fs := dirty_fs
 
   val validCommit = io.commits.map(_.valid)
   when(state===s_walk) {