Remove the final 'BoringUtils'

src/main/scala/xiangshan/backend/Backend.scala

@@ -2,15 +2,13 @@ package xiangshan.backend
 
 import chisel3._
 import chisel3.util._
-import chisel3.util.experimental.BoringUtils
 import xiangshan._
 import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
 import xiangshan.backend.rename.Rename
 import xiangshan.backend.brq.Brq
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
-import xiangshan.backend.fu.FunctionUnit
-import xiangshan.backend.issue.{IssueQueue, ReservationStationNew}
+import xiangshan.backend.issue.ReservationStationNew
 import xiangshan.backend.regfile.{Regfile, RfWritePort}
 import xiangshan.backend.roq.Roq
 import xiangshan.mem._
@@ -239,8 +237,8 @@ class Backend extends XSModule
 
 
   val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
-  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
-  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
+  ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug)
+  ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug)
   val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
   if (!env.FPGAPlatform) {
     ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)

src/main/scala/xiangshan/backend/regfile/Regfile.scala

@@ -2,7 +2,6 @@ package xiangshan.backend.regfile
 
 import chisel3._
 import chisel3.util._
-import chisel3.util.experimental.BoringUtils
 import xiangshan._
 
 class RfReadPort extends XSBundle {
@@ -41,8 +40,18 @@ class Regfile
   }
 
   val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W))))
-  BoringUtils.addSink(debugArchRat, if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT")
-
-  val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(x => if(hasZero && x._2==0) 0.U else mem(x._1))))
-  BoringUtils.addSource(debugArchReg, if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG")
+  ExcitingUtils.addSink(
+    debugArchRat,
+    if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT",
+    ExcitingUtils.Debug
+  )
+
+  val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
+    x => if(hasZero && x._2==0) 0.U else mem(x._1)
+  )))
+  ExcitingUtils.addSource(
+    debugArchReg,
+    if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG",
+    ExcitingUtils.Debug
+  )
 }

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -2,7 +2,6 @@ package xiangshan.backend.rename
 
 import chisel3._
 import chisel3.util._
-import chisel3.util.experimental.BoringUtils
 import xiangshan._
 
 class RatReadPort extends XSBundle {
@@ -52,5 +51,9 @@ class RenameTable(float: Boolean) extends XSModule {
     }
   }
 
-  BoringUtils.addSource(arch_table, if(float) "DEBUG_FP_ARCH_RAT" else "DEBUG_INI_ARCH_RAT")
+  ExcitingUtils.addSource(
+    arch_table,
+    if(float) "DEBUG_FP_ARCH_RAT" else "DEBUG_INI_ARCH_RAT",
+    ExcitingUtils.Debug
+  )
 }
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