perf_event.c 49.1 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#include <asm/timer.h>
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#include <asm/desc.h>
#include <asm/ldt.h>
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#include "perf_event.h"

struct x86_pmu x86_pmu __read_mostly;
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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u64 __read_mostly hw_cache_event_ids
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 __read_mostly hw_cache_extra_regs
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/*
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 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
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 * Returns the delta events processed.
 */
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u64 x86_perf_event_update(struct perf_event *event)
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{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
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	s64 delta;
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	if (idx == INTEL_PMC_IDX_FIXED_BTS)
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		return 0;

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	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
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	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
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	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
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	struct hw_perf_event_extra *reg;
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	struct extra_reg *er;

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	reg = &event->hw.extra_reg;
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	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
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		/* Check if the extra msrs can be safely accessed*/
		if (!er->extra_msr_access)
			return -ENXIO;
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		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
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		break;
	}
	return 0;
}

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static atomic_t active_events;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
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	u64 val, val_fail, val_new= ~0;
	int i, reg, reg_fail, ret = 0;
	int bios_fail = 0;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
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		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
		}
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	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
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			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
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		}
	}

	/*
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	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
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	 */
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	reg = x86_pmu_event_addr(0);
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	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
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	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	/*
	 * We still allow the PMU driver to operate:
	 */
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	if (bios_fail) {
		printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
		printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
	}
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	return true;
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msr_fail:
	printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
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	printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
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	return false;
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}

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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
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		release_ds_buffers();
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		mutex_unlock(&pmc_reserve_mutex);
	}
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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int x86_setup_perfctr(struct perf_event *event)
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{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	}

	if (attr->type == PERF_TYPE_RAW)
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		return x86_pmu_extra_regs(event->attr.config, event);
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
	}

	hwc->config |= config;

	return 0;
}
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/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

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int x86_pmu_hw_config(struct perf_event *event)
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{
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	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
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		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
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			precise++;

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			/* Support for IP fixup */
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			if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
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				precise++;
		}
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		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
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		/*
		 * check that PEBS LBR correction does not conflict with
		 * whatever the user is asking with attr->branch_sample_type
		 */
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		if (event->attr.precise_ip > 1 &&
		    x86_pmu.intel_cap.pebs_format < 2) {
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			u64 *br_type = &event->attr.branch_sample_type;

			if (has_branch_stack(event)) {
				if (!precise_br_compat(event))
					return -EOPNOTSUPP;

				/* branch_sample_type is compatible */

			} else {
				/*
				 * user did not specify  branch_sample_type
				 *
				 * For PEBS fixups, we capture all
				 * the branches at the priv level of the
				 * event.
				 */
				*br_type = PERF_SAMPLE_BRANCH_ANY;

				if (!event->attr.exclude_user)
					*br_type |= PERF_SAMPLE_BRANCH_USER;

				if (!event->attr.exclude_kernel)
					*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
			}
		}
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	}

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	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
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	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
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	/*
	 * Count user and OS events unless requested not to
	 */
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	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
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	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
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	return x86_setup_perfctr(event);
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}

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/*
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 * Setup the hardware configuration for a given attr_type
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 */
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static int __x86_pmu_event_init(struct perf_event *event)
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{
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	int err;
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	if (!x86_pmu_initialized())
		return -ENODEV;
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	err = 0;
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	if (!atomic_inc_not_zero(&active_events)) {
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		mutex_lock(&pmc_reserve_mutex);
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		if (atomic_read(&active_events) == 0) {
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			if (!reserve_pmc_hardware())
				err = -EBUSY;
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			else
				reserve_ds_buffers();
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		}
		if (!err)
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			atomic_inc(&active_events);
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		mutex_unlock(&pmc_reserve_mutex);
	}
	if (err)
		return err;

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	event->destroy = hw_perf_event_destroy;
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	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
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	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;

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	return x86_pmu.hw_config(event);
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}

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void x86_pmu_disable_all(void)
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{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

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	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		u64 val;

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		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		rdmsrl(x86_pmu_config_addr(idx), val);
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		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
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			continue;
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		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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		wrmsrl(x86_pmu_config_addr(idx), val);
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	}
}

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static void x86_pmu_disable(struct pmu *pmu)
507
{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

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	if (!x86_pmu_initialized())
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		return;
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	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
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	x86_pmu.disable_all();
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}
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void x86_pmu_enable_all(int added)
524
{
525
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

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	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
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		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
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	}
}

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static struct pmu pmu;
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static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

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/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

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/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

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struct perf_sched {
	int			max_weight;
	int			max_events;
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	struct perf_event	**events;
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	struct sched_state	state;
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	int			saved_states;
	struct sched_state	saved[SCHED_STATES_MAX];
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};

/*
 * Initialize interator that runs through all events and counters.
 */
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static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
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			    int num, int wmin, int wmax)
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
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	sched->events		= events;
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	for (idx = 0; idx < num; idx++) {
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		if (events[idx]->hw.constraint->weight == wmin)
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			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

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static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

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/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
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static bool __perf_sched_find_counter(struct perf_sched *sched)
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{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

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	c = sched->events[sched->state.event]->hw.constraint;
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	/* Prefer fixed purpose counters */
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	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
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		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
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			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
642 643
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
644
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
645
		if (!__test_and_set_bit(idx, sched->state.used))
646
			goto done;
647 648
	}

649 650 651 652
	return false;

done:
	sched->state.counter = idx;
653

654 655 656 657 658 659 660 661 662 663 664 665 666
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
691
		c = sched->events[sched->state.event]->hw.constraint;
692 693 694 695 696 697 698 699 700 701
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
702
int perf_assign_events(struct perf_event **events, int n,
Y
Yan, Zheng 已提交
703
			int wmin, int wmax, int *assign)
704 705 706
{
	struct perf_sched sched;

707
	perf_sched_init(&sched, events, n, wmin, wmax);
708 709 710 711 712 713 714 715 716 717

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}
718
EXPORT_SYMBOL_GPL(perf_assign_events);
719

720
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
721
{
722
	struct event_constraint *c;
723
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
724
	struct perf_event *e;
725
	int i, wmin, wmax, num = 0;
726 727 728 729
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

730
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
731
		hwc = &cpuc->event_list[i]->hw;
732
		c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
733 734
		hwc->constraint = c;

735 736
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
737 738
	}

739 740 741
	/*
	 * fastpath, try to reuse previous register
	 */
742
	for (i = 0; i < n; i++) {
743
		hwc = &cpuc->event_list[i]->hw;
744
		c = hwc->constraint;
745 746 747 748 749 750

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
751
		if (!test_bit(hwc->idx, c->idxmsk))
752 753 754 755 756 757
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
758
		__set_bit(hwc->idx, used_mask);
759 760 761 762
		if (assign)
			assign[i] = hwc->idx;
	}

763 764
	/* slow path */
	if (i != n)
765 766
		num = perf_assign_events(cpuc->event_list, n, wmin,
					 wmax, assign);
767

768 769 770 771 772 773 774 775 776 777
	/*
	 * Mark the event as committed, so we do not put_constraint()
	 * in case new events are added and fail scheduling.
	 */
	if (!num && assign) {
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
		}
	}
778 779 780 781 782 783
	/*
	 * scheduling failed or is just a simulation,
	 * free resources if necessary
	 */
	if (!assign || num) {
		for (i = 0; i < n; i++) {
784 785 786 787 788 789 790 791
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

792
			if (x86_pmu.put_event_constraints)
793
				x86_pmu.put_event_constraints(cpuc, e);
794 795
		}
	}
796
	return num ? -EINVAL : 0;
797 798 799 800 801 802 803 804 805 806 807
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

808
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
809 810 811 812 813 814

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
815
			return -EINVAL;
816 817 818 819 820 821 822 823
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
824
		    event->state <= PERF_EVENT_STATE_OFF)
825 826 827
			continue;

		if (n >= max_count)
828
			return -EINVAL;
829 830 831 832 833 834 835 836

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
837
				struct cpu_hw_events *cpuc, int i)
838
{
839 840 841 842 843
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
844

845
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
846 847
		hwc->config_base = 0;
		hwc->event_base	= 0;
848
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
849
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
850 851
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
852
	} else {
853 854
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
855
		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
856 857 858
	}
}

859 860 861 862 863 864 865 866 867
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
868
static void x86_pmu_start(struct perf_event *event, int flags);
869

P
Peter Zijlstra 已提交
870
static void x86_pmu_enable(struct pmu *pmu)
871
{
872 873 874
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct perf_event *event;
	struct hw_perf_event *hwc;
875
	int i, added = cpuc->n_added;
876

877
	if (!x86_pmu_initialized())
878
		return;
879 880 881 882

	if (cpuc->enabled)
		return;

883
	if (cpuc->n_added) {
884
		int n_running = cpuc->n_events - cpuc->n_added;
885 886 887 888 889 890
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 */
891
		for (i = 0; i < n_running; i++) {
892 893 894
			event = cpuc->event_list[i];
			hwc = &event->hw;

895 896 897 898 899 900 901 902
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
903 904
				continue;

P
Peter Zijlstra 已提交
905 906 907 908 909 910 911 912
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
913 914
		}

915 916 917
		/*
		 * step2: reprogram moved events into new counters
		 */
918 919 920 921
		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

922
			if (!match_prev_assignment(hwc, cpuc, i))
923
				x86_assign_hw_event(event, cpuc, i);
924 925
			else if (i < n_running)
				continue;
926

P
Peter Zijlstra 已提交
927 928 929 930
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
931 932 933 934
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
935 936 937 938

	cpuc->enabled = 1;
	barrier();

939
	x86_pmu.enable_all(added);
940 941
}

942
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
943

944 945
/*
 * Set the next IRQ period, based on the hwc->period_left value.
946
 * To be called with the event disabled in hw:
947
 */
948
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
949
{
950
	struct hw_perf_event *hwc = &event->hw;
951
	s64 left = local64_read(&hwc->period_left);
952
	s64 period = hwc->sample_period;
953
	int ret = 0, idx = hwc->idx;
954

955
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
956 957
		return 0;

958
	/*
959
	 * If we are way outside a reasonable range then just skip forward:
960 961 962
	 */
	if (unlikely(left <= -period)) {
		left = period;
963
		local64_set(&hwc->period_left, left);
964
		hwc->last_period = period;
965
		ret = 1;
966 967 968 969
	}

	if (unlikely(left <= 0)) {
		left += period;
970
		local64_set(&hwc->period_left, left);
971
		hwc->last_period = period;
972
		ret = 1;
973
	}
974
	/*
975
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
976 977 978
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
979

980 981 982
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

983
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
984 985

	/*
986
	 * The hw event starts counting from this event offset,
987 988
	 * mark it to be able to extra future deltas:
	 */
989
	local64_set(&hwc->prev_count, (u64)-left);
990

991
	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
992 993 994 995 996 997 998

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
999
		wrmsrl(hwc->event_base,
1000
			(u64)(-left) & x86_pmu.cntval_mask);
1001
	}
1002

1003
	perf_event_update_userpage(event);
1004

1005
	return ret;
1006 1007
}

1008
void x86_pmu_enable_event(struct perf_event *event)
1009
{
T
Tejun Heo 已提交
1010
	if (__this_cpu_read(cpu_hw_events.enabled))
1011 1012
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1013 1014
}

1015
/*
P
Peter Zijlstra 已提交
1016
 * Add a single event to the PMU.
1017 1018 1019
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1020
 */
P
Peter Zijlstra 已提交
1021
static int x86_pmu_add(struct perf_event *event, int flags)
1022 1023
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1024 1025 1026
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1027

1028
	hwc = &event->hw;
1029

P
Peter Zijlstra 已提交
1030
	perf_pmu_disable(event->pmu);
1031
	n0 = cpuc->n_events;
1032 1033 1034
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1035

P
Peter Zijlstra 已提交
1036 1037 1038 1039
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1040 1041
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1042
	 * skip the schedulability test here, it will be performed
1043
	 * at commit time (->commit_txn) as a whole.
1044
	 */
1045
	if (cpuc->group_flag & PERF_EVENT_TXN)
1046
		goto done_collect;
1047

1048
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1049
	if (ret)
1050
		goto out;
1051 1052 1053 1054 1055
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1056

1057
done_collect:
1058 1059 1060 1061
	/*
	 * Commit the collect_events() state. See x86_pmu_del() and
	 * x86_pmu_*_txn().
	 */
1062
	cpuc->n_events = n;
1063
	cpuc->n_added += n - n0;
1064
	cpuc->n_txn += n - n0;
1065

1066 1067
	ret = 0;
out:
P
Peter Zijlstra 已提交
1068
	perf_pmu_enable(event->pmu);
1069
	return ret;
I
Ingo Molnar 已提交
1070 1071
}

P
Peter Zijlstra 已提交
1072
static void x86_pmu_start(struct perf_event *event, int flags)
1073
{
P
Peter Zijlstra 已提交
1074 1075 1076
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1089

P
Peter Zijlstra 已提交
1090 1091
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1092
	__set_bit(idx, cpuc->running);
1093
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1094
	perf_event_update_userpage(event);
1095 1096
}

1097
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1098
{
1099
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1100
	u64 pebs;
1101
	struct cpu_hw_events *cpuc;
1102
	unsigned long flags;
1103 1104
	int cpu, idx;

1105
	if (!x86_pmu.num_counters)
1106
		return;
I
Ingo Molnar 已提交
1107

1108
	local_irq_save(flags);
I
Ingo Molnar 已提交
1109 1110

	cpu = smp_processor_id();
1111
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1112

1113
	if (x86_pmu.version >= 2) {
1114 1115 1116 1117
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1118
		rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1119 1120 1121 1122 1123 1124

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1125
		pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1126
	}
1127
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1128

1129
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1130 1131
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1132

1133
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1134

1135
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1136
			cpu, idx, pmc_ctrl);
1137
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1138
			cpu, idx, pmc_count);
1139
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1140
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1141
	}
1142
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1143 1144
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1145
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1146 1147
			cpu, idx, pmc_count);
	}
1148
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1149 1150
}

1151
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1152
{
1153
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1154
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1155

P
Peter Zijlstra 已提交
1156 1157 1158 1159 1160 1161
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1162

P
Peter Zijlstra 已提交
1163 1164 1165 1166 1167 1168 1169 1170
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1171 1172
}

P
Peter Zijlstra 已提交
1173
static void x86_pmu_del(struct perf_event *event, int flags)
1174 1175 1176 1177
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int i;

1178 1179 1180 1181 1182
	/*
	 * event is descheduled
	 */
	event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;

1183 1184 1185 1186
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
1187 1188 1189
	 *
	 * XXX assumes any ->del() called during a TXN will only be on
	 * an event added during that same TXN.
1190
	 */
1191
	if (cpuc->group_flag & PERF_EVENT_TXN)
1192 1193
		return;

1194 1195 1196
	/*
	 * Not a TXN, therefore cleanup properly.
	 */
P
Peter Zijlstra 已提交
1197
	x86_pmu_stop(event, PERF_EF_UPDATE);
1198

1199
	for (i = 0; i < cpuc->n_events; i++) {
1200 1201 1202
		if (event == cpuc->event_list[i])
			break;
	}
1203

1204 1205
	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
		return;
P
Peter Zijlstra 已提交
1206

1207 1208 1209
	/* If we have a newly added event; make sure to decrease n_added. */
	if (i >= cpuc->n_events - cpuc->n_added)
		--cpuc->n_added;
1210

1211 1212 1213 1214 1215 1216 1217
	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(cpuc, event);

	/* Delete the array entry. */
	while (++i < cpuc->n_events)
		cpuc->event_list[i-1] = cpuc->event_list[i];
	--cpuc->n_events;
1218

1219
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1220 1221
}

1222
int x86_pmu_handle_irq(struct pt_regs *regs)
1223
{
1224
	struct perf_sample_data data;
1225 1226
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1227
	int idx, handled = 0;
1228 1229
	u64 val;

1230
	cpuc = &__get_cpu_var(cpu_hw_events);
1231

1232 1233 1234 1235 1236 1237 1238 1239 1240 1241
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1242
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1243 1244 1245 1246 1247 1248 1249 1250
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1251
			continue;
1252
		}
1253

1254
		event = cpuc->events[idx];
1255

1256
		val = x86_perf_event_update(event);
1257
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1258
			continue;
1259

1260
		/*
1261
		 * event overflow
1262
		 */
1263
		handled++;
1264
		perf_sample_data_init(&data, 0, event->hw.last_period);
1265

1266
		if (!x86_perf_event_set_period(event))
1267 1268
			continue;

1269
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1270
			x86_pmu_stop(event, 0);
1271
	}
1272

1273 1274 1275
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1276 1277
	return handled;
}
1278

1279
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1280
{
1281
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1282
		return;
1283

I
Ingo Molnar 已提交
1284
	/*
1285
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1286
	 */
1287
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1288 1289
}

1290
static int
1291
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1292
{
1293 1294
	u64 start_clock;
	u64 finish_clock;
P
Peter Zijlstra 已提交
1295
	int ret;
1296

1297
	if (!atomic_read(&active_events))
1298
		return NMI_DONE;
1299

P
Peter Zijlstra 已提交
1300
	start_clock = sched_clock();
1301
	ret = x86_pmu.handle_irq(regs);
P
Peter Zijlstra 已提交
1302
	finish_clock = sched_clock();
1303 1304 1305 1306

	perf_sample_event_took(finish_clock - start_clock);

	return ret;
I
Ingo Molnar 已提交
1307
}
1308
NOKPROBE_SYMBOL(perf_event_nmi_handler);
I
Ingo Molnar 已提交
1309

1310 1311
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1312

1313
static int
1314 1315 1316
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1317
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1318
	int ret = NOTIFY_OK;
1319 1320 1321

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1322
		cpuc->kfree_on_online = NULL;
1323
		if (x86_pmu.cpu_prepare)
1324
			ret = x86_pmu.cpu_prepare(cpu);
1325 1326 1327
		break;

	case CPU_STARTING:
1328 1329
		if (x86_pmu.attr_rdpmc)
			set_in_cr4(X86_CR4_PCE);
1330 1331 1332 1333
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1334 1335 1336 1337
	case CPU_ONLINE:
		kfree(cpuc->kfree_on_online);
		break;

1338 1339 1340 1341 1342
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1343
	case CPU_UP_CANCELED:
1344 1345 1346 1347 1348 1349 1350 1351 1352
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1353
	return ret;
1354 1355
}

1356 1357 1358 1359 1360 1361 1362 1363
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
1364 1365 1366 1367 1368 1369 1370 1371 1372

	/*
	 * If we have a PMU initialized but no APIC
	 * interrupts, we cannot sample hardware
	 * events (user-space has to fall back and
	 * sample via a hrtimer based software event):
	 */
	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

1373 1374
}

1375 1376 1377 1378 1379
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1380 1381 1382 1383 1384 1385
/*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
 */
static void __init filter_events(struct attribute **attrs)
{
1386 1387
	struct device_attribute *d;
	struct perf_pmu_events_attr *pmu_attr;
1388 1389 1390
	int i, j;

	for (i = 0; attrs[i]; i++) {
1391 1392 1393 1394 1395
		d = (struct device_attribute *)attrs[i];
		pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
		/* str trumps id */
		if (pmu_attr->event_str)
			continue;
1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
		if (x86_pmu.event_map(i))
			continue;

		for (j = i; attrs[j]; j++)
			attrs[j] = attrs[j + 1];

		/* Check the shifted attr. */
		i--;
	}
}

1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
/* Merge two pointer arrays */
static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
{
	struct attribute **new;
	int j, i;

	for (j = 0; a[j]; j++)
		;
	for (i = 0; b[i]; i++)
		j++;
	j++;

	new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
	if (!new)
		return NULL;

	j = 0;
	for (i = 0; a[i]; i++)
		new[j++] = a[i];
	for (i = 0; b[i]; i++)
		new[j++] = b[i];
	new[j] = NULL;

	return new;
}

1433
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1434 1435 1436 1437 1438 1439
			  char *page)
{
	struct perf_pmu_events_attr *pmu_attr = \
		container_of(attr, struct perf_pmu_events_attr, attr);
	u64 config = x86_pmu.event_map(pmu_attr->id);

1440 1441 1442
	/* string trumps id */
	if (pmu_attr->event_str)
		return sprintf(page, "%s", pmu_attr->event_str);
1443

1444 1445
	return x86_pmu.events_sysfs_show(page, config);
}
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459

EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
EVENT_ATTR(instructions,		INSTRUCTIONS		);
EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);

static struct attribute *empty_attrs;

P
Peter Huewe 已提交
1460
static struct attribute *events_attr[] = {
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478
	EVENT_PTR(CPU_CYCLES),
	EVENT_PTR(INSTRUCTIONS),
	EVENT_PTR(CACHE_REFERENCES),
	EVENT_PTR(CACHE_MISSES),
	EVENT_PTR(BRANCH_INSTRUCTIONS),
	EVENT_PTR(BRANCH_MISSES),
	EVENT_PTR(BUS_CYCLES),
	EVENT_PTR(STALLED_CYCLES_FRONTEND),
	EVENT_PTR(STALLED_CYCLES_BACKEND),
	EVENT_PTR(REF_CPU_CYCLES),
	NULL,
};

static struct attribute_group x86_pmu_events_group = {
	.name = "events",
	.attrs = events_attr,
};

1479
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517
{
	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
	ssize_t ret;

	/*
	* We have whole page size to spend and just little data
	* to write, so we can safely use sprintf.
	*/
	ret = sprintf(page, "event=0x%02llx", event);

	if (umask)
		ret += sprintf(page + ret, ",umask=0x%02llx", umask);

	if (edge)
		ret += sprintf(page + ret, ",edge");

	if (pc)
		ret += sprintf(page + ret, ",pc");

	if (any)
		ret += sprintf(page + ret, ",any");

	if (inv)
		ret += sprintf(page + ret, ",inv");

	if (cmask)
		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);

	ret += sprintf(page + ret, "\n");

	return ret;
}

1518
static int __init init_hw_perf_events(void)
1519
{
1520
	struct x86_pmu_quirk *quirk;
1521 1522
	int err;

1523
	pr_info("Performance Events: ");
1524

1525 1526
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1527
		err = intel_pmu_init();
1528
		break;
1529
	case X86_VENDOR_AMD:
1530
		err = amd_pmu_init();
1531
		break;
1532
	default:
1533
		err = -ENOTSUPP;
1534
	}
1535
	if (err != 0) {
1536
		pr_cont("no PMU driver, software events only.\n");
1537
		return 0;
1538
	}
1539

1540 1541
	pmu_check_apic();

1542
	/* sanity check that the hardware exists or is emulated */
1543
	if (!check_hw_exists())
1544
		return 0;
1545

1546
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1547

1548 1549
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */

1550 1551
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1552

1553 1554
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1555

1556
	perf_events_lapic_init();
1557
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1558

1559
	unconstrained = (struct event_constraint)
1560
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1561
				   0, x86_pmu.num_counters, 0, 0);
1562

1563
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1564

1565 1566 1567
	if (x86_pmu.event_attrs)
		x86_pmu_events_group.attrs = x86_pmu.event_attrs;

1568 1569
	if (!x86_pmu.events_sysfs_show)
		x86_pmu_events_group.attrs = &empty_attrs;
1570 1571
	else
		filter_events(x86_pmu_events_group.attrs);
1572

1573 1574 1575 1576 1577 1578 1579 1580
	if (x86_pmu.cpu_events) {
		struct attribute **tmp;

		tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
		if (!WARN_ON(!tmp))
			x86_pmu_events_group.attrs = tmp;
	}

I
Ingo Molnar 已提交
1581
	pr_info("... version:                %d\n",     x86_pmu.version);
1582 1583 1584
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1585
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1586
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1587
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1588

P
Peter Zijlstra 已提交
1589
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1590
	perf_cpu_notifier(x86_pmu_notifier);
1591 1592

	return 0;
I
Ingo Molnar 已提交
1593
}
1594
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1595

1596
static inline void x86_pmu_read(struct perf_event *event)
1597
{
1598
	x86_perf_event_update(event);
1599 1600
}

1601 1602 1603 1604 1605
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
P
Peter Zijlstra 已提交
1606
static void x86_pmu_start_txn(struct pmu *pmu)
1607
{
P
Peter Zijlstra 已提交
1608
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1609 1610
	__this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1611 1612 1613 1614 1615 1616 1617
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1618
static void x86_pmu_cancel_txn(struct pmu *pmu)
1619
{
T
Tejun Heo 已提交
1620
	__this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1621
	/*
1622 1623
	 * Truncate collected array by the number of events added in this
	 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1624
	 */
T
Tejun Heo 已提交
1625 1626
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1627
	perf_pmu_enable(pmu);
1628 1629 1630 1631 1632 1633
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
1634 1635
 *
 * Does not cancel the transaction on failure; expects the caller to do this.
1636
 */
P
Peter Zijlstra 已提交
1637
static int x86_pmu_commit_txn(struct pmu *pmu)
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1658
	cpuc->group_flag &= ~PERF_EVENT_TXN;
P
Peter Zijlstra 已提交
1659
	perf_pmu_enable(pmu);
1660 1661
	return 0;
}
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1691
	cpuc->is_fake = 1;
1692 1693 1694 1695 1696
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1697

1698 1699 1700 1701 1702 1703 1704 1705 1706
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1707 1708 1709
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1710 1711 1712 1713

	c = x86_pmu.get_event_constraints(fake_cpuc, event);

	if (!c || !c->weight)
1714
		ret = -EINVAL;
1715 1716 1717 1718

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1719
	free_fake_cpuc(fake_cpuc);
1720 1721 1722 1723

	return ret;
}

1724 1725 1726 1727
/*
 * validate a single event group
 *
 * validation include:
1728 1729 1730
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1731 1732 1733 1734
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1735 1736
static int validate_group(struct perf_event *event)
{
1737
	struct perf_event *leader = event->group_leader;
1738
	struct cpu_hw_events *fake_cpuc;
1739
	int ret = -EINVAL, n;
1740

1741 1742 1743
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1744 1745 1746 1747 1748 1749
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1750
	n = collect_events(fake_cpuc, leader, true);
1751
	if (n < 0)
1752
		goto out;
1753

1754 1755
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1756
	if (n < 0)
1757
		goto out;
1758

1759
	fake_cpuc->n_events = n;
1760

1761
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1762 1763

out:
1764
	free_fake_cpuc(fake_cpuc);
1765
	return ret;
1766 1767
}

1768
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1769
{
P
Peter Zijlstra 已提交
1770
	struct pmu *tmp;
I
Ingo Molnar 已提交
1771 1772
	int err;

1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1784
	if (!err) {
1785 1786 1787 1788 1789 1790 1791 1792
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1793 1794
		if (event->group_leader != event)
			err = validate_group(event);
1795 1796
		else
			err = validate_event(event);
1797 1798

		event->pmu = tmp;
1799
	}
1800
	if (err) {
1801 1802
		if (event->destroy)
			event->destroy(event);
1803
	}
I
Ingo Molnar 已提交
1804

1805
	return err;
I
Ingo Molnar 已提交
1806
}
1807

1808 1809 1810 1811
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

1812 1813 1814
	if (!x86_pmu.attr_rdpmc)
		return 0;

1815 1816
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
1817 1818 1819 1820 1821 1822
		idx |= 1 << 30;
	}

	return idx + 1;
}

1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static void change_rdpmc(void *info)
{
	bool enable = !!(unsigned long)info;

	if (enable)
		set_in_cr4(X86_CR4_PCE);
	else
		clear_in_cr4(X86_CR4_PCE);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
1844 1845 1846 1847 1848 1849
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
1850 1851 1852

	if (x86_pmu.attr_rdpmc_broken)
		return -ENOTSUPP;
1853 1854 1855

	if (!!val != !!x86_pmu.attr_rdpmc) {
		x86_pmu.attr_rdpmc = !!val;
1856
		on_each_cpu(change_rdpmc, (void *)val, 1);
1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874
	}

	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
1875
	&x86_pmu_format_group,
1876
	&x86_pmu_events_group,
1877 1878 1879
	NULL,
};

1880 1881 1882 1883 1884 1885
static void x86_pmu_flush_branch_stack(void)
{
	if (x86_pmu.flush_branch_stack)
		x86_pmu.flush_branch_stack();
}

1886 1887 1888 1889 1890 1891 1892
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

1893
static struct pmu pmu = {
1894 1895
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
P
Peter Zijlstra 已提交
1896

1897
	.attr_groups		= x86_pmu_attr_groups,
1898

1899
	.event_init		= x86_pmu_event_init,
P
Peter Zijlstra 已提交
1900

1901 1902 1903 1904 1905
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
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Peter Zijlstra 已提交
1906

1907 1908 1909
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
1910

1911
	.event_idx		= x86_pmu_event_idx,
1912
	.flush_branch_stack	= x86_pmu_flush_branch_stack,
1913 1914
};

1915
void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1916
{
1917 1918
	struct cyc2ns_data *data;

1919 1920 1921
	userpg->cap_user_time = 0;
	userpg->cap_user_time_zero = 0;
	userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1922 1923
	userpg->pmc_width = x86_pmu.cntval_bits;

1924
	if (!sched_clock_stable())
1925 1926
		return;

1927 1928
	data = cyc2ns_read_begin();

1929
	userpg->cap_user_time = 1;
1930 1931 1932
	userpg->time_mult = data->cyc2ns_mul;
	userpg->time_shift = data->cyc2ns_shift;
	userpg->time_offset = data->cyc2ns_offset - now;
1933

1934
	userpg->cap_user_time_zero = 1;
1935 1936 1937
	userpg->time_zero = data->cyc2ns_offset;

	cyc2ns_read_end(data);
1938 1939
}

1940 1941 1942 1943 1944 1945
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
1946
	return 0;
1947 1948 1949 1950 1951 1952
}

static void backtrace_address(void *data, unsigned long addr, int reliable)
{
	struct perf_callchain_entry *entry = data;

1953
	perf_callchain_store(entry, addr);
1954 1955 1956 1957 1958
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
1959
	.walk_stack		= print_context_stack_bp,
1960 1961
};

1962 1963
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1964
{
1965 1966
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1967
		return;
1968 1969
	}

1970
	perf_callchain_store(entry, regs->ip);
1971

1972
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1973 1974
}

1975 1976 1977 1978 1979 1980
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
		if (idx > LDT_ENTRIES)
			return 0;

		if (idx > current->active_mm->context.size)
			return 0;

		desc = current->active_mm->context.ldt;
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

		desc = __this_cpu_ptr(&gdt_page.gdt[0]);
	}

	return get_desc_base(desc + idx);
}

2004
#ifdef CONFIG_COMPAT
H
H. Peter Anvin 已提交
2005 2006 2007

#include <asm/compat.h>

2008 2009
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2010
{
2011
	/* 32-bit process in 64-bit kernel. */
2012
	unsigned long ss_base, cs_base;
2013 2014
	struct stack_frame_ia32 frame;
	const void __user *fp;
2015

2016 2017 2018
	if (!test_thread_flag(TIF_IA32))
		return 0;

2019 2020 2021 2022
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
2023 2024 2025 2026 2027 2028
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2029
		if (bytes != 0)
2030
			break;
2031

2032 2033 2034
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2035 2036
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
2037 2038
	}
	return 1;
2039
}
2040 2041 2042 2043 2044 2045 2046
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
2047

2048 2049
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2050 2051 2052 2053
{
	struct stack_frame frame;
	const void __user *fp;

2054 2055
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2056
		return;
2057
	}
2058

2059 2060 2061 2062 2063 2064
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

2065
	fp = (void __user *)regs->bp;
2066

2067
	perf_callchain_store(entry, regs->ip);
2068

2069 2070 2071
	if (!current->mm)
		return;

2072 2073 2074
	if (perf_callchain_user32(regs, entry))
		return;

2075
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
2076
		unsigned long bytes;
2077
		frame.next_frame	     = NULL;
2078 2079
		frame.return_address = 0;

2080
		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2081
		if (bytes != 0)
2082 2083
			break;

2084 2085 2086
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2087
		perf_callchain_store(entry, frame.return_address);
2088
		fp = frame.next_frame;
2089 2090 2091
	}
}

2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
2106
{
2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */
#ifdef CONFIG_X86_32
	if (user_mode(regs) && regs->cs != __USER_CS)
		return get_segment_base(regs->cs);
#else
	if (test_thread_flag(TIF_IA32)) {
		if (user_mode(regs) && regs->cs != __USER32_CS)
			return get_segment_base(regs->cs);
	}
#endif
	return 0;
}
2129

2130 2131
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
2132
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2133
		return perf_guest_cbs->get_guest_ip();
2134

2135
	return regs->ip + code_segment_base(regs);
2136 2137 2138 2139 2140
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
2141

2142
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2143 2144 2145 2146 2147
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
2148
		if (user_mode(regs))
2149 2150 2151 2152 2153
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

2154
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
2155
		misc |= PERF_RECORD_MISC_EXACT_IP;
2156 2157 2158

	return misc;
}
2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170

void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);