helper.c 169.5 KB
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#include "cpu.h"
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#include "internals.h"
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#include "exec/gdbstub.h"
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#include "helper.h"
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#include "qemu/host-utils.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/sysemu.h"
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#include "qemu/bitops.h"
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#include "qemu/crc32c.h"
#include <zlib.h> /* For crc32 */
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#ifndef CONFIG_USER_ONLY
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
                                int access_type, int is_user,
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                                hwaddr *phys_ptr, int *prot,
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                                target_ulong *page_size);
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/* Definitions for the PMCCNTR and PMCR registers */
#define PMCRD   0x8
#define PMCRC   0x4
#define PMCRE   0x1
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#endif

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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
    int nregs;

    /* VFP data registers are always little-endian.  */
    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
    if (reg < nregs) {
        stfq_le_p(buf, env->vfp.regs[reg]);
        return 8;
    }
    if (arm_feature(env, ARM_FEATURE_NEON)) {
        /* Aliases for Q regs.  */
        nregs += 16;
        if (reg < nregs) {
            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
            return 16;
        }
    }
    switch (reg - nregs) {
    case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
    case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
    case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
    }
    return 0;
}

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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
    int nregs;

    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
    if (reg < nregs) {
        env->vfp.regs[reg] = ldfq_le_p(buf);
        return 8;
    }
    if (arm_feature(env, ARM_FEATURE_NEON)) {
        nregs += 16;
        if (reg < nregs) {
            env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
            return 16;
        }
    }
    switch (reg - nregs) {
    case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
    case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
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    case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
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    }
    return 0;
}

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static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
{
    switch (reg) {
    case 0 ... 31:
        /* 128 bit FP register */
        stfq_le_p(buf, env->vfp.regs[reg * 2]);
        stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
        return 16;
    case 32:
        /* FPSR */
        stl_p(buf, vfp_get_fpsr(env));
        return 4;
    case 33:
        /* FPCR */
        stl_p(buf, vfp_get_fpcr(env));
        return 4;
    default:
        return 0;
    }
}

static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
{
    switch (reg) {
    case 0 ... 31:
        /* 128 bit FP register */
        env->vfp.regs[reg * 2] = ldfq_le_p(buf);
        env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
        return 16;
    case 32:
        /* FPSR */
        vfp_set_fpsr(env, ldl_p(buf));
        return 4;
    case 33:
        /* FPCR */
        vfp_set_fpcr(env, ldl_p(buf));
        return 4;
    default:
        return 0;
    }
}

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static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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    if (cpreg_field_is_64bit(ri)) {
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        return CPREG_FIELD64(env, ri);
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    } else {
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        return CPREG_FIELD32(env, ri);
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    }
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}

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static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
                      uint64_t value)
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{
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    if (cpreg_field_is_64bit(ri)) {
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        CPREG_FIELD64(env, ri) = value;
    } else {
        CPREG_FIELD32(env, ri) = value;
    }
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}

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static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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    /* Raw read of a coprocessor register (as needed for migration, etc). */
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    if (ri->type & ARM_CP_CONST) {
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        return ri->resetvalue;
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    } else if (ri->raw_readfn) {
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        return ri->raw_readfn(env, ri);
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    } else if (ri->readfn) {
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        return ri->readfn(env, ri);
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    } else {
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        return raw_read(env, ri);
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    }
}

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static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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                             uint64_t v)
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{
    /* Raw write of a coprocessor register (as needed for migration, etc).
     * Note that constant registers are treated as write-ignored; the
     * caller should check for success by whether a readback gives the
     * value written.
     */
    if (ri->type & ARM_CP_CONST) {
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        return;
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    } else if (ri->raw_writefn) {
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        ri->raw_writefn(env, ri, v);
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    } else if (ri->writefn) {
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        ri->writefn(env, ri, v);
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    } else {
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        raw_write(env, ri, v);
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    }
}

bool write_cpustate_to_list(ARMCPU *cpu)
{
    /* Write the coprocessor state from cpu->env to the (index,value) list. */
    int i;
    bool ok = true;

    for (i = 0; i < cpu->cpreg_array_len; i++) {
        uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
        const ARMCPRegInfo *ri;
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        ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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        if (!ri) {
            ok = false;
            continue;
        }
        if (ri->type & ARM_CP_NO_MIGRATE) {
            continue;
        }
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        cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
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    }
    return ok;
}

bool write_list_to_cpustate(ARMCPU *cpu)
{
    int i;
    bool ok = true;

    for (i = 0; i < cpu->cpreg_array_len; i++) {
        uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
        uint64_t v = cpu->cpreg_values[i];
        const ARMCPRegInfo *ri;

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        ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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        if (!ri) {
            ok = false;
            continue;
        }
        if (ri->type & ARM_CP_NO_MIGRATE) {
            continue;
        }
        /* Write value and confirm it reads back as written
         * (to catch read-only registers and partially read-only
         * registers where the incoming migration value doesn't match)
         */
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        write_raw_cp_reg(&cpu->env, ri, v);
        if (read_raw_cp_reg(&cpu->env, ri) != v) {
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            ok = false;
        }
    }
    return ok;
}

static void add_cpreg_to_list(gpointer key, gpointer opaque)
{
    ARMCPU *cpu = opaque;
    uint64_t regidx;
    const ARMCPRegInfo *ri;

    regidx = *(uint32_t *)key;
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    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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    if (!(ri->type & ARM_CP_NO_MIGRATE)) {
        cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
        /* The value array need not be initialized at this point */
        cpu->cpreg_array_len++;
    }
}

static void count_cpreg(gpointer key, gpointer opaque)
{
    ARMCPU *cpu = opaque;
    uint64_t regidx;
    const ARMCPRegInfo *ri;

    regidx = *(uint32_t *)key;
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    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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    if (!(ri->type & ARM_CP_NO_MIGRATE)) {
        cpu->cpreg_array_len++;
    }
}

static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
{
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    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
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    if (aidx > bidx) {
        return 1;
    }
    if (aidx < bidx) {
        return -1;
    }
    return 0;
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}

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static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
{
    GList **plist = udata;

    *plist = g_list_prepend(*plist, key);
}

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void init_cpreg_list(ARMCPU *cpu)
{
    /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
     * Note that we require cpreg_tuples[] to be sorted by key ID.
     */
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    GList *keys = NULL;
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    int arraylen;

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    g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);

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    keys = g_list_sort(keys, cpreg_key_compare);

    cpu->cpreg_array_len = 0;

    g_list_foreach(keys, count_cpreg, cpu);

    arraylen = cpu->cpreg_array_len;
    cpu->cpreg_indexes = g_new(uint64_t, arraylen);
    cpu->cpreg_values = g_new(uint64_t, arraylen);
    cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
    cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
    cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
    cpu->cpreg_array_len = 0;

    g_list_foreach(keys, add_cpreg_to_list, cpu);

    assert(cpu->cpreg_array_len == arraylen);

    g_list_free(keys);
}

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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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    ARMCPU *cpu = arm_env_get_cpu(env);

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    env->cp15.c3 = value;
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    tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
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}

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static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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    ARMCPU *cpu = arm_env_get_cpu(env);

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    if (env->cp15.c13_fcse != value) {
        /* Unlike real hardware the qemu TLB uses virtual addresses,
         * not modified virtual addresses, so this causes a TLB flush.
         */
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        tlb_flush(CPU(cpu), 1);
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        env->cp15.c13_fcse = value;
    }
}
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static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
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{
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    ARMCPU *cpu = arm_env_get_cpu(env);

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    if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
        /* For VMSA (when not using the LPAE long descriptor page table
         * format) this register includes the ASID, so do a TLB flush.
         * For PMSA it is purely a process ID and no action is needed.
         */
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        tlb_flush(CPU(cpu), 1);
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    }
    env->cp15.c13_context = value;
}

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static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
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{
    /* Invalidate all (TLBIALL) */
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    ARMCPU *cpu = arm_env_get_cpu(env);

    tlb_flush(CPU(cpu), 1);
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}

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static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
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{
    /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
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    ARMCPU *cpu = arm_env_get_cpu(env);

    tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
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}

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static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           uint64_t value)
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{
    /* Invalidate by ASID (TLBIASID) */
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    ARMCPU *cpu = arm_env_get_cpu(env);

    tlb_flush(CPU(cpu), value == 0);
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}

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static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           uint64_t value)
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{
    /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
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    ARMCPU *cpu = arm_env_get_cpu(env);

    tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
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}

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static const ARMCPRegInfo cp_reginfo[] = {
    /* DBGDIDR: just RAZ. In particular this means the "debug architecture
     * version" bits will read as a reserved value, which should cause
     * Linux to not try to use the debug hardware.
     */
    { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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    /* MMU Domain access control / MPU write buffer control */
    { .name = "DACR", .cp = 15,
      .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
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      .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
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    { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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      .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
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    { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
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      .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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    /* ??? This covers not just the impdef TLB lockdown registers but also
     * some v7VMSA registers relating to TEX remap, so it is overly broad.
     */
    { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
      .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
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    /* MMU TLB control. Note that the wildcarding means we cover not just
     * the unified TLB ops but also the dside/iside/inner-shareable variants.
     */
    { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
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      .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
      .type = ARM_CP_NO_MIGRATE },
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    { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
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      .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
      .type = ARM_CP_NO_MIGRATE },
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    { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
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      .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
      .type = ARM_CP_NO_MIGRATE },
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    { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
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      .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
      .type = ARM_CP_NO_MIGRATE },
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    /* Cache maintenance ops; some of this space may be overridden later. */
    { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
      .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
      .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
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    REGINFO_SENTINEL
};

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static const ARMCPRegInfo not_v6_cp_reginfo[] = {
    /* Not all pre-v6 cores implemented this WFI, so this is slightly
     * over-broad.
     */
    { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_WFI },
    REGINFO_SENTINEL
};

static const ARMCPRegInfo not_v7_cp_reginfo[] = {
    /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
     * is UNPREDICTABLE; we choose to NOP as most implementations do).
     */
    { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
      .access = PL1_W, .type = ARM_CP_WFI },
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    /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
     * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
     * OMAPCP will override this space.
     */
    { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
      .resetvalue = 0 },
    { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
      .resetvalue = 0 },
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    /* v6 doesn't have the cache ID registers but Linux reads them anyway */
    { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
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      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
      .resetvalue = 0 },
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    REGINFO_SENTINEL
};

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static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
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{
    if (env->cp15.c1_coproc != value) {
        env->cp15.c1_coproc = value;
        /* ??? Is this safe when called from within a TB?  */
        tb_flush(env);
    }
}

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static const ARMCPRegInfo v6_cp_reginfo[] = {
    /* prefetch by MVA in v6, NOP in v7 */
    { .name = "MVA_prefetch",
      .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
      .access = PL0_W, .type = ARM_CP_NOP },
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    { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
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      .access = PL0_W, .type = ARM_CP_NOP },
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    { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
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      .access = PL0_W, .type = ARM_CP_NOP },
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    { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
      .resetvalue = 0, },
    /* Watchpoint Fault Address Register : should actually only be present
     * for 1136, 1176, 11MPCore.
     */
    { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
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    { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
      .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
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      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
      .resetvalue = 0, .writefn = cpacr_write },
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    REGINFO_SENTINEL
};

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static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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    /* Performance monitor registers user accessibility is controlled
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     * by PMUSERENR.
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     */
    if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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        return CP_ACCESS_TRAP;
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    }
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    return CP_ACCESS_OK;
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}

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#ifndef CONFIG_USER_ONLY
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static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                       uint64_t value)
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{
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    /* Don't computer the number of ticks in user mode */
    uint32_t temp_ticks;

    temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
                  get_ticks_per_sec() / 1000000;

    if (env->cp15.c9_pmcr & PMCRE) {
        /* If the counter is enabled */
        if (env->cp15.c9_pmcr & PMCRD) {
            /* Increment once every 64 processor clock cycles */
            env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
        } else {
            env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
        }
    }

    if (value & PMCRC) {
        /* The counter has been reset */
        env->cp15.c15_ccnt = 0;
    }

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    /* only the DP, X, D and E bits are writable */
    env->cp15.c9_pmcr &= ~0x39;
    env->cp15.c9_pmcr |= (value & 0x39);
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    if (env->cp15.c9_pmcr & PMCRE) {
        if (env->cp15.c9_pmcr & PMCRD) {
            /* Increment once every 64 processor clock cycles */
            temp_ticks /= 64;
        }
        env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
    }
}

static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
    uint32_t total_ticks;

    if (!(env->cp15.c9_pmcr & PMCRE)) {
        /* Counter is disabled, do not change value */
        return env->cp15.c15_ccnt;
    }

    total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
                  get_ticks_per_sec() / 1000000;

    if (env->cp15.c9_pmcr & PMCRD) {
        /* Increment once every 64 processor clock cycles */
        total_ticks /= 64;
    }
    return total_ticks - env->cp15.c15_ccnt;
}

static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
{
    uint32_t total_ticks;

    if (!(env->cp15.c9_pmcr & PMCRE)) {
        /* Counter is disabled, set the absolute value */
        env->cp15.c15_ccnt = value;
        return;
    }

    total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
                  get_ticks_per_sec() / 1000000;

    if (env->cp15.c9_pmcr & PMCRD) {
        /* Increment once every 64 processor clock cycles */
        total_ticks /= 64;
    }
    env->cp15.c15_ccnt = total_ticks - value;
577
}
578
#endif
579

580
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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                            uint64_t value)
{
    value &= (1 << 31);
    env->cp15.c9_pmcnten |= value;
}

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static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
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{
    value &= (1 << 31);
    env->cp15.c9_pmcnten &= ~value;
}

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static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
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{
    env->cp15.c9_pmovsr &= ~value;
}

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static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
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{
    env->cp15.c9_pmxevtyper = value & 0xff;
}

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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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                            uint64_t value)
{
    env->cp15.c9_pmuserenr = value & 1;
}

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static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
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{
    /* We have no event counters so only the C bit can be changed */
    value &= (1 << 31);
    env->cp15.c9_pminten |= value;
}

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static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
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{
    value &= (1 << 31);
    env->cp15.c9_pminten &= ~value;
}

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static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                       uint64_t value)
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{
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    /* Note that even though the AArch64 view of this register has bits
     * [10:0] all RES0 we can only mask the bottom 5, to comply with the
     * architectural requirements for bits which are RES0 only in some
     * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
     * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
     */
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    env->cp15.c12_vbar = value & ~0x1Ful;
}

639
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
    ARMCPU *cpu = arm_env_get_cpu(env);
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    return cpu->ccsidr[env->cp15.c0_cssel];
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}

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static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
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{
    env->cp15.c0_cssel = value & 0xf;
}

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static const ARMCPRegInfo v7_cp_reginfo[] = {
    /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
     * debug components
     */
    { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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    { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
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      .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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    /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
    { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
      .access = PL1_W, .type = ARM_CP_NOP },
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    /* Performance monitors are implementation defined in v7,
     * but with an ARM recommended set of registers, which we
     * follow (although we don't actually implement any counters)
     *
     * Performance registers fall into three categories:
     *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
     *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
     *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
     * For the cases controlled by PMUSERENR we must set .access to PL0_RW
     * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
     */
    { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
      .access = PL0_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
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      .writefn = pmcntenset_write,
      .accessfn = pmreg_access,
      .raw_writefn = raw_write },
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    { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
      .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
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      .accessfn = pmreg_access,
      .writefn = pmcntenclr_write,
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      .type = ARM_CP_NO_MIGRATE },
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    { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
      .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
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      .accessfn = pmreg_access,
      .writefn = pmovsr_write,
      .raw_writefn = raw_write },
    /* Unimplemented so WI. */
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    { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
691
      .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
692
    /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
693
     * We choose to RAZ/WI.
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     */
    { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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      .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
      .accessfn = pmreg_access },
698
#ifndef CONFIG_USER_ONLY
699
    { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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      .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
      .readfn = pmccntr_read, .writefn = pmccntr_write,
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      .accessfn = pmreg_access },
703
#endif
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    { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
      .access = PL0_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
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      .accessfn = pmreg_access, .writefn = pmxevtyper_write,
      .raw_writefn = raw_write },
    /* Unimplemented, RAZ/WI. */
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    { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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      .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
      .accessfn = pmreg_access },
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    { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
      .access = PL0_R | PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
      .resetvalue = 0,
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      .writefn = pmuserenr_write, .raw_writefn = raw_write },
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    { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
      .resetvalue = 0,
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      .writefn = pmintenset_write, .raw_writefn = raw_write },
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    { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
724
      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
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      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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      .resetvalue = 0, .writefn = pmintenclr_write, },
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    { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
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      .access = PL1_RW, .writefn = vbar_write,
      .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
      .resetvalue = 0 },
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    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
      .resetvalue = 0, },
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    { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
737
      .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
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    { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
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      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
      .writefn = csselr_write, .resetvalue = 0 },
    /* Auxiliary ID register: this actually has an IMPDEF value but for now
     * just RAZ for all cores:
     */
    { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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    /* MAIR can just read-as-written because we don't implement caches
     * and so don't need to care about memory attributes.
     */
    { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
      .resetvalue = 0 },
    /* For non-long-descriptor page tables these are PRRR and NMRR;
     * regardless they still act as reads-as-written for QEMU.
     * The override is necessary because of the overly-broad TLB_LOCKDOWN
     * definition.
     */
    { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
      .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
      .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
      .resetfn = arm_cp_reset_ignore },
    { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
      .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
      .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
      .resetfn = arm_cp_reset_ignore },
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    REGINFO_SENTINEL
};

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static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
772 773 774 775 776
{
    value &= 1;
    env->teecr = value;
}

777
static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
778 779
{
    if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
780
        return CP_ACCESS_TRAP;
781
    }
782
    return CP_ACCESS_OK;
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}

static const ARMCPRegInfo t2ee_cp_reginfo[] = {
    { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
      .resetvalue = 0,
      .writefn = teecr_write },
    { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
      .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
792
      .accessfn = teehbr_access, .resetvalue = 0 },
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    REGINFO_SENTINEL
};

796
static const ARMCPRegInfo v6k_cp_reginfo[] = {
797 798 799 800
    { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
      .access = PL0_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
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    { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
      .access = PL0_RW,
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      .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
      .resetfn = arm_cp_reset_ignore },
    { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
      .access = PL0_R|PL1_W,
      .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
809 810
    { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
      .access = PL0_R|PL1_W,
811 812 813 814
      .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
      .resetfn = arm_cp_reset_ignore },
    { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
815
      .access = PL1_RW,
816
      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
817 818 819
    REGINFO_SENTINEL
};

820 821
#ifndef CONFIG_USER_ONLY

822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
    if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
    /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
    if (arm_current_pl(env) == 0 &&
        !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
    /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
     * EL0[PV]TEN is zero.
     */
    if (arm_current_pl(env) == 0 &&
        !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

static CPAccessResult gt_pct_access(CPUARMState *env,
                                         const ARMCPRegInfo *ri)
{
    return gt_counter_access(env, GTIMER_PHYS);
}

static CPAccessResult gt_vct_access(CPUARMState *env,
                                         const ARMCPRegInfo *ri)
{
    return gt_counter_access(env, GTIMER_VIRT);
}

static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    return gt_timer_access(env, GTIMER_PHYS);
}

static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    return gt_timer_access(env, GTIMER_VIRT);
}

875 876
static uint64_t gt_get_countervalue(CPUARMState *env)
{
877
    return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
}

static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
{
    ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];

    if (gt->ctl & 1) {
        /* Timer enabled: calculate and set current ISTATUS, irq, and
         * reset timer to when ISTATUS next has to change
         */
        uint64_t count = gt_get_countervalue(&cpu->env);
        /* Note that this must be unsigned 64 bit arithmetic: */
        int istatus = count >= gt->cval;
        uint64_t nexttick;

        gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
        qemu_set_irq(cpu->gt_timer_outputs[timeridx],
                     (istatus && !(gt->ctl & 2)));
        if (istatus) {
            /* Next transition is when count rolls back over to zero */
            nexttick = UINT64_MAX;
        } else {
            /* Next transition is when we hit cval */
            nexttick = gt->cval;
        }
        /* Note that the desired next expiry time might be beyond the
         * signed-64-bit range of a QEMUTimer -- in this case we just
         * set the timer for as far in the future as possible. When the
         * timer expires we will reset the timer for any remaining period.
         */
        if (nexttick > INT64_MAX / GTIMER_SCALE) {
            nexttick = INT64_MAX / GTIMER_SCALE;
        }
911
        timer_mod(cpu->gt_timer[timeridx], nexttick);
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    } else {
        /* Timer disabled: ISTATUS and timer output always clear */
        gt->ctl &= ~4;
        qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
916
        timer_del(cpu->gt_timer[timeridx]);
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    }
}

static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
    ARMCPU *cpu = arm_env_get_cpu(env);
    int timeridx = ri->opc1 & 1;

925
    timer_del(cpu->gt_timer[timeridx]);
926 927
}

928
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
929
{
930
    return gt_get_countervalue(env);
931 932
}

933 934
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
935 936 937 938 939 940
{
    int timeridx = ri->opc1 & 1;

    env->cp15.c14_timer[timeridx].cval = value;
    gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
941 942

static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
943 944 945
{
    int timeridx = ri->crm & 1;

946 947
    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
                      gt_get_countervalue(env));
948 949
}

950 951
static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
952 953 954 955 956 957 958 959
{
    int timeridx = ri->crm & 1;

    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
        + sextract64(value, 0, 32);
    gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}

960 961
static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
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{
    ARMCPU *cpu = arm_env_get_cpu(env);
    int timeridx = ri->crm & 1;
    uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;

    env->cp15.c14_timer[timeridx].ctl = value & 3;
    if ((oldval ^ value) & 1) {
        /* Enable toggled */
        gt_recalc_timer(cpu, timeridx);
    } else if ((oldval & value) & 2) {
        /* IMASK toggled: don't need to recalculate,
         * just set the interrupt line based on ISTATUS
         */
        qemu_set_irq(cpu->gt_timer_outputs[timeridx],
                     (oldval & 4) && (value & 2));
    }
}

void arm_gt_ptimer_cb(void *opaque)
{
    ARMCPU *cpu = opaque;

    gt_recalc_timer(cpu, GTIMER_PHYS);
}

void arm_gt_vtimer_cb(void *opaque)
{
    ARMCPU *cpu = opaque;

    gt_recalc_timer(cpu, GTIMER_VIRT);
}

static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
    /* Note that CNTFRQ is purely reads-as-written for the benefit
     * of software; writing it doesn't actually change the timer frequency.
     * Our reset value matches the fixed frequency we implement the timer at.
     */
    { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1000 1001 1002 1003 1004 1005 1006 1007
      .type = ARM_CP_NO_MIGRATE,
      .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
      .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
      .resetfn = arm_cp_reset_ignore,
    },
    { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
      .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1008 1009 1010 1011
      .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
      .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
    },
    /* overall control: mostly access permissions */
1012 1013
    { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1014 1015 1016 1017 1018 1019
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
      .resetvalue = 0,
    },
    /* per-timer control */
    { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1020 1021 1022 1023 1024 1025 1026 1027 1028
      .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
      .accessfn = gt_ptimer_access,
      .fieldoffset = offsetoflow32(CPUARMState,
                                   cp15.c14_timer[GTIMER_PHYS].ctl),
      .resetfn = arm_cp_reset_ignore,
      .writefn = gt_ctl_write, .raw_writefn = raw_write,
    },
    { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1029
      .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1030
      .accessfn = gt_ptimer_access,
1031 1032
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
      .resetvalue = 0,
1033
      .writefn = gt_ctl_write, .raw_writefn = raw_write,
1034 1035
    },
    { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1036 1037 1038 1039 1040 1041 1042 1043 1044
      .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
      .accessfn = gt_vtimer_access,
      .fieldoffset = offsetoflow32(CPUARMState,
                                   cp15.c14_timer[GTIMER_VIRT].ctl),
      .resetfn = arm_cp_reset_ignore,
      .writefn = gt_ctl_write, .raw_writefn = raw_write,
    },
    { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1045
      .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1046
      .accessfn = gt_vtimer_access,
1047 1048
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
      .resetvalue = 0,
1049
      .writefn = gt_ctl_write, .raw_writefn = raw_write,
1050 1051 1052 1053
    },
    /* TimerValue views: a 32 bit downcounting view of the underlying state */
    { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1054
      .accessfn = gt_ptimer_access,
1055 1056
      .readfn = gt_tval_read, .writefn = gt_tval_write,
    },
1057 1058 1059 1060 1061
    { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
      .readfn = gt_tval_read, .writefn = gt_tval_write,
    },
1062 1063
    { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1064
      .accessfn = gt_vtimer_access,
1065 1066
      .readfn = gt_tval_read, .writefn = gt_tval_write,
    },
1067 1068 1069 1070 1071
    { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
      .readfn = gt_tval_read, .writefn = gt_tval_write,
    },
1072 1073 1074
    /* The counter itself */
    { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1075
      .accessfn = gt_pct_access,
1076 1077 1078 1079 1080 1081
      .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
    },
    { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
      .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
      .accessfn = gt_pct_access,
1082 1083 1084 1085
      .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
    },
    { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1086
      .accessfn = gt_vct_access,
1087 1088 1089 1090 1091 1092
      .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
    },
    { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
      .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
      .accessfn = gt_vct_access,
1093 1094 1095 1096 1097
      .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
    },
    /* Comparison value, indicating when the timer goes off */
    { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
      .access = PL1_RW | PL0_R,
1098
      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1099
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1100 1101 1102 1103 1104 1105 1106 1107 1108
      .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
      .writefn = gt_cval_write, .raw_writefn = raw_write,
    },
    { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
      .access = PL1_RW | PL0_R,
      .type = ARM_CP_IO,
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
      .resetvalue = 0, .accessfn = gt_vtimer_access,
1109
      .writefn = gt_cval_write, .raw_writefn = raw_write,
1110 1111 1112
    },
    { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
      .access = PL1_RW | PL0_R,
1113
      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1114
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1115 1116 1117 1118 1119 1120 1121 1122 1123
      .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
      .writefn = gt_cval_write, .raw_writefn = raw_write,
    },
    { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
      .access = PL1_RW | PL0_R,
      .type = ARM_CP_IO,
      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
      .resetvalue = 0, .accessfn = gt_vtimer_access,
1124
      .writefn = gt_cval_write, .raw_writefn = raw_write,
1125 1126 1127 1128 1129 1130
    },
    REGINFO_SENTINEL
};

#else
/* In user-mode none of the generic timer registers are accessible,
1131
 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1132 1133
 * so instead just don't register any of them.
 */
1134 1135 1136 1137
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
    REGINFO_SENTINEL
};

1138 1139
#endif

1140
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1141
{
1142 1143 1144
    if (arm_feature(env, ARM_FEATURE_LPAE)) {
        env->cp15.c7_par = value;
    } else if (arm_feature(env, ARM_FEATURE_V7)) {
1145 1146 1147 1148 1149 1150 1151 1152
        env->cp15.c7_par = value & 0xfffff6ff;
    } else {
        env->cp15.c7_par = value & 0xfffff1ff;
    }
}

#ifndef CONFIG_USER_ONLY
/* get_phys_addr() isn't present for user-mode-only targets */
1153 1154 1155 1156 1157 1158 1159 1160

/* Return true if extended addresses are enabled, ie this is an
 * LPAE implementation and we are using the long-descriptor translation
 * table format because the TTBCR EAE bit is set.
 */
static inline bool extended_addresses_enabled(CPUARMState *env)
{
    return arm_feature(env, ARM_FEATURE_LPAE)
1161
        && (env->cp15.c2_control & (1U << 31));
1162 1163
}

1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    if (ri->opc2 & 4) {
        /* Other states are only available with TrustZone; in
         * a non-TZ implementation these registers don't exist
         * at all, which is an Uncategorized trap. This underdecoding
         * is safe because the reginfo is NO_MIGRATE.
         */
        return CP_ACCESS_TRAP_UNCATEGORIZED;
    }
    return CP_ACCESS_OK;
}

1177
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1178
{
A
Avi Kivity 已提交
1179
    hwaddr phys_addr;
1180 1181 1182 1183 1184 1185 1186
    target_ulong page_size;
    int prot;
    int ret, is_user = ri->opc2 & 2;
    int access_type = ri->opc2 & 1;

    ret = get_phys_addr(env, value, access_type, is_user,
                        &phys_addr, &prot, &page_size);
1187 1188 1189 1190 1191 1192 1193 1194 1195
    if (extended_addresses_enabled(env)) {
        /* ret is a DFSR/IFSR value for the long descriptor
         * translation table format, but with WnR always clear.
         * Convert it to a 64-bit PAR.
         */
        uint64_t par64 = (1 << 11); /* LPAE bit always set */
        if (ret == 0) {
            par64 |= phys_addr & ~0xfffULL;
            /* We don't set the ATTR or SH fields in the PAR. */
1196
        } else {
1197 1198 1199 1200 1201 1202
            par64 |= 1; /* F */
            par64 |= (ret & 0x3f) << 1; /* FS */
            /* Note that S2WLK and FSTAGE are always zero, because we don't
             * implement virtualization and therefore there can't be a stage 2
             * fault.
             */
1203
        }
1204 1205
        env->cp15.c7_par = par64;
        env->cp15.c7_par_hi = par64 >> 32;
1206
    } else {
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
        /* ret is a DFSR/IFSR value for the short descriptor
         * translation table format (with WnR always clear).
         * Convert it to a 32-bit PAR.
         */
        if (ret == 0) {
            /* We do not set any attribute bits in the PAR */
            if (page_size == (1 << 24)
                && arm_feature(env, ARM_FEATURE_V7)) {
                env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
            } else {
                env->cp15.c7_par = phys_addr & 0xfffff000;
            }
        } else {
1220 1221
            env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
                ((ret & (1 << 12)) >> 6) |
1222 1223 1224
                ((ret & 0xf) << 1) | 1;
        }
        env->cp15.c7_par_hi = 0;
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
    }
}
#endif

static const ARMCPRegInfo vapa_cp_reginfo[] = {
    { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
      .writefn = par_write },
#ifndef CONFIG_USER_ONLY
    { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1236 1237
      .access = PL1_W, .accessfn = ats_access,
      .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1238 1239 1240 1241
#endif
    REGINFO_SENTINEL
};

1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
/* Return basic MPU access permission bits.  */
static uint32_t simple_mpu_ap_bits(uint32_t val)
{
    uint32_t ret;
    uint32_t mask;
    int i;
    ret = 0;
    mask = 3;
    for (i = 0; i < 16; i += 2) {
        ret |= (val >> i) & mask;
        mask <<= 2;
    }
    return ret;
}

/* Pad basic MPU access permission bits to extended format.  */
static uint32_t extended_mpu_ap_bits(uint32_t val)
{
    uint32_t ret;
    uint32_t mask;
    int i;
    ret = 0;
    mask = 3;
    for (i = 0; i < 16; i += 2) {
        ret |= (val & mask) << i;
        mask <<= 2;
    }
    return ret;
}

1272 1273
static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
1274 1275 1276 1277
{
    env->cp15.c5_data = extended_mpu_ap_bits(value);
}

1278
static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1279
{
1280
    return simple_mpu_ap_bits(env->cp15.c5_data);
1281 1282
}

1283 1284
static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
1285 1286 1287 1288
{
    env->cp15.c5_insn = extended_mpu_ap_bits(value);
}

1289
static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1290
{
1291
    return simple_mpu_ap_bits(env->cp15.c5_insn);
1292 1293 1294 1295
}

static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
    { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1296
      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1297 1298 1299
      .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
      .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
    { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1300
      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1301 1302 1303 1304 1305 1306 1307 1308
      .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
      .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
    { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
    { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1309 1310 1311 1312 1313 1314
    { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
    { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1315
    /* Protection region base and size registers */
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339
    { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
    { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
    { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
    { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
    { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
    { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
    { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
    { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
      .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
      .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1340 1341 1342
    REGINFO_SENTINEL
};

1343 1344
static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
1345
{
1346 1347
    int maskshift = extract32(value, 0, 3);

1348
    if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1349 1350 1351 1352 1353 1354 1355 1356 1357
        value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
    } else {
        value &= 7;
    }
    /* Note that we always calculate c2_mask and c2_base_mask, but
     * they are only used for short-descriptor tables (ie if EAE is 0);
     * for long-descriptor tables the TTBCR fields are used differently
     * and the c2_mask and c2_base_mask values are meaningless.
     */
1358
    env->cp15.c2_control = value;
1359 1360
    env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
    env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1361 1362
}

1363 1364
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
1365
{
1366 1367
    ARMCPU *cpu = arm_env_get_cpu(env);

1368 1369 1370 1371
    if (arm_feature(env, ARM_FEATURE_LPAE)) {
        /* With LPAE the TTBCR could result in a change of ASID
         * via the TTBCR.A1 bit, so do a TLB flush.
         */
1372
        tlb_flush(CPU(cpu), 1);
1373
    }
1374
    vmsa_ttbcr_raw_write(env, ri, value);
1375 1376
}

1377 1378 1379 1380 1381 1382 1383
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
    env->cp15.c2_base_mask = 0xffffc000u;
    env->cp15.c2_control = 0;
    env->cp15.c2_mask = 0;
}

1384 1385 1386
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                               uint64_t value)
{
1387 1388
    ARMCPU *cpu = arm_env_get_cpu(env);

1389
    /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1390
    tlb_flush(CPU(cpu), 1);
1391 1392 1393
    env->cp15.c2_control = value;
}

1394 1395 1396 1397 1398 1399 1400
static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
{
    /* 64 bit accesses to the TTBRs can change the ASID and so we
     * must flush the TLB.
     */
    if (cpreg_field_is_64bit(ri)) {
1401 1402 1403
        ARMCPU *cpu = arm_env_get_cpu(env);

        tlb_flush(CPU(cpu), 1);
1404 1405 1406 1407
    }
    raw_write(env, ri, value);
}

1408 1409 1410 1411 1412 1413 1414
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
    { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
    { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1415 1416 1417 1418 1419 1420 1421 1422
    { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
      .writefn = vmsa_ttbr_write, .resetvalue = 0 },
    { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
      .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1423 1424 1425 1426
    { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
      .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
      .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1427
      .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1428 1429 1430 1431
    { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
      .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
      .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1432 1433 1434
    { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
      .resetvalue = 0, },
1435 1436 1437
    REGINFO_SENTINEL
};

1438 1439
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
1440 1441 1442 1443 1444 1445 1446
{
    env->cp15.c15_ticonfig = value & 0xe7;
    /* The OS_TYPE bit in this register changes the reported CPUID! */
    env->cp15.c0_cpuid = (value & (1 << 5)) ?
        ARM_CPUID_TI915T : ARM_CPUID_TI925T;
}

1447 1448
static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
1449 1450 1451 1452
{
    env->cp15.c15_threadid = value & 0xffff;
}

1453 1454
static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           uint64_t value)
1455 1456
{
    /* Wait-for-interrupt (deprecated) */
1457
    cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1458 1459
}

1460 1461
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
1462 1463 1464 1465 1466 1467 1468 1469
{
    /* On OMAP there are registers indicating the max/min index of dcache lines
     * containing a dirty line; cache flush operations have to reset these.
     */
    env->cp15.c15_i_max = 0x000;
    env->cp15.c15_i_min = 0xff0;
}

1470 1471 1472 1473
static const ARMCPRegInfo omap_cp_reginfo[] = {
    { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
      .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
      .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
    { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .type = ARM_CP_NOP },
    { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
      .writefn = omap_ticonfig_write },
    { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
    { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW, .resetvalue = 0xff0,
      .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
    { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
      .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
      .writefn = omap_threadid_write },
    { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
      .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1492
      .type = ARM_CP_NO_MIGRATE,
1493 1494 1495 1496 1497 1498
      .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
    /* TODO: Peripheral port remap register:
     * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
     * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
     * when MMU is off.
     */
1499
    { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1500 1501
      .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
      .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1502
      .writefn = omap_cachemaint_write },
1503 1504 1505
    { .name = "C9", .cp = 15, .crn = 9,
      .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
      .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1506 1507 1508
    REGINFO_SENTINEL
};

1509 1510
static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value)
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524
{
    value &= 0x3fff;
    if (env->cp15.c15_cpar != value) {
        /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
        tb_flush(env);
        env->cp15.c15_cpar = value;
    }
}

static const ARMCPRegInfo xscale_cp_reginfo[] = {
    { .name = "XSCALE_CPAR",
      .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
      .writefn = xscale_cpar_write, },
1525 1526 1527 1528
    { .name = "XSCALE_AUXCR",
      .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
      .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
      .resetvalue = 0, },
1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
    REGINFO_SENTINEL
};

static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
    /* RAZ/WI the whole crn=15 space, when we don't have a more specific
     * implementation of this implementation-defined space.
     * Ideally this should eventually disappear in favour of actually
     * implementing the correct behaviour for all cores.
     */
    { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
      .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1540 1541
      .access = PL1_RW,
      .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1542
      .resetvalue = 0 },
1543 1544 1545
    REGINFO_SENTINEL
};

1546 1547 1548
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
    /* Cache status: RAZ because we have no cache so it's always clean */
    { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1549 1550
      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
      .resetvalue = 0 },
1551 1552 1553 1554 1555 1556
    REGINFO_SENTINEL
};

static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
    /* We never have a a block transfer operation in progress */
    { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1557 1558
      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
      .resetvalue = 0 },
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571
    /* The cache ops themselves: these all NOP for QEMU */
    { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
    { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
    { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
    { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
    { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
    { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1572 1573 1574 1575 1576 1577 1578 1579
    REGINFO_SENTINEL
};

static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
    /* The cache test-and-clean instructions always return (1 << 30)
     * to indicate that there are no dirty cache lines.
     */
    { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1580 1581
      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
      .resetvalue = (1 << 30) },
1582
    { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1583 1584
      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
      .resetvalue = (1 << 30) },
1585 1586 1587
    REGINFO_SENTINEL
};

1588 1589 1590 1591
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
    /* Ignore ReadBuffer accesses */
    { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
      .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1592 1593
      .access = PL1_RW, .resetvalue = 0,
      .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1594 1595 1596
    REGINFO_SENTINEL
};

1597
static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
P
Peter Maydell 已提交
1598
{
1599 1600
    CPUState *cs = CPU(arm_env_get_cpu(env));
    uint32_t mpidr = cs->cpu_index;
1601 1602
    /* We don't support setting cluster ID ([8..11]) (known as Aff1
     * in later ARM ARM versions), or any of the higher affinity level fields,
P
Peter Maydell 已提交
1603 1604 1605
     * so these bits always RAZ.
     */
    if (arm_feature(env, ARM_FEATURE_V7MP)) {
1606
        mpidr |= (1U << 31);
P
Peter Maydell 已提交
1607 1608 1609 1610 1611 1612
        /* Cores which are uniprocessor (non-coherent)
         * but still implement the MP extensions set
         * bit 30. (For instance, A9UP.) However we do
         * not currently model any of those cores.
         */
    }
1613
    return mpidr;
P
Peter Maydell 已提交
1614 1615 1616
}

static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1617 1618
    { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1619
      .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
P
Peter Maydell 已提交
1620 1621 1622
    REGINFO_SENTINEL
};

1623
static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1624
{
1625
    return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1626 1627
}

1628 1629
static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640
{
    env->cp15.c7_par_hi = value >> 32;
    env->cp15.c7_par = value;
}

static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
    env->cp15.c7_par_hi = 0;
    env->cp15.c7_par = 0;
}

1641
static const ARMCPRegInfo lpae_cp_reginfo[] = {
1642
    /* NOP AMAIR0/1: the override is because these clash with the rather
1643 1644
     * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
     */
1645 1646
    { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1647 1648
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
      .resetvalue = 0 },
1649
    /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1650 1651 1652
    { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
      .resetvalue = 0 },
1653 1654 1655 1656 1657
    /* 64 bit access versions of the (dummy) debug registers */
    { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
      .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
      .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1658 1659 1660 1661
    { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
      .access = PL1_RW, .type = ARM_CP_64BIT,
      .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
    { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1662 1663 1664
      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
      .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
      .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1665
    { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1666 1667 1668
      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
      .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
      .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1669 1670 1671
    REGINFO_SENTINEL
};

1672
static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1673
{
1674
    return vfp_get_fpcr(env);
1675 1676
}

1677 1678
static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
1679 1680 1681 1682
{
    vfp_set_fpcr(env, value);
}

1683
static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1684
{
1685
    return vfp_get_fpsr(env);
1686 1687
}

1688 1689
static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
1690 1691 1692 1693
{
    vfp_set_fpsr(env, value);
}

1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707
static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
{
    env->daif = value & PSTATE_DAIF;
}

1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
static CPAccessResult aa64_cacheop_access(CPUARMState *env,
                                          const ARMCPRegInfo *ri)
{
    /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
     * SCTLR_EL1.UCI is set.
     */
    if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

1720 1721 1722 1723
static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
                               uint64_t value)
{
    /* Invalidate by VA (AArch64 version) */
1724
    ARMCPU *cpu = arm_env_get_cpu(env);
1725
    uint64_t pageaddr = value << 12;
1726
    tlb_flush_page(CPU(cpu), pageaddr);
1727 1728 1729 1730 1731 1732
}

static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
{
    /* Invalidate by VA, all ASIDs (AArch64 version) */
1733
    ARMCPU *cpu = arm_env_get_cpu(env);
1734
    uint64_t pageaddr = value << 12;
1735
    tlb_flush_page(CPU(cpu), pageaddr);
1736 1737 1738 1739 1740 1741
}

static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
{
    /* Invalidate by ASID (AArch64 version) */
1742
    ARMCPU *cpu = arm_env_get_cpu(env);
1743
    int asid = extract64(value, 48, 16);
1744
    tlb_flush(CPU(cpu), asid == 0);
1745 1746
}

1747 1748 1749 1750 1751 1752 1753
static const ARMCPRegInfo v8_cp_reginfo[] = {
    /* Minimal set of EL0-visible registers. This will need to be expanded
     * significantly for system emulation of AArch64 CPUs.
     */
    { .name = "NZCV", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
      .access = PL0_RW, .type = ARM_CP_NZCV },
1754 1755 1756 1757 1758 1759
    { .name = "DAIF", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
      .type = ARM_CP_NO_MIGRATE,
      .access = PL0_RW, .accessfn = aa64_daif_access,
      .fieldoffset = offsetof(CPUARMState, daif),
      .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772
    { .name = "FPCR", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
      .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
    { .name = "FPSR", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
      .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
    /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
     * For system mode the DZP bit here will need to be computed, not constant.
     */
    { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
      .access = PL0_R, .type = ARM_CP_CONST,
      .resetvalue = 0x10 },
1773 1774 1775
    { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
      .access = PL1_R, .type = ARM_CP_CURRENTEL },
1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810
    /* Cache ops: all NOPs since we don't emulate caches */
    { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
      .access = PL0_W, .type = ARM_CP_NOP,
      .accessfn = aa64_cacheop_access },
    { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
      .access = PL0_W, .type = ARM_CP_NOP,
      .accessfn = aa64_cacheop_access },
    { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_NOP },
    { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
      .access = PL0_W, .type = ARM_CP_NOP,
      .accessfn = aa64_cacheop_access },
    { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
      .access = PL0_W, .type = ARM_CP_NOP,
      .accessfn = aa64_cacheop_access },
    { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_NOP },
1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
    /* TLBI operations */
    { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbiall_write },
    { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_va_write },
    { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_asid_write },
    { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_vaa_write },
    { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_va_write },
    { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_vaa_write },
    { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbiall_write },
    { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_va_write },
    { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_asid_write },
    { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_vaa_write },
    { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_va_write },
    { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
      .writefn = tlbi_aa64_vaa_write },
1860 1861 1862 1863 1864 1865
    /* Dummy implementation of monitor debug system control register:
     * we don't support debug.
     */
    { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1866 1867 1868 1869
    /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
    { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
      .access = PL1_W, .type = ARM_CP_NOP },
1870 1871 1872
    REGINFO_SENTINEL
};

1873 1874
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
1875
{
1876 1877
    ARMCPU *cpu = arm_env_get_cpu(env);

1878 1879 1880
    env->cp15.c1_sys = value;
    /* ??? Lots of these bits are not implemented.  */
    /* This may enable/disable the MMU, so do a TLB flush.  */
1881
    tlb_flush(CPU(cpu), 1);
1882 1883
}

1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
    /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
     * but the AArch32 CTR has its own reginfo struct)
     */
    if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
        return CP_ACCESS_TRAP;
    }
    return CP_ACCESS_OK;
}

1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925
static void define_aarch64_debug_regs(ARMCPU *cpu)
{
    /* Define breakpoint and watchpoint registers. These do nothing
     * but read as written, for now.
     */
    int i;

    for (i = 0; i < 16; i++) {
        ARMCPRegInfo dbgregs[] = {
            { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
              .access = PL1_RW,
              .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
            { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
              .access = PL1_RW,
              .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
            { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
              .access = PL1_RW,
              .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
            { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
              .access = PL1_RW,
              .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
               REGINFO_SENTINEL
        };
        define_arm_cp_regs(cpu, dbgregs);
    }
}

1926 1927 1928 1929 1930 1931 1932 1933 1934
void register_cp_regs_for_features(ARMCPU *cpu)
{
    /* Register all the coprocessor registers based on feature bits */
    CPUARMState *env = &cpu->env;
    if (arm_feature(env, ARM_FEATURE_M)) {
        /* M profile has no coprocessor registers */
        return;
    }

1935
    define_arm_cp_regs(cpu, cp_reginfo);
1936
    if (arm_feature(env, ARM_FEATURE_V6)) {
1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990
        /* The ID registers all have impdef reset values */
        ARMCPRegInfo v6_idregs[] = {
            { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_pfr0 },
            { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_pfr1 },
            { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_dfr0 },
            { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_afr0 },
            { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_mmfr0 },
            { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_mmfr1 },
            { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_mmfr2 },
            { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
              .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_mmfr3 },
            { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar0 },
            { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar1 },
            { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar2 },
            { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar3 },
            { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar4 },
            { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_isar5 },
            /* 6..7 are as yet unallocated and must RAZ */
            { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = 0 },
            { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
              .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = 0 },
            REGINFO_SENTINEL
        };
        define_arm_cp_regs(cpu, v6_idregs);
1991 1992 1993 1994
        define_arm_cp_regs(cpu, v6_cp_reginfo);
    } else {
        define_arm_cp_regs(cpu, not_v6_cp_reginfo);
    }
1995 1996 1997
    if (arm_feature(env, ARM_FEATURE_V6K)) {
        define_arm_cp_regs(cpu, v6k_cp_reginfo);
    }
1998
    if (arm_feature(env, ARM_FEATURE_V7)) {
1999
        /* v7 performance monitor control register: same implementor
2000 2001
         * field as main ID register, and we implement only the cycle
         * count register.
2002
         */
2003
#ifndef CONFIG_USER_ONLY
2004 2005 2006
        ARMCPRegInfo pmcr = {
            .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
            .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2007
            .type = ARM_CP_IO,
2008
            .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2009 2010
            .accessfn = pmreg_access, .writefn = pmcr_write,
            .raw_writefn = raw_write,
2011
        };
2012 2013
        define_one_arm_cp_reg(cpu, &pmcr);
#endif
2014
        ARMCPRegInfo clidr = {
2015 2016
            .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
            .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2017 2018 2019
            .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
        };
        define_one_arm_cp_reg(cpu, &clidr);
2020
        define_arm_cp_regs(cpu, v7_cp_reginfo);
2021 2022
    } else {
        define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2023
    }
2024
    if (arm_feature(env, ARM_FEATURE_V8)) {
2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
        /* AArch64 ID registers, which all have impdef reset values */
        ARMCPRegInfo v8_idregs[] = {
            { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64pfr0 },
            { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64pfr1},
            { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64dfr0 },
            { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64dfr1 },
            { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64afr0 },
            { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64afr1 },
            { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64isar0 },
            { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64isar1 },
            { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64mmfr0 },
            { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
              .access = PL1_R, .type = ARM_CP_CONST,
              .resetvalue = cpu->id_aa64mmfr1 },
            REGINFO_SENTINEL
        };
        define_arm_cp_regs(cpu, v8_idregs);
2070
        define_arm_cp_regs(cpu, v8_cp_reginfo);
2071
        define_aarch64_debug_regs(cpu);
2072
    }
2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083
    if (arm_feature(env, ARM_FEATURE_MPU)) {
        /* These are the MPU registers prior to PMSAv6. Any new
         * PMSA core later than the ARM946 will require that we
         * implement the PMSAv6 or PMSAv7 registers, which are
         * completely different.
         */
        assert(!arm_feature(env, ARM_FEATURE_V6));
        define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
    } else {
        define_arm_cp_regs(cpu, vmsa_cp_reginfo);
    }
2084 2085 2086
    if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
        define_arm_cp_regs(cpu, t2ee_cp_reginfo);
    }
2087 2088 2089
    if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
        define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
    }
2090 2091 2092
    if (arm_feature(env, ARM_FEATURE_VAPA)) {
        define_arm_cp_regs(cpu, vapa_cp_reginfo);
    }
2093 2094 2095 2096 2097 2098 2099 2100 2101
    if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
        define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
    }
    if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
        define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
    }
    if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
        define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
    }
2102 2103 2104
    if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
        define_arm_cp_regs(cpu, omap_cp_reginfo);
    }
2105 2106 2107
    if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
        define_arm_cp_regs(cpu, strongarm_cp_reginfo);
    }
2108 2109 2110 2111 2112 2113
    if (arm_feature(env, ARM_FEATURE_XSCALE)) {
        define_arm_cp_regs(cpu, xscale_cp_reginfo);
    }
    if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
        define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
    }
2114 2115 2116
    if (arm_feature(env, ARM_FEATURE_LPAE)) {
        define_arm_cp_regs(cpu, lpae_cp_reginfo);
    }
2117 2118 2119 2120 2121 2122 2123 2124 2125
    /* Slightly awkwardly, the OMAP and StrongARM cores need all of
     * cp15 crn=0 to be writes-ignored, whereas for other cores they should
     * be read-only (ie write causes UNDEF exception).
     */
    {
        ARMCPRegInfo id_cp_reginfo[] = {
            /* Note that the MIDR isn't a simple constant register because
             * of the TI925 behaviour where writes to another register can
             * cause the MIDR value to change.
2126 2127 2128 2129
             *
             * Unimplemented registers in the c15 0 0 0 space default to
             * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
             * and friends override accordingly.
2130 2131
             */
            { .name = "MIDR",
2132
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2133
              .access = PL1_R, .resetvalue = cpu->midr,
2134
              .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2135 2136
              .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
              .type = ARM_CP_OVERRIDE },
2137 2138 2139
            { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
              .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2140 2141 2142
            { .name = "CTR",
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2143 2144 2145 2146
            { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
              .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
              .access = PL0_R, .accessfn = ctr_el0_access,
              .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
            { .name = "TCMTR",
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            { .name = "TLBTR",
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
            { .name = "DUMMY",
              .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            { .name = "DUMMY",
              .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            { .name = "DUMMY",
              .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            { .name = "DUMMY",
              .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            { .name = "DUMMY",
              .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
            REGINFO_SENTINEL
        };
        ARMCPRegInfo crn0_wi_reginfo = {
            .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
            .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
            .type = ARM_CP_NOP | ARM_CP_OVERRIDE
        };
        if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
            arm_feature(env, ARM_FEATURE_STRONGARM)) {
            ARMCPRegInfo *r;
            /* Register the blanket "writes ignored" value first to cover the
2180 2181 2182
             * whole space. Then update the specific ID registers to allow write
             * access, so that they ignore writes rather than causing them to
             * UNDEF.
2183 2184 2185 2186 2187 2188
             */
            define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
                r->access = PL1_RW;
            }
        }
2189
        define_arm_cp_regs(cpu, id_cp_reginfo);
2190 2191
    }

2192 2193 2194 2195
    if (arm_feature(env, ARM_FEATURE_MPIDR)) {
        define_arm_cp_regs(cpu, mpidr_cp_reginfo);
    }

2196 2197 2198 2199 2200 2201 2202 2203 2204
    if (arm_feature(env, ARM_FEATURE_AUXCR)) {
        ARMCPRegInfo auxcr = {
            .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
            .access = PL1_RW, .type = ARM_CP_CONST,
            .resetvalue = cpu->reset_auxcr
        };
        define_one_arm_cp_reg(cpu, &auxcr);
    }

2205 2206 2207 2208 2209 2210 2211 2212 2213
    if (arm_feature(env, ARM_FEATURE_CBAR)) {
        ARMCPRegInfo cbar = {
            .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
            .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
        };
        define_one_arm_cp_reg(cpu, &cbar);
    }

2214 2215 2216
    /* Generic registers whose values depend on the implementation */
    {
        ARMCPRegInfo sctlr = {
2217 2218
            .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
            .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2219
            .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2220 2221
            .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
            .raw_writefn = raw_write,
2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
        };
        if (arm_feature(env, ARM_FEATURE_XSCALE)) {
            /* Normally we would always end the TB on an SCTLR write, but Linux
             * arch/arm/mach-pxa/sleep.S expects two instructions following
             * an MMU enable to execute from cache.  Imitate this behaviour.
             */
            sctlr.type |= ARM_CP_SUPPRESS_TB_END;
        }
        define_one_arm_cp_reg(cpu, &sctlr);
    }
2232 2233
}

2234
ARMCPU *cpu_arm_init(const char *cpu_model)
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{
2236
    return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2237 2238 2239 2240
}

void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
2241
    CPUState *cs = CPU(cpu);
2242 2243
    CPUARMState *env = &cpu->env;

2244 2245 2246 2247 2248
    if (arm_feature(env, ARM_FEATURE_AARCH64)) {
        gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
                                 aarch64_fpu_gdb_set_reg,
                                 34, "aarch64-fpu.xml", 0);
    } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2249
        gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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2250 2251
                                 51, "arm-neon.xml", 0);
    } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2252
        gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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                                 35, "arm-vfp3.xml", 0);
    } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2255
        gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
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                                 19, "arm-vfp.xml", 0);
    }
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}

2260 2261
/* Sort alphabetically by type name, except for "any". */
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
2263 2264 2265
    ObjectClass *class_a = (ObjectClass *)a;
    ObjectClass *class_b = (ObjectClass *)b;
    const char *name_a, *name_b;
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2267 2268
    name_a = object_class_get_name(class_a);
    name_b = object_class_get_name(class_b);
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2269
    if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2270
        return 1;
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2271
    } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2272 2273 2274
        return -1;
    } else {
        return strcmp(name_a, name_b);
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    }
}

2278
static void arm_cpu_list_entry(gpointer data, gpointer user_data)
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2279
{
2280
    ObjectClass *oc = data;
2281
    CPUListState *s = user_data;
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2282 2283
    const char *typename;
    char *name;
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2285 2286
    typename = object_class_get_name(oc);
    name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2287
    (*s->cpu_fprintf)(s->file, "  %s\n",
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2288 2289
                      name);
    g_free(name);
2290 2291 2292 2293
}

void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
2294
    CPUListState s = {
2295 2296 2297 2298 2299 2300 2301 2302 2303 2304
        .file = f,
        .cpu_fprintf = cpu_fprintf,
    };
    GSList *list;

    list = object_class_get_list(TYPE_ARM_CPU, false);
    list = g_slist_sort(list, arm_cpu_list_compare);
    (*cpu_fprintf)(f, "Available CPUs:\n");
    g_slist_foreach(list, arm_cpu_list_entry, &s);
    g_slist_free(list);
2305 2306 2307 2308 2309 2310
#ifdef CONFIG_KVM
    /* The 'host' CPU type is dynamically registered only if KVM is
     * enabled, so we have to special-case it here:
     */
    (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
#endif
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}

2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343
static void arm_cpu_add_definition(gpointer data, gpointer user_data)
{
    ObjectClass *oc = data;
    CpuDefinitionInfoList **cpu_list = user_data;
    CpuDefinitionInfoList *entry;
    CpuDefinitionInfo *info;
    const char *typename;

    typename = object_class_get_name(oc);
    info = g_malloc0(sizeof(*info));
    info->name = g_strndup(typename,
                           strlen(typename) - strlen("-" TYPE_ARM_CPU));

    entry = g_malloc0(sizeof(*entry));
    entry->value = info;
    entry->next = *cpu_list;
    *cpu_list = entry;
}

CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
{
    CpuDefinitionInfoList *cpu_list = NULL;
    GSList *list;

    list = object_class_get_list(TYPE_ARM_CPU, false);
    g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
    g_slist_free(list);

    return cpu_list;
}

2344
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2345 2346
                                   void *opaque, int state,
                                   int crm, int opc1, int opc2)
2347 2348 2349 2350 2351 2352 2353
{
    /* Private utility function for define_one_arm_cp_reg_with_opaque():
     * add a single reginfo struct to the hash table.
     */
    uint32_t *key = g_new(uint32_t, 1);
    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
    int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
    if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
        /* The AArch32 view of a shared register sees the lower 32 bits
         * of a 64 bit backing field. It is not migratable as the AArch64
         * view handles that. AArch64 also handles reset.
         * We assume it is a cp15 register.
         */
        r2->cp = 15;
        r2->type |= ARM_CP_NO_MIGRATE;
        r2->resetfn = arm_cp_reset_ignore;
#ifdef HOST_WORDS_BIGENDIAN
        if (r2->fieldoffset) {
            r2->fieldoffset += sizeof(uint32_t);
        }
#endif
    }
    if (state == ARM_CP_STATE_AA64) {
        /* To allow abbreviation of ARMCPRegInfo
         * definitions, we treat cp == 0 as equivalent to
         * the value for "standard guest-visible sysreg".
         */
        if (r->cp == 0) {
            r2->cp = CP_REG_ARM64_SYSREG_CP;
        }
        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
                                  r2->opc0, opc1, opc2);
    } else {
        *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
    }
2382 2383 2384
    if (opaque) {
        r2->opaque = opaque;
    }
2385 2386 2387 2388
    /* reginfo passed to helpers is correct for the actual access,
     * and is never ARM_CP_STATE_BOTH:
     */
    r2->state = state;
2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426
    /* Make sure reginfo passed to helpers for wildcarded regs
     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
     */
    r2->crm = crm;
    r2->opc1 = opc1;
    r2->opc2 = opc2;
    /* By convention, for wildcarded registers only the first
     * entry is used for migration; the others are marked as
     * NO_MIGRATE so we don't try to transfer the register
     * multiple times. Special registers (ie NOP/WFI) are
     * never migratable.
     */
    if ((r->type & ARM_CP_SPECIAL) ||
        ((r->crm == CP_ANY) && crm != 0) ||
        ((r->opc1 == CP_ANY) && opc1 != 0) ||
        ((r->opc2 == CP_ANY) && opc2 != 0)) {
        r2->type |= ARM_CP_NO_MIGRATE;
    }

    /* Overriding of an existing definition must be explicitly
     * requested.
     */
    if (!(r->type & ARM_CP_OVERRIDE)) {
        ARMCPRegInfo *oldreg;
        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
            fprintf(stderr, "Register redefined: cp=%d %d bit "
                    "crn=%d crm=%d opc1=%d opc2=%d, "
                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
                    r2->crn, r2->crm, r2->opc1, r2->opc2,
                    oldreg->name, r2->name);
            g_assert_not_reached();
        }
    }
    g_hash_table_insert(cpu->cp_regs, key, r2);
}


2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                       const ARMCPRegInfo *r, void *opaque)
{
    /* Define implementations of coprocessor registers.
     * We store these in a hashtable because typically
     * there are less than 150 registers in a space which
     * is 16*16*16*8*8 = 262144 in size.
     * Wildcarding is supported for the crm, opc1 and opc2 fields.
     * If a register is defined twice then the second definition is
     * used, so this can be used to define some generic registers and
     * then override them with implementation specific variations.
     * At least one of the original and the second definition should
     * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
     * against accidental use.
2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451
     *
     * The state field defines whether the register is to be
     * visible in the AArch32 or AArch64 execution state. If the
     * state is set to ARM_CP_STATE_BOTH then we synthesise a
     * reginfo structure for the AArch32 view, which sees the lower
     * 32 bits of the 64 bit register.
     *
     * Only registers visible in AArch64 may set r->opc0; opc0 cannot
     * be wildcarded. AArch64 registers are always considered to be 64
     * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
     * the register, if any.
2452
     */
2453
    int crm, opc1, opc2, state;
2454 2455 2456 2457 2458 2459 2460 2461
    int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
    int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
    int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
    int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
    int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
    int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
    /* 64 bit registers have only CRm and Opc1 fields */
    assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507
    /* op0 only exists in the AArch64 encodings */
    assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
    /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
    assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
    /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
     * encodes a minimum access level for the register. We roll this
     * runtime check into our general permission check code, so check
     * here that the reginfo's specified permissions are strict enough
     * to encompass the generic architectural permission check.
     */
    if (r->state != ARM_CP_STATE_AA32) {
        int mask = 0;
        switch (r->opc1) {
        case 0: case 1: case 2:
            /* min_EL EL1 */
            mask = PL1_RW;
            break;
        case 3:
            /* min_EL EL0 */
            mask = PL0_RW;
            break;
        case 4:
            /* min_EL EL2 */
            mask = PL2_RW;
            break;
        case 5:
            /* unallocated encoding, so not possible */
            assert(false);
            break;
        case 6:
            /* min_EL EL3 */
            mask = PL3_RW;
            break;
        case 7:
            /* min_EL EL1, secure mode only (we don't check the latter) */
            mask = PL1_RW;
            break;
        default:
            /* broken reginfo with out-of-range opc1 */
            assert(false);
            break;
        }
        /* assert our permissions are not too lax (stricter is fine) */
        assert((r->access & ~mask) == 0);
    }

2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523
    /* Check that the register definition has enough info to handle
     * reads and writes if they are permitted.
     */
    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
        if (r->access & PL3_R) {
            assert(r->fieldoffset || r->readfn);
        }
        if (r->access & PL3_W) {
            assert(r->fieldoffset || r->writefn);
        }
    }
    /* Bad type field probably means missing sentinel at end of reg list */
    assert(cptype_valid(r->type));
    for (crm = crmmin; crm <= crmmax; crm++) {
        for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
            for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2524 2525 2526 2527 2528 2529 2530 2531
                for (state = ARM_CP_STATE_AA32;
                     state <= ARM_CP_STATE_AA64; state++) {
                    if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
                        continue;
                    }
                    add_cpreg_to_hashtable(cpu, r, opaque, state,
                                           crm, opc1, opc2);
                }
2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
            }
        }
    }
}

void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
                                    const ARMCPRegInfo *regs, void *opaque)
{
    /* Define a whole list of registers */
    const ARMCPRegInfo *r;
    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
    }
}

2547
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2548
{
2549
    return g_hash_table_lookup(cpregs, &encoded_cp);
2550 2551
}

2552 2553
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
2554 2555 2556 2557
{
    /* Helper coprocessor write function for write-ignore registers */
}

2558
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2559 2560 2561 2562 2563
{
    /* Helper coprocessor write function for read-as-zero registers */
    return 0;
}

2564 2565 2566 2567 2568
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
{
    /* Helper coprocessor reset function for do-nothing-on-reset registers */
}

2569
static int bad_mode_switch(CPUARMState *env, int mode)
2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588
{
    /* Return true if it is not valid for us to switch to
     * this CPU mode (ie all the UNPREDICTABLE cases in
     * the ARM ARM CPSRWriteByInstr pseudocode).
     */
    switch (mode) {
    case ARM_CPU_MODE_USR:
    case ARM_CPU_MODE_SYS:
    case ARM_CPU_MODE_SVC:
    case ARM_CPU_MODE_ABT:
    case ARM_CPU_MODE_UND:
    case ARM_CPU_MODE_IRQ:
    case ARM_CPU_MODE_FIQ:
        return 0;
    default:
        return 1;
    }
}

2589 2590 2591
uint32_t cpsr_read(CPUARMState *env)
{
    int ZF;
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2592 2593
    ZF = (env->ZF == 0);
    return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2594 2595 2596
        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
2597
        | (env->GE << 16) | (env->daif & CPSR_AIF);
2598 2599 2600 2601 2602
}

void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
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        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & CPSR_T)
        env->thumb = ((val & CPSR_T) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & CPSR_GE) {
        env->GE = (val >> 16) & 0xf;
    }

2624 2625 2626
    env->daif &= ~(CPSR_AIF & mask);
    env->daif |= val & CPSR_AIF & mask;

2627
    if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2628 2629 2630 2631 2632 2633 2634 2635 2636
        if (bad_mode_switch(env, val & CPSR_M)) {
            /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
             * We choose to ignore the attempt and leave the CPSR M field
             * untouched.
             */
            mask &= ~CPSR_M;
        } else {
            switch_mode(env, val & CPSR_M);
        }
2637 2638 2639 2640 2641
    }
    mask &= ~CACHED_CPSR_BITS;
    env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}

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/* Sign/zero extend */
uint32_t HELPER(sxtb16)(uint32_t x)
{
    uint32_t res;
    res = (uint16_t)(int8_t)x;
    res |= (uint32_t)(int8_t)(x >> 16) << 16;
    return res;
}

uint32_t HELPER(uxtb16)(uint32_t x)
{
    uint32_t res;
    res = (uint16_t)(uint8_t)x;
    res |= (uint32_t)(uint8_t)(x >> 16) << 16;
    return res;
}

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uint32_t HELPER(clz)(uint32_t x)
{
2661
    return clz32(x);
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}

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int32_t HELPER(sdiv)(int32_t num, int32_t den)
{
    if (den == 0)
      return 0;
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    if (num == INT_MIN && den == -1)
      return INT_MIN;
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    return num / den;
}

uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
{
    if (den == 0)
      return 0;
    return num / den;
}

uint32_t HELPER(rbit)(uint32_t x)
{
    x =  ((x & 0xff000000) >> 24)
       | ((x & 0x00ff0000) >> 8)
       | ((x & 0x0000ff00) << 8)
       | ((x & 0x000000ff) << 24);
    x =  ((x & 0xf0f0f0f0) >> 4)
       | ((x & 0x0f0f0f0f) << 4);
    x =  ((x & 0x88888888) >> 3)
       | ((x & 0x44444444) >> 1)
       | ((x & 0x22222222) << 1)
       | ((x & 0x11111111) << 3);
    return x;
}

2695
#if defined(CONFIG_USER_ONLY)
B
bellard 已提交
2696

2697
void arm_cpu_do_interrupt(CPUState *cs)
B
bellard 已提交
2698
{
2699
    cs->exception_index = -1;
B
bellard 已提交
2700 2701
}

2702 2703
int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
                             int mmu_idx)
B
bellard 已提交
2704
{
2705 2706 2707
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;

2708
    env->exception.vaddress = address;
B
bellard 已提交
2709
    if (rw == 2) {
2710
        cs->exception_index = EXCP_PREFETCH_ABORT;
B
bellard 已提交
2711
    } else {
2712
        cs->exception_index = EXCP_DATA_ABORT;
B
bellard 已提交
2713 2714 2715 2716
    }
    return 1;
}

P
pbrook 已提交
2717
/* These should probably raise undefined insn exceptions.  */
2718
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
P
pbrook 已提交
2719
{
2720 2721 2722
    ARMCPU *cpu = arm_env_get_cpu(env);

    cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
P
pbrook 已提交
2723 2724
}

2725
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
P
pbrook 已提交
2726
{
2727 2728 2729
    ARMCPU *cpu = arm_env_get_cpu(env);

    cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
P
pbrook 已提交
2730 2731 2732
    return 0;
}

2733
void switch_mode(CPUARMState *env, int mode)
B
bellard 已提交
2734
{
2735 2736 2737 2738 2739
    ARMCPU *cpu = arm_env_get_cpu(env);

    if (mode != ARM_CPU_MODE_USR) {
        cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
    }
B
bellard 已提交
2740 2741
}

2742
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
P
pbrook 已提交
2743
{
2744 2745 2746
    ARMCPU *cpu = arm_env_get_cpu(env);

    cpu_abort(CPU(cpu), "banked r13 write\n");
P
pbrook 已提交
2747 2748
}

2749
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
P
pbrook 已提交
2750
{
2751 2752 2753
    ARMCPU *cpu = arm_env_get_cpu(env);

    cpu_abort(CPU(cpu), "banked r13 read\n");
P
pbrook 已提交
2754 2755 2756
    return 0;
}

B
bellard 已提交
2757 2758 2759
#else

/* Map CPU modes onto saved register banks.  */
2760
int bank_number(int mode)
B
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2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776
{
    switch (mode) {
    case ARM_CPU_MODE_USR:
    case ARM_CPU_MODE_SYS:
        return 0;
    case ARM_CPU_MODE_SVC:
        return 1;
    case ARM_CPU_MODE_ABT:
        return 2;
    case ARM_CPU_MODE_UND:
        return 3;
    case ARM_CPU_MODE_IRQ:
        return 4;
    case ARM_CPU_MODE_FIQ:
        return 5;
    }
2777
    hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
B
bellard 已提交
2778 2779
}

2780
void switch_mode(CPUARMState *env, int mode)
B
bellard 已提交
2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
{
    int old_mode;
    int i;

    old_mode = env->uncached_cpsr & CPSR_M;
    if (mode == old_mode)
        return;

    if (old_mode == ARM_CPU_MODE_FIQ) {
        memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
P
pbrook 已提交
2791
        memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
B
bellard 已提交
2792 2793
    } else if (mode == ARM_CPU_MODE_FIQ) {
        memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
P
pbrook 已提交
2794
        memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
B
bellard 已提交
2795 2796
    }

2797
    i = bank_number(old_mode);
B
bellard 已提交
2798 2799 2800 2801
    env->banked_r13[i] = env->regs[13];
    env->banked_r14[i] = env->regs[14];
    env->banked_spsr[i] = env->spsr;

2802
    i = bank_number(mode);
B
bellard 已提交
2803 2804 2805 2806 2807
    env->regs[13] = env->banked_r13[i];
    env->regs[14] = env->banked_r14[i];
    env->spsr = env->banked_spsr[i];
}

P
pbrook 已提交
2808 2809
static void v7m_push(CPUARMState *env, uint32_t val)
{
2810 2811
    CPUState *cs = CPU(arm_env_get_cpu(env));

P
pbrook 已提交
2812
    env->regs[13] -= 4;
2813
    stl_phys(cs->as, env->regs[13], val);
P
pbrook 已提交
2814 2815 2816 2817
}

static uint32_t v7m_pop(CPUARMState *env)
{
2818
    CPUState *cs = CPU(arm_env_get_cpu(env));
P
pbrook 已提交
2819
    uint32_t val;
2820

2821
    val = ldl_phys(cs->as, env->regs[13]);
P
pbrook 已提交
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844
    env->regs[13] += 4;
    return val;
}

/* Switch to V7M main or process stack pointer.  */
static void switch_v7m_sp(CPUARMState *env, int process)
{
    uint32_t tmp;
    if (env->v7m.current_sp != process) {
        tmp = env->v7m.other_sp;
        env->v7m.other_sp = env->regs[13];
        env->regs[13] = tmp;
        env->v7m.current_sp = process;
    }
}

static void do_v7m_exception_exit(CPUARMState *env)
{
    uint32_t type;
    uint32_t xpsr;

    type = env->regs[15];
    if (env->v7m.exception != 0)
P
Paul Brook 已提交
2845
        armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
P
pbrook 已提交
2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868

    /* Switch to the target stack.  */
    switch_v7m_sp(env, (type & 4) != 0);
    /* Pop registers.  */
    env->regs[0] = v7m_pop(env);
    env->regs[1] = v7m_pop(env);
    env->regs[2] = v7m_pop(env);
    env->regs[3] = v7m_pop(env);
    env->regs[12] = v7m_pop(env);
    env->regs[14] = v7m_pop(env);
    env->regs[15] = v7m_pop(env);
    xpsr = v7m_pop(env);
    xpsr_write(env, xpsr, 0xfffffdff);
    /* Undo stack alignment.  */
    if (xpsr & 0x200)
        env->regs[13] |= 4;
    /* ??? The exception return type specifies Thread/Handler mode.  However
       this is also implied by the xPSR value. Not sure what to do
       if there is a mismatch.  */
    /* ??? Likewise for mismatches between the CONTROL register and the stack
       pointer.  */
}

2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899
/* Exception names for debug logging; note that not all of these
 * precisely correspond to architectural exceptions.
 */
static const char * const excnames[] = {
    [EXCP_UDEF] = "Undefined Instruction",
    [EXCP_SWI] = "SVC",
    [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
    [EXCP_DATA_ABORT] = "Data Abort",
    [EXCP_IRQ] = "IRQ",
    [EXCP_FIQ] = "FIQ",
    [EXCP_BKPT] = "Breakpoint",
    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
    [EXCP_STREX] = "QEMU intercept of STREX",
};

static inline void arm_log_exception(int idx)
{
    if (qemu_loglevel_mask(CPU_LOG_INT)) {
        const char *exc = NULL;

        if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
            exc = excnames[idx];
        }
        if (!exc) {
            exc = "unknown";
        }
        qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
    }
}

2900
void arm_v7m_cpu_do_interrupt(CPUState *cs)
P
pbrook 已提交
2901
{
2902 2903
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
P
pbrook 已提交
2904 2905 2906 2907
    uint32_t xpsr = xpsr_read(env);
    uint32_t lr;
    uint32_t addr;

2908
    arm_log_exception(cs->exception_index);
2909

P
pbrook 已提交
2910 2911 2912 2913 2914 2915 2916 2917 2918 2919
    lr = 0xfffffff1;
    if (env->v7m.current_sp)
        lr |= 4;
    if (env->v7m.exception == 0)
        lr |= 8;

    /* For exceptions we just mark as pending on the NVIC, and let that
       handle it.  */
    /* TODO: Need to escalate if the current priority is higher than the
       one we're raising.  */
2920
    switch (cs->exception_index) {
P
pbrook 已提交
2921
    case EXCP_UDEF:
P
Paul Brook 已提交
2922
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
P
pbrook 已提交
2923 2924
        return;
    case EXCP_SWI:
2925
        /* The PC already points to the next instruction.  */
P
Paul Brook 已提交
2926
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
P
pbrook 已提交
2927 2928 2929
        return;
    case EXCP_PREFETCH_ABORT:
    case EXCP_DATA_ABORT:
2930 2931 2932
        /* TODO: if we implemented the MPU registers, this is where we
         * should set the MMFAR, etc from exception.fsr and exception.vaddress.
         */
P
Paul Brook 已提交
2933
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
P
pbrook 已提交
2934 2935
        return;
    case EXCP_BKPT:
P
pbrook 已提交
2936 2937
        if (semihosting_enabled) {
            int nr;
2938
            nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
P
pbrook 已提交
2939 2940 2941
            if (nr == 0xab) {
                env->regs[15] += 2;
                env->regs[0] = do_arm_semihosting(env);
2942
                qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
P
pbrook 已提交
2943 2944 2945
                return;
            }
        }
P
Paul Brook 已提交
2946
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
P
pbrook 已提交
2947 2948
        return;
    case EXCP_IRQ:
P
Paul Brook 已提交
2949
        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
P
pbrook 已提交
2950 2951 2952 2953 2954
        break;
    case EXCP_EXCEPTION_EXIT:
        do_v7m_exception_exit(env);
        return;
    default:
2955
        cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
P
pbrook 已提交
2956 2957 2958 2959 2960 2961 2962
        return; /* Never happens.  Keep compiler happy.  */
    }

    /* Align stack pointer.  */
    /* ??? Should only do this if Configuration Control Register
       STACKALIGN bit is set.  */
    if (env->regs[13] & 4) {
P
pbrook 已提交
2963
        env->regs[13] -= 4;
P
pbrook 已提交
2964 2965
        xpsr |= 0x200;
    }
B
balrog 已提交
2966
    /* Switch to the handler mode.  */
P
pbrook 已提交
2967 2968 2969 2970 2971 2972 2973 2974 2975
    v7m_push(env, xpsr);
    v7m_push(env, env->regs[15]);
    v7m_push(env, env->regs[14]);
    v7m_push(env, env->regs[12]);
    v7m_push(env, env->regs[3]);
    v7m_push(env, env->regs[2]);
    v7m_push(env, env->regs[1]);
    v7m_push(env, env->regs[0]);
    switch_v7m_sp(env, 0);
2976 2977
    /* Clear IT bits */
    env->condexec_bits = 0;
P
pbrook 已提交
2978
    env->regs[14] = lr;
2979
    addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
P
pbrook 已提交
2980 2981 2982 2983
    env->regs[15] = addr & 0xfffffffe;
    env->thumb = addr & 1;
}

B
bellard 已提交
2984
/* Handle a CPU exception.  */
2985
void arm_cpu_do_interrupt(CPUState *cs)
B
bellard 已提交
2986
{
2987 2988
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
B
bellard 已提交
2989 2990 2991 2992 2993
    uint32_t addr;
    uint32_t mask;
    int new_mode;
    uint32_t offset;

2994 2995
    assert(!IS_M(env));

2996
    arm_log_exception(cs->exception_index);
2997

B
bellard 已提交
2998
    /* TODO: Vectored interrupt controller.  */
2999
    switch (cs->exception_index) {
B
bellard 已提交
3000 3001 3002 3003 3004 3005 3006 3007 3008 3009
    case EXCP_UDEF:
        new_mode = ARM_CPU_MODE_UND;
        addr = 0x04;
        mask = CPSR_I;
        if (env->thumb)
            offset = 2;
        else
            offset = 4;
        break;
    case EXCP_SWI:
3010 3011 3012
        if (semihosting_enabled) {
            /* Check for semihosting interrupt.  */
            if (env->thumb) {
3013 3014
                mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
                    & 0xff;
3015
            } else {
3016
                mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
P
Paul Brook 已提交
3017
                    & 0xffffff;
3018 3019 3020 3021 3022 3023 3024
            }
            /* Only intercept calls from privileged modes, to provide some
               semblance of security.  */
            if (((mask == 0x123456 && !env->thumb)
                    || (mask == 0xab && env->thumb))
                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
                env->regs[0] = do_arm_semihosting(env);
3025
                qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3026 3027 3028
                return;
            }
        }
B
bellard 已提交
3029 3030 3031
        new_mode = ARM_CPU_MODE_SVC;
        addr = 0x08;
        mask = CPSR_I;
3032
        /* The PC already points to the next instruction.  */
B
bellard 已提交
3033 3034
        offset = 0;
        break;
P
pbrook 已提交
3035
    case EXCP_BKPT:
P
pbrook 已提交
3036
        /* See if this is a semihosting syscall.  */
P
pbrook 已提交
3037
        if (env->thumb && semihosting_enabled) {
3038
            mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
P
pbrook 已提交
3039 3040 3041 3042
            if (mask == 0xab
                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
                env->regs[15] += 2;
                env->regs[0] = do_arm_semihosting(env);
3043
                qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
P
pbrook 已提交
3044 3045 3046
                return;
            }
        }
3047
        env->exception.fsr = 2;
P
pbrook 已提交
3048 3049
        /* Fall through to prefetch abort.  */
    case EXCP_PREFETCH_ABORT:
3050 3051
        env->cp15.c5_insn = env->exception.fsr;
        env->cp15.c6_insn = env->exception.vaddress;
3052 3053
        qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
                      env->cp15.c5_insn, env->cp15.c6_insn);
B
bellard 已提交
3054 3055 3056 3057 3058 3059
        new_mode = ARM_CPU_MODE_ABT;
        addr = 0x0c;
        mask = CPSR_A | CPSR_I;
        offset = 4;
        break;
    case EXCP_DATA_ABORT:
3060 3061
        env->cp15.c5_data = env->exception.fsr;
        env->cp15.c6_data = env->exception.vaddress;
3062 3063
        qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
                      env->cp15.c5_data, env->cp15.c6_data);
B
bellard 已提交
3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083
        new_mode = ARM_CPU_MODE_ABT;
        addr = 0x10;
        mask = CPSR_A | CPSR_I;
        offset = 8;
        break;
    case EXCP_IRQ:
        new_mode = ARM_CPU_MODE_IRQ;
        addr = 0x18;
        /* Disable IRQ and imprecise data aborts.  */
        mask = CPSR_A | CPSR_I;
        offset = 4;
        break;
    case EXCP_FIQ:
        new_mode = ARM_CPU_MODE_FIQ;
        addr = 0x1c;
        /* Disable FIQ, IRQ and imprecise data aborts.  */
        mask = CPSR_A | CPSR_I | CPSR_F;
        offset = 4;
        break;
    default:
3084
        cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
B
bellard 已提交
3085 3086 3087
        return; /* Never happens.  Keep compiler happy.  */
    }
    /* High vectors.  */
3088
    if (env->cp15.c1_sys & SCTLR_V) {
N
Nathan Rossi 已提交
3089
        /* when enabled, base address cannot be remapped.  */
B
bellard 已提交
3090
        addr += 0xffff0000;
N
Nathan Rossi 已提交
3091 3092 3093 3094 3095 3096 3097 3098 3099
    } else {
        /* ARM v7 architectures provide a vector base address register to remap
         * the interrupt vector table.
         * This register is only followed in non-monitor mode, and has a secure
         * and un-secure copy. Since the cpu is always in a un-secure operation
         * and is never in monitor mode this feature is always active.
         * Note: only bits 31:5 are valid.
         */
        addr += env->cp15.c12_vbar;
B
bellard 已提交
3100 3101 3102
    }
    switch_mode (env, new_mode);
    env->spsr = cpsr_read(env);
P
pbrook 已提交
3103 3104
    /* Clear IT bits.  */
    env->condexec_bits = 0;
3105
    /* Switch to the new mode, and to the correct instruction set.  */
3106
    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3107
    env->daif |= mask;
3108 3109 3110
    /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
     * and we should just guard the thumb mode on V4 */
    if (arm_feature(env, ARM_FEATURE_V4T)) {
3111
        env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3112
    }
B
bellard 已提交
3113 3114
    env->regs[14] = env->regs[15] + offset;
    env->regs[15] = addr;
3115
    cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
B
bellard 已提交
3116 3117 3118 3119 3120
}

/* Check section/page access permissions.
   Returns the page protection flags, or zero if the access is not
   permitted.  */
3121
static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3122
                           int access_type, int is_user)
B
bellard 已提交
3123
{
P
pbrook 已提交
3124 3125
  int prot_ro;

3126
  if (domain_prot == 3) {
B
bellard 已提交
3127
    return PAGE_READ | PAGE_WRITE;
3128
  }
B
bellard 已提交
3129

P
pbrook 已提交
3130 3131 3132 3133 3134
  if (access_type == 1)
      prot_ro = 0;
  else
      prot_ro = PAGE_READ;

B
bellard 已提交
3135 3136
  switch (ap) {
  case 0:
3137 3138 3139
      if (arm_feature(env, ARM_FEATURE_V7)) {
          return 0;
      }
P
pbrook 已提交
3140
      if (access_type == 1)
B
bellard 已提交
3141
          return 0;
3142 3143
      switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
      case SCTLR_S:
B
bellard 已提交
3144
          return is_user ? 0 : PAGE_READ;
3145
      case SCTLR_R:
B
bellard 已提交
3146 3147 3148 3149 3150 3151 3152 3153
          return PAGE_READ;
      default:
          return 0;
      }
  case 1:
      return is_user ? 0 : PAGE_READ | PAGE_WRITE;
  case 2:
      if (is_user)
P
pbrook 已提交
3154
          return prot_ro;
B
bellard 已提交
3155 3156 3157 3158
      else
          return PAGE_READ | PAGE_WRITE;
  case 3:
      return PAGE_READ | PAGE_WRITE;
P
pbrook 已提交
3159
  case 4: /* Reserved.  */
P
pbrook 已提交
3160 3161 3162 3163 3164
      return 0;
  case 5:
      return is_user ? 0 : prot_ro;
  case 6:
      return prot_ro;
P
pbrook 已提交
3165
  case 7:
3166
      if (!arm_feature (env, ARM_FEATURE_V6K))
P
pbrook 已提交
3167 3168
          return 0;
      return prot_ro;
B
bellard 已提交
3169 3170 3171 3172 3173
  default:
      abort();
  }
}

3174
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3175 3176 3177 3178
{
    uint32_t table;

    if (address & env->cp15.c2_mask)
3179
        table = env->cp15.ttbr1_el1 & 0xffffc000;
3180
    else
3181
        table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3182 3183 3184 3185 3186

    table |= (address >> 18) & 0x3ffc;
    return table;
}

3187
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
A
Avi Kivity 已提交
3188
                            int is_user, hwaddr *phys_ptr,
3189
                            int *prot, target_ulong *page_size)
B
bellard 已提交
3190
{
3191
    CPUState *cs = CPU(arm_env_get_cpu(env));
B
bellard 已提交
3192 3193 3194 3195 3196 3197
    int code;
    uint32_t table;
    uint32_t desc;
    int type;
    int ap;
    int domain;
3198
    int domain_prot;
A
Avi Kivity 已提交
3199
    hwaddr phys_addr;
B
bellard 已提交
3200

P
pbrook 已提交
3201 3202
    /* Pagetable walk.  */
    /* Lookup l1 descriptor.  */
3203
    table = get_level1_table_address(env, address);
3204
    desc = ldl_phys(cs->as, table);
P
pbrook 已提交
3205
    type = (desc & 3);
3206 3207
    domain = (desc >> 5) & 0x0f;
    domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
P
pbrook 已提交
3208
    if (type == 0) {
3209
        /* Section translation fault.  */
P
pbrook 已提交
3210 3211 3212
        code = 5;
        goto do_fault;
    }
3213
    if (domain_prot == 0 || domain_prot == 2) {
P
pbrook 已提交
3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224
        if (type == 2)
            code = 9; /* Section domain fault.  */
        else
            code = 11; /* Page domain fault.  */
        goto do_fault;
    }
    if (type == 2) {
        /* 1Mb section.  */
        phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
        ap = (desc >> 10) & 3;
        code = 13;
P
Paul Brook 已提交
3225
        *page_size = 1024 * 1024;
P
pbrook 已提交
3226 3227 3228 3229 3230 3231 3232 3233 3234
    } else {
        /* Lookup l2 entry.  */
	if (type == 1) {
	    /* Coarse pagetable.  */
	    table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
	} else {
	    /* Fine pagetable.  */
	    table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
	}
3235
        desc = ldl_phys(cs->as, table);
P
pbrook 已提交
3236 3237 3238 3239 3240 3241 3242
        switch (desc & 3) {
        case 0: /* Page translation fault.  */
            code = 7;
            goto do_fault;
        case 1: /* 64k page.  */
            phys_addr = (desc & 0xffff0000) | (address & 0xffff);
            ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
P
Paul Brook 已提交
3243
            *page_size = 0x10000;
P
pbrook 已提交
3244
            break;
P
pbrook 已提交
3245 3246
        case 2: /* 4k page.  */
            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3247
            ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
P
Paul Brook 已提交
3248
            *page_size = 0x1000;
P
pbrook 已提交
3249
            break;
P
pbrook 已提交
3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
        case 3: /* 1k page.  */
	    if (type == 1) {
		if (arm_feature(env, ARM_FEATURE_XSCALE)) {
		    phys_addr = (desc & 0xfffff000) | (address & 0xfff);
		} else {
		    /* Page translation fault.  */
		    code = 7;
		    goto do_fault;
		}
	    } else {
		phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
	    }
            ap = (desc >> 4) & 3;
P
Paul Brook 已提交
3263
            *page_size = 0x400;
P
pbrook 已提交
3264 3265
            break;
        default:
P
pbrook 已提交
3266 3267
            /* Never happens, but compiler isn't smart enough to tell.  */
            abort();
P
pbrook 已提交
3268
        }
P
pbrook 已提交
3269 3270
        code = 15;
    }
3271
    *prot = check_ap(env, ap, domain_prot, access_type, is_user);
P
pbrook 已提交
3272 3273 3274 3275
    if (!*prot) {
        /* Access permission fault.  */
        goto do_fault;
    }
3276
    *prot |= PAGE_EXEC;
P
pbrook 已提交
3277 3278 3279 3280 3281 3282
    *phys_ptr = phys_addr;
    return 0;
do_fault:
    return code | (domain << 4);
}

3283
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
A
Avi Kivity 已提交
3284
                            int is_user, hwaddr *phys_ptr,
3285
                            int *prot, target_ulong *page_size)
P
pbrook 已提交
3286
{
3287
    CPUState *cs = CPU(arm_env_get_cpu(env));
P
pbrook 已提交
3288 3289 3290 3291
    int code;
    uint32_t table;
    uint32_t desc;
    uint32_t xn;
3292
    uint32_t pxn = 0;
P
pbrook 已提交
3293 3294
    int type;
    int ap;
3295
    int domain = 0;
3296
    int domain_prot;
A
Avi Kivity 已提交
3297
    hwaddr phys_addr;
P
pbrook 已提交
3298 3299 3300

    /* Pagetable walk.  */
    /* Lookup l1 descriptor.  */
3301
    table = get_level1_table_address(env, address);
3302
    desc = ldl_phys(cs->as, table);
P
pbrook 已提交
3303
    type = (desc & 3);
3304 3305 3306 3307
    if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
        /* Section translation fault, or attempt to use the encoding
         * which is Reserved on implementations without PXN.
         */
P
pbrook 已提交
3308 3309
        code = 5;
        goto do_fault;
3310 3311 3312
    }
    if ((type == 1) || !(desc & (1 << 18))) {
        /* Page or Section.  */
3313
        domain = (desc >> 5) & 0x0f;
P
pbrook 已提交
3314
    }
3315 3316
    domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
    if (domain_prot == 0 || domain_prot == 2) {
3317
        if (type != 1) {
P
pbrook 已提交
3318
            code = 9; /* Section domain fault.  */
3319
        } else {
P
pbrook 已提交
3320
            code = 11; /* Page domain fault.  */
3321
        }
P
pbrook 已提交
3322 3323
        goto do_fault;
    }
3324
    if (type != 1) {
P
pbrook 已提交
3325 3326 3327
        if (desc & (1 << 18)) {
            /* Supersection.  */
            phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
P
Paul Brook 已提交
3328
            *page_size = 0x1000000;
B
bellard 已提交
3329
        } else {
P
pbrook 已提交
3330 3331
            /* Section.  */
            phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
P
Paul Brook 已提交
3332
            *page_size = 0x100000;
B
bellard 已提交
3333
        }
P
pbrook 已提交
3334 3335
        ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
        xn = desc & (1 << 4);
3336
        pxn = desc & 1;
P
pbrook 已提交
3337 3338
        code = 13;
    } else {
3339 3340 3341
        if (arm_feature(env, ARM_FEATURE_PXN)) {
            pxn = (desc >> 2) & 1;
        }
P
pbrook 已提交
3342 3343
        /* Lookup l2 entry.  */
        table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3344
        desc = ldl_phys(cs->as, table);
P
pbrook 已提交
3345 3346 3347 3348
        ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
        switch (desc & 3) {
        case 0: /* Page translation fault.  */
            code = 7;
B
bellard 已提交
3349
            goto do_fault;
P
pbrook 已提交
3350 3351 3352
        case 1: /* 64k page.  */
            phys_addr = (desc & 0xffff0000) | (address & 0xffff);
            xn = desc & (1 << 15);
P
Paul Brook 已提交
3353
            *page_size = 0x10000;
P
pbrook 已提交
3354 3355 3356 3357
            break;
        case 2: case 3: /* 4k page.  */
            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
            xn = desc & 1;
P
Paul Brook 已提交
3358
            *page_size = 0x1000;
P
pbrook 已提交
3359 3360 3361 3362
            break;
        default:
            /* Never happens, but compiler isn't smart enough to tell.  */
            abort();
B
bellard 已提交
3363
        }
P
pbrook 已提交
3364 3365
        code = 15;
    }
3366
    if (domain_prot == 3) {
3367 3368
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    } else {
3369 3370 3371
        if (pxn && !is_user) {
            xn = 1;
        }
3372 3373
        if (xn && access_type == 2)
            goto do_fault;
P
pbrook 已提交
3374

3375
        /* The simplified model uses AP[0] as an access control bit.  */
3376
        if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3377 3378 3379 3380
            /* Access flag fault.  */
            code = (code == 15) ? 6 : 3;
            goto do_fault;
        }
3381
        *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3382 3383 3384 3385 3386 3387 3388
        if (!*prot) {
            /* Access permission fault.  */
            goto do_fault;
        }
        if (!xn) {
            *prot |= PAGE_EXEC;
        }
3389
    }
P
pbrook 已提交
3390
    *phys_ptr = phys_addr;
B
bellard 已提交
3391 3392 3393 3394 3395
    return 0;
do_fault:
    return code | (domain << 4);
}

3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406
/* Fault type for long-descriptor MMU fault reporting; this corresponds
 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
 */
typedef enum {
    translation_fault = 1,
    access_fault = 2,
    permission_fault = 3,
} MMUFaultType;

static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
                              int access_type, int is_user,
A
Avi Kivity 已提交
3407
                              hwaddr *phys_ptr, int *prot,
3408 3409
                              target_ulong *page_size_ptr)
{
3410
    CPUState *cs = CPU(arm_env_get_cpu(env));
3411 3412 3413 3414 3415 3416 3417 3418
    /* Read an LPAE long-descriptor translation table. */
    MMUFaultType fault_type = translation_fault;
    uint32_t level = 1;
    uint32_t epd;
    uint32_t tsz;
    uint64_t ttbr;
    int ttbr_select;
    int n;
A
Avi Kivity 已提交
3419
    hwaddr descaddr;
3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456
    uint32_t tableattrs;
    target_ulong page_size;
    uint32_t attrs;

    /* Determine whether this address is in the region controlled by
     * TTBR0 or TTBR1 (or if it is in neither region and should fault).
     * This is a Non-secure PL0/1 stage 1 translation, so controlled by
     * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
     */
    uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
    uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
    if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
        /* there is a ttbr0 region and we are in it (high bits all zero) */
        ttbr_select = 0;
    } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
        /* there is a ttbr1 region and we are in it (high bits all one) */
        ttbr_select = 1;
    } else if (!t0sz) {
        /* ttbr0 region is "everything not in the ttbr1 region" */
        ttbr_select = 0;
    } else if (!t1sz) {
        /* ttbr1 region is "everything not in the ttbr0 region" */
        ttbr_select = 1;
    } else {
        /* in the gap between the two regions, this is a Translation fault */
        fault_type = translation_fault;
        goto do_fault;
    }

    /* Note that QEMU ignores shareability and cacheability attributes,
     * so we don't need to do anything with the SH, ORGN, IRGN fields
     * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
     * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
     * implement any ASID-like capability so we can ignore it (instead
     * we will always flush the TLB any time the ASID is changed).
     */
    if (ttbr_select == 0) {
3457
        ttbr = env->cp15.ttbr0_el1;
3458 3459 3460
        epd = extract32(env->cp15.c2_control, 7, 1);
        tsz = t0sz;
    } else {
3461
        ttbr = env->cp15.ttbr1_el1;
3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498
        epd = extract32(env->cp15.c2_control, 23, 1);
        tsz = t1sz;
    }

    if (epd) {
        /* Translation table walk disabled => Translation fault on TLB miss */
        goto do_fault;
    }

    /* If the region is small enough we will skip straight to a 2nd level
     * lookup. This affects the number of bits of the address used in
     * combination with the TTBR to find the first descriptor. ('n' here
     * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
     * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
     */
    if (tsz > 1) {
        level = 2;
        n = 14 - tsz;
    } else {
        n = 5 - tsz;
    }

    /* Clear the vaddr bits which aren't part of the within-region address,
     * so that we don't have to special case things when calculating the
     * first descriptor address.
     */
    address &= (0xffffffffU >> tsz);

    /* Now we can extract the actual base address from the TTBR */
    descaddr = extract64(ttbr, 0, 40);
    descaddr &= ~((1ULL << n) - 1);

    tableattrs = 0;
    for (;;) {
        uint64_t descriptor;

        descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3499
        descriptor = ldq_phys(cs->as, descaddr);
3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574
        if (!(descriptor & 1) ||
            (!(descriptor & 2) && (level == 3))) {
            /* Invalid, or the Reserved level 3 encoding */
            goto do_fault;
        }
        descaddr = descriptor & 0xfffffff000ULL;

        if ((descriptor & 2) && (level < 3)) {
            /* Table entry. The top five bits are attributes which  may
             * propagate down through lower levels of the table (and
             * which are all arranged so that 0 means "no effect", so
             * we can gather them up by ORing in the bits at each level).
             */
            tableattrs |= extract64(descriptor, 59, 5);
            level++;
            continue;
        }
        /* Block entry at level 1 or 2, or page entry at level 3.
         * These are basically the same thing, although the number
         * of bits we pull in from the vaddr varies.
         */
        page_size = (1 << (39 - (9 * level)));
        descaddr |= (address & (page_size - 1));
        /* Extract attributes from the descriptor and merge with table attrs */
        attrs = extract64(descriptor, 2, 10)
            | (extract64(descriptor, 52, 12) << 10);
        attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
        attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
        /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
         * means "force PL1 access only", which means forcing AP[1] to 0.
         */
        if (extract32(tableattrs, 2, 1)) {
            attrs &= ~(1 << 4);
        }
        /* Since we're always in the Non-secure state, NSTable is ignored. */
        break;
    }
    /* Here descaddr is the final physical address, and attributes
     * are all in attrs.
     */
    fault_type = access_fault;
    if ((attrs & (1 << 8)) == 0) {
        /* Access flag */
        goto do_fault;
    }
    fault_type = permission_fault;
    if (is_user && !(attrs & (1 << 4))) {
        /* Unprivileged access not enabled */
        goto do_fault;
    }
    *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
        /* XN or PXN */
        if (access_type == 2) {
            goto do_fault;
        }
        *prot &= ~PAGE_EXEC;
    }
    if (attrs & (1 << 5)) {
        /* Write access forbidden */
        if (access_type == 1) {
            goto do_fault;
        }
        *prot &= ~PAGE_WRITE;
    }

    *phys_ptr = descaddr;
    *page_size_ptr = page_size;
    return 0;

do_fault:
    /* Long-descriptor format IFSR/DFSR value */
    return (1 << 9) | (fault_type << 2) | level;
}

3575 3576
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
                             int access_type, int is_user,
A
Avi Kivity 已提交
3577
                             hwaddr *phys_ptr, int *prot)
P
pbrook 已提交
3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631
{
    int n;
    uint32_t mask;
    uint32_t base;

    *phys_ptr = address;
    for (n = 7; n >= 0; n--) {
	base = env->cp15.c6_region[n];
	if ((base & 1) == 0)
	    continue;
	mask = 1 << ((base >> 1) & 0x1f);
	/* Keep this shift separate from the above to avoid an
	   (undefined) << 32.  */
	mask = (mask << 1) - 1;
	if (((base ^ address) & ~mask) == 0)
	    break;
    }
    if (n < 0)
	return 2;

    if (access_type == 2) {
	mask = env->cp15.c5_insn;
    } else {
	mask = env->cp15.c5_data;
    }
    mask = (mask >> (n * 4)) & 0xf;
    switch (mask) {
    case 0:
	return 1;
    case 1:
	if (is_user)
	  return 1;
	*prot = PAGE_READ | PAGE_WRITE;
	break;
    case 2:
	*prot = PAGE_READ;
	if (!is_user)
	    *prot |= PAGE_WRITE;
	break;
    case 3:
	*prot = PAGE_READ | PAGE_WRITE;
	break;
    case 5:
	if (is_user)
	    return 1;
	*prot = PAGE_READ;
	break;
    case 6:
	*prot = PAGE_READ;
	break;
    default:
	/* Bad permission.  */
	return 1;
    }
3632
    *prot |= PAGE_EXEC;
P
pbrook 已提交
3633 3634 3635
    return 0;
}

3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658
/* get_phys_addr - get the physical address for this virtual address
 *
 * Find the physical address corresponding to the given virtual address,
 * by doing a translation table walk on MMU based systems or using the
 * MPU state on MPU based systems.
 *
 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
 * prot and page_size are not filled in, and the return value provides
 * information on why the translation aborted, in the format of a
 * DFSR/IFSR fault register, with the following caveats:
 *  * we honour the short vs long DFSR format differences.
 *  * the WnR bit is never set (the caller must do this).
 *  * for MPU based systems we don't bother to return a full FSR format
 *    value.
 *
 * @env: CPUARMState
 * @address: virtual address to get physical address for
 * @access_type: 0 for read, 1 for write, 2 for execute
 * @is_user: 0 for privileged access, 1 for user
 * @phys_ptr: set to the physical address corresponding to the virtual address
 * @prot: set to the permissions for the page containing phys_ptr
 * @page_size: set to the size of the page containing phys_ptr
 */
3659
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
P
pbrook 已提交
3660
                                int access_type, int is_user,
A
Avi Kivity 已提交
3661
                                hwaddr *phys_ptr, int *prot,
P
Paul Brook 已提交
3662
                                target_ulong *page_size)
P
pbrook 已提交
3663 3664 3665 3666 3667
{
    /* Fast Context Switch Extension.  */
    if (address < 0x02000000)
        address += env->cp15.c13_fcse;

3668
    if ((env->cp15.c1_sys & SCTLR_M) == 0) {
P
pbrook 已提交
3669 3670
        /* MMU/MPU disabled.  */
        *phys_ptr = address;
3671
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
P
Paul Brook 已提交
3672
        *page_size = TARGET_PAGE_SIZE;
P
pbrook 已提交
3673 3674
        return 0;
    } else if (arm_feature(env, ARM_FEATURE_MPU)) {
P
Paul Brook 已提交
3675
        *page_size = TARGET_PAGE_SIZE;
P
pbrook 已提交
3676 3677
	return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
				 prot);
3678 3679 3680
    } else if (extended_addresses_enabled(env)) {
        return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
                                  prot, page_size);
3681
    } else if (env->cp15.c1_sys & SCTLR_XP) {
P
pbrook 已提交
3682
        return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
P
Paul Brook 已提交
3683
                                prot, page_size);
P
pbrook 已提交
3684 3685
    } else {
        return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
P
Paul Brook 已提交
3686
                                prot, page_size);
P
pbrook 已提交
3687 3688 3689
    }
}

3690 3691
int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
                             int access_type, int mmu_idx)
B
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3692
{
3693 3694
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
A
Avi Kivity 已提交
3695
    hwaddr phys_addr;
P
Paul Brook 已提交
3696
    target_ulong page_size;
B
bellard 已提交
3697
    int prot;
3698
    int ret, is_user;
B
bellard 已提交
3699

3700
    is_user = mmu_idx == MMU_USER_IDX;
P
Paul Brook 已提交
3701 3702
    ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
                        &page_size);
B
bellard 已提交
3703 3704
    if (ret == 0) {
        /* Map a single [sub]page.  */
A
Avi Kivity 已提交
3705
        phys_addr &= ~(hwaddr)0x3ff;
B
bellard 已提交
3706
        address &= ~(uint32_t)0x3ff;
3707
        tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
P
Paul Brook 已提交
3708
        return 0;
B
bellard 已提交
3709 3710 3711
    }

    if (access_type == 2) {
3712
        cs->exception_index = EXCP_PREFETCH_ABORT;
B
bellard 已提交
3713
    } else {
3714 3715 3716
        if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
            ret |= (1 << 11);
        }
3717
        cs->exception_index = EXCP_DATA_ABORT;
B
bellard 已提交
3718
    }
3719 3720
    env->exception.vaddress = address;
    env->exception.fsr = ret;
B
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3721 3722 3723
    return 1;
}

3724
hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
B
bellard 已提交
3725
{
3726
    ARMCPU *cpu = ARM_CPU(cs);
A
Avi Kivity 已提交
3727
    hwaddr phys_addr;
P
Paul Brook 已提交
3728
    target_ulong page_size;
B
bellard 已提交
3729 3730 3731
    int prot;
    int ret;

3732
    ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
B
bellard 已提交
3733

3734
    if (ret != 0) {
B
bellard 已提交
3735
        return -1;
3736
    }
B
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3737 3738 3739 3740

    return phys_addr;
}

3741
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
P
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3742
{
3743 3744 3745
    if ((env->uncached_cpsr & CPSR_M) == mode) {
        env->regs[13] = val;
    } else {
3746
        env->banked_r13[bank_number(mode)] = val;
3747
    }
P
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3748 3749
}

3750
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
P
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3751
{
3752 3753 3754
    if ((env->uncached_cpsr & CPSR_M) == mode) {
        return env->regs[13];
    } else {
3755
        return env->banked_r13[bank_number(mode)];
3756
    }
P
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3757 3758
}

3759
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
P
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3760
{
3761 3762
    ARMCPU *cpu = arm_env_get_cpu(env);

P
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3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782
    switch (reg) {
    case 0: /* APSR */
        return xpsr_read(env) & 0xf8000000;
    case 1: /* IAPSR */
        return xpsr_read(env) & 0xf80001ff;
    case 2: /* EAPSR */
        return xpsr_read(env) & 0xff00fc00;
    case 3: /* xPSR */
        return xpsr_read(env) & 0xff00fdff;
    case 5: /* IPSR */
        return xpsr_read(env) & 0x000001ff;
    case 6: /* EPSR */
        return xpsr_read(env) & 0x0700fc00;
    case 7: /* IEPSR */
        return xpsr_read(env) & 0x0700edff;
    case 8: /* MSP */
        return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
    case 9: /* PSP */
        return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
    case 16: /* PRIMASK */
3783
        return (env->daif & PSTATE_I) != 0;
3784 3785
    case 17: /* BASEPRI */
    case 18: /* BASEPRI_MAX */
P
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3786
        return env->v7m.basepri;
3787
    case 19: /* FAULTMASK */
3788
        return (env->daif & PSTATE_F) != 0;
P
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3789 3790 3791 3792
    case 20: /* CONTROL */
        return env->v7m.control;
    default:
        /* ??? For debugging only.  */
3793
        cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
P
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3794 3795 3796 3797
        return 0;
    }
}

3798
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
P
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3799
{
3800 3801
    ARMCPU *cpu = arm_env_get_cpu(env);

P
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3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836
    switch (reg) {
    case 0: /* APSR */
        xpsr_write(env, val, 0xf8000000);
        break;
    case 1: /* IAPSR */
        xpsr_write(env, val, 0xf8000000);
        break;
    case 2: /* EAPSR */
        xpsr_write(env, val, 0xfe00fc00);
        break;
    case 3: /* xPSR */
        xpsr_write(env, val, 0xfe00fc00);
        break;
    case 5: /* IPSR */
        /* IPSR bits are readonly.  */
        break;
    case 6: /* EPSR */
        xpsr_write(env, val, 0x0600fc00);
        break;
    case 7: /* IEPSR */
        xpsr_write(env, val, 0x0600fc00);
        break;
    case 8: /* MSP */
        if (env->v7m.current_sp)
            env->v7m.other_sp = val;
        else
            env->regs[13] = val;
        break;
    case 9: /* PSP */
        if (env->v7m.current_sp)
            env->regs[13] = val;
        else
            env->v7m.other_sp = val;
        break;
    case 16: /* PRIMASK */
3837 3838 3839 3840 3841
        if (val & 1) {
            env->daif |= PSTATE_I;
        } else {
            env->daif &= ~PSTATE_I;
        }
P
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3842
        break;
3843
    case 17: /* BASEPRI */
P
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3844 3845
        env->v7m.basepri = val & 0xff;
        break;
3846
    case 18: /* BASEPRI_MAX */
P
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3847 3848 3849 3850
        val &= 0xff;
        if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
            env->v7m.basepri = val;
        break;
3851
    case 19: /* FAULTMASK */
3852 3853 3854 3855 3856
        if (val & 1) {
            env->daif |= PSTATE_F;
        } else {
            env->daif &= ~PSTATE_F;
        }
3857
        break;
P
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3858 3859 3860 3861 3862 3863
    case 20: /* CONTROL */
        env->v7m.control = val & 3;
        switch_v7m_sp(env, (val & 2) != 0);
        break;
    default:
        /* ??? For debugging only.  */
3864
        cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
P
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3865 3866 3867 3868
        return;
    }
}

B
bellard 已提交
3869
#endif
P
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3870 3871 3872 3873 3874 3875 3876

/* Note that signed overflow is undefined in C.  The following routines are
   careful to use unsigned types where modulo arithmetic is required.
   Failure to do so _will_ break on newer gcc.  */

/* Signed saturating arithmetic.  */

A
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3877
/* Perform 16-bit signed saturating addition.  */
P
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3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
{
    uint16_t res;

    res = a + b;
    if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
        if (a & 0x8000)
            res = 0x8000;
        else
            res = 0x7fff;
    }
    return res;
}

A
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3892
/* Perform 8-bit signed saturating addition.  */
P
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3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
{
    uint8_t res;

    res = a + b;
    if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
        if (a & 0x80)
            res = 0x80;
        else
            res = 0x7f;
    }
    return res;
}

A
aurel32 已提交
3907
/* Perform 16-bit signed saturating subtraction.  */
P
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3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
{
    uint16_t res;

    res = a - b;
    if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
        if (a & 0x8000)
            res = 0x8000;
        else
            res = 0x7fff;
    }
    return res;
}

A
aurel32 已提交
3922
/* Perform 8-bit signed saturating subtraction.  */
P
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3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
{
    uint8_t res;

    res = a - b;
    if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
        if (a & 0x80)
            res = 0x80;
        else
            res = 0x7f;
    }
    return res;
}

#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
#define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
#define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
#define PFX q

#include "op_addsub.h"

/* Unsigned saturating arithmetic.  */
P
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3946
static inline uint16_t add16_usat(uint16_t a, uint16_t b)
P
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3947 3948 3949 3950 3951 3952 3953 3954
{
    uint16_t res;
    res = a + b;
    if (res < a)
        res = 0xffff;
    return res;
}

P
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3955
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
P
pbrook 已提交
3956
{
3957
    if (a > b)
P
pbrook 已提交
3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973
        return a - b;
    else
        return 0;
}

static inline uint8_t add8_usat(uint8_t a, uint8_t b)
{
    uint8_t res;
    res = a + b;
    if (res < a)
        res = 0xff;
    return res;
}

static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
{
3974
    if (a > b)
P
pbrook 已提交
3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990
        return a - b;
    else
        return 0;
}

#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
#define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
#define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
#define PFX uq

#include "op_addsub.h"

/* Signed modulo arithmetic.  */
#define SARITH16(a, b, n, op) do { \
    int32_t sum; \
3991
    sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
P
pbrook 已提交
3992 3993 3994 3995 3996 3997 3998
    RESULT(sum, n, 16); \
    if (sum >= 0) \
        ge |= 3 << (n * 2); \
    } while(0)

#define SARITH8(a, b, n, op) do { \
    int32_t sum; \
3999
    sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
P
pbrook 已提交
4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019
    RESULT(sum, n, 8); \
    if (sum >= 0) \
        ge |= 1 << n; \
    } while(0)


#define ADD16(a, b, n) SARITH16(a, b, n, +)
#define SUB16(a, b, n) SARITH16(a, b, n, -)
#define ADD8(a, b, n)  SARITH8(a, b, n, +)
#define SUB8(a, b, n)  SARITH8(a, b, n, -)
#define PFX s
#define ARITH_GE

#include "op_addsub.h"

/* Unsigned modulo arithmetic.  */
#define ADD16(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
    RESULT(sum, n, 16); \
4020
    if ((sum >> 16) == 1) \
P
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4021 4022 4023 4024 4025 4026 4027
        ge |= 3 << (n * 2); \
    } while(0)

#define ADD8(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
    RESULT(sum, n, 8); \
4028 4029
    if ((sum >> 8) == 1) \
        ge |= 1 << n; \
P
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4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044
    } while(0)

#define SUB16(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
    RESULT(sum, n, 16); \
    if ((sum >> 16) == 0) \
        ge |= 3 << (n * 2); \
    } while(0)

#define SUB8(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
    RESULT(sum, n, 8); \
    if ((sum >> 8) == 0) \
4045
        ge |= 1 << n; \
P
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4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114
    } while(0)

#define PFX u
#define ARITH_GE

#include "op_addsub.h"

/* Halved signed arithmetic.  */
#define ADD16(a, b, n) \
  RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
  RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
  RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
  RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
#define PFX sh

#include "op_addsub.h"

/* Halved unsigned arithmetic.  */
#define ADD16(a, b, n) \
  RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
  RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
  RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
  RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define PFX uh

#include "op_addsub.h"

static inline uint8_t do_usad(uint8_t a, uint8_t b)
{
    if (a > b)
        return a - b;
    else
        return b - a;
}

/* Unsigned sum of absolute byte differences.  */
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
{
    uint32_t sum;
    sum = do_usad(a, b);
    sum += do_usad(a >> 8, b >> 8);
    sum += do_usad(a >> 16, b >>16);
    sum += do_usad(a >> 24, b >> 24);
    return sum;
}

/* For ARMv6 SEL instruction.  */
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
{
    uint32_t mask;

    mask = 0;
    if (flags & 1)
        mask |= 0xff;
    if (flags & 2)
        mask |= 0xff00;
    if (flags & 4)
        mask |= 0xff0000;
    if (flags & 8)
        mask |= 0xff000000;
    return (a & mask) | (b & ~mask);
}

4115 4116
/* VFP support.  We follow the convention used for VFP instructions:
   Single precision routines have a "s" suffix, double precision a
P
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4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129
   "d" suffix.  */

/* Convert host exception flags to vfp form.  */
static inline int vfp_exceptbits_from_host(int host_bits)
{
    int target_bits = 0;

    if (host_bits & float_flag_invalid)
        target_bits |= 1;
    if (host_bits & float_flag_divbyzero)
        target_bits |= 2;
    if (host_bits & float_flag_overflow)
        target_bits |= 4;
4130
    if (host_bits & (float_flag_underflow | float_flag_output_denormal))
P
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4131 4132 4133
        target_bits |= 8;
    if (host_bits & float_flag_inexact)
        target_bits |= 0x10;
4134 4135
    if (host_bits & float_flag_input_denormal)
        target_bits |= 0x80;
P
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4136 4137 4138
    return target_bits;
}

4139
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
P
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4140 4141 4142 4143 4144 4145 4146 4147
{
    int i;
    uint32_t fpscr;

    fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
            | (env->vfp.vec_len << 16)
            | (env->vfp.vec_stride << 20);
    i = get_float_exception_flags(&env->vfp.fp_status);
4148
    i |= get_float_exception_flags(&env->vfp.standard_fp_status);
P
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4149 4150 4151 4152
    fpscr |= vfp_exceptbits_from_host(i);
    return fpscr;
}

4153
uint32_t vfp_get_fpscr(CPUARMState *env)
4154 4155 4156 4157
{
    return HELPER(vfp_get_fpscr)(env);
}

P
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4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172
/* Convert vfp exception flags to target form.  */
static inline int vfp_exceptbits_to_host(int target_bits)
{
    int host_bits = 0;

    if (target_bits & 1)
        host_bits |= float_flag_invalid;
    if (target_bits & 2)
        host_bits |= float_flag_divbyzero;
    if (target_bits & 4)
        host_bits |= float_flag_overflow;
    if (target_bits & 8)
        host_bits |= float_flag_underflow;
    if (target_bits & 0x10)
        host_bits |= float_flag_inexact;
4173 4174
    if (target_bits & 0x80)
        host_bits |= float_flag_input_denormal;
P
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4175 4176 4177
    return host_bits;
}

4178
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
P
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4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191
{
    int i;
    uint32_t changed;

    changed = env->vfp.xregs[ARM_VFP_FPSCR];
    env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
    env->vfp.vec_len = (val >> 16) & 7;
    env->vfp.vec_stride = (val >> 20) & 3;

    changed ^= val;
    if (changed & (3 << 22)) {
        i = (val >> 22) & 3;
        switch (i) {
4192
        case FPROUNDING_TIEEVEN:
P
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4193 4194
            i = float_round_nearest_even;
            break;
4195
        case FPROUNDING_POSINF:
P
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4196 4197
            i = float_round_up;
            break;
4198
        case FPROUNDING_NEGINF:
P
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4199 4200
            i = float_round_down;
            break;
4201
        case FPROUNDING_ZERO:
P
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4202 4203 4204 4205 4206
            i = float_round_to_zero;
            break;
        }
        set_float_rounding_mode(i, &env->vfp.fp_status);
    }
4207
    if (changed & (1 << 24)) {
4208
        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4209 4210
        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
    }
P
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4211 4212
    if (changed & (1 << 25))
        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
P
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4213

4214
    i = vfp_exceptbits_to_host(val);
P
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4215
    set_float_exception_flags(i, &env->vfp.fp_status);
4216
    set_float_exception_flags(0, &env->vfp.standard_fp_status);
P
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4217 4218
}

4219
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4220 4221 4222 4223
{
    HELPER(vfp_set_fpscr)(env, val);
}

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4224 4225 4226
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))

#define VFP_BINOP(name) \
4227
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
P
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4228
{ \
4229 4230
    float_status *fpst = fpstp; \
    return float32_ ## name(a, b, fpst); \
P
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4231
} \
4232
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
P
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4233
{ \
4234 4235
    float_status *fpst = fpstp; \
    return float64_ ## name(a, b, fpst); \
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4236 4237 4238 4239 4240
}
VFP_BINOP(add)
VFP_BINOP(sub)
VFP_BINOP(mul)
VFP_BINOP(div)
4241 4242 4243 4244
VFP_BINOP(min)
VFP_BINOP(max)
VFP_BINOP(minnum)
VFP_BINOP(maxnum)
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4245 4246 4247 4248 4249 4250 4251 4252 4253
#undef VFP_BINOP

float32 VFP_HELPER(neg, s)(float32 a)
{
    return float32_chs(a);
}

float64 VFP_HELPER(neg, d)(float64 a)
{
4254
    return float64_chs(a);
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4255 4256 4257 4258 4259 4260 4261 4262 4263
}

float32 VFP_HELPER(abs, s)(float32 a)
{
    return float32_abs(a);
}

float64 VFP_HELPER(abs, d)(float64 a)
{
4264
    return float64_abs(a);
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4265 4266
}

4267
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
P
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4268 4269 4270 4271
{
    return float32_sqrt(a, &env->vfp.fp_status);
}

4272
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
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4273 4274 4275 4276 4277 4278
{
    return float64_sqrt(a, &env->vfp.fp_status);
}

/* XXX: check quiet/signaling case */
#define DO_VFP_cmp(p, type) \
4279
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
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4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290
{ \
    uint32_t flags; \
    switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
    case 0: flags = 0x6; break; \
    case -1: flags = 0x8; break; \
    case 1: flags = 0x2; break; \
    default: case 2: flags = 0x3; break; \
    } \
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
} \
4291
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
P
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4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306
{ \
    uint32_t flags; \
    switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
    case 0: flags = 0x6; break; \
    case -1: flags = 0x8; break; \
    case 1: flags = 0x2; break; \
    default: case 2: flags = 0x3; break; \
    } \
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
}
DO_VFP_cmp(s, float32)
DO_VFP_cmp(d, float64)
#undef DO_VFP_cmp

4307
/* Integer to float and float to integer conversions */
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4308

4309 4310 4311 4312
#define CONV_ITOF(name, fsz, sign) \
    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
{ \
    float_status *fpst = fpstp; \
4313
    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
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4314 4315
}

4316 4317 4318 4319 4320 4321 4322 4323 4324
#define CONV_FTOI(name, fsz, sign, round) \
uint32_t HELPER(name)(float##fsz x, void *fpstp) \
{ \
    float_status *fpst = fpstp; \
    if (float##fsz##_is_any_nan(x)) { \
        float_raise(float_flag_invalid, fpst); \
        return 0; \
    } \
    return float##fsz##_to_##sign##int32##round(x, fpst); \
P
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4325 4326
}

4327 4328 4329 4330
#define FLOAT_CONVS(name, p, fsz, sign) \
CONV_ITOF(vfp_##name##to##p, fsz, sign) \
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
P
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4331

4332 4333 4334 4335
FLOAT_CONVS(si, s, 32, )
FLOAT_CONVS(si, d, 64, )
FLOAT_CONVS(ui, s, 32, u)
FLOAT_CONVS(ui, d, 64, u)
P
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4336

4337 4338 4339
#undef CONV_ITOF
#undef CONV_FTOI
#undef FLOAT_CONVS
P
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4340 4341

/* floating point conversion */
4342
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
P
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4343
{
4344 4345 4346 4347 4348
    float64 r = float32_to_float64(x, &env->vfp.fp_status);
    /* ARM requires that S<->D conversion of any kind of NaN generates
     * a quiet NaN by forcing the most significant frac bit to 1.
     */
    return float64_maybe_silence_nan(r);
P
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4349 4350
}

4351
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
P
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4352
{
4353 4354 4355 4356 4357
    float32 r =  float64_to_float32(x, &env->vfp.fp_status);
    /* ARM requires that S<->D conversion of any kind of NaN generates
     * a quiet NaN by forcing the most significant frac bit to 1.
     */
    return float32_maybe_silence_nan(r);
P
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4358 4359 4360
}

/* VFP3 fixed point conversion.  */
4361
#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4362 4363
float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
                                     void *fpstp) \
P
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4364
{ \
4365
    float_status *fpst = fpstp; \
4366
    float##fsz tmp; \
4367
    tmp = itype##_to_##float##fsz(x, fpst); \
4368
    return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4369 4370
}

4371 4372 4373 4374 4375
/* Notice that we want only input-denormal exception flags from the
 * scalbn operation: the other possible flags (overflow+inexact if
 * we overflow to infinity, output-denormal) aren't correct for the
 * complete scale-and-convert operation.
 */
4376 4377 4378 4379
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
                                             uint32_t shift, \
                                             void *fpstp) \
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4380
{ \
4381
    float_status *fpst = fpstp; \
4382
    int old_exc_flags = get_float_exception_flags(fpst); \
4383 4384
    float##fsz tmp; \
    if (float##fsz##_is_any_nan(x)) { \
4385
        float_raise(float_flag_invalid, fpst); \
4386
        return 0; \
4387
    } \
4388
    tmp = float##fsz##_scalbn(x, shift, fpst); \
4389 4390 4391
    old_exc_flags |= get_float_exception_flags(fpst) \
        & float_flag_input_denormal; \
    set_float_exception_flags(old_exc_flags, fpst); \
4392
    return float##fsz##_to_##itype##round(tmp, fpst); \
4393 4394
}

4395 4396
#define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4397 4398 4399 4400 4401 4402
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )

#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4403

4404 4405
VFP_CONV_FIX(sh, d, 64, 64, int16)
VFP_CONV_FIX(sl, d, 64, 64, int32)
4406
VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4407 4408
VFP_CONV_FIX(uh, d, 64, 64, uint16)
VFP_CONV_FIX(ul, d, 64, 64, uint32)
4409
VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4410 4411
VFP_CONV_FIX(sh, s, 32, 32, int16)
VFP_CONV_FIX(sl, s, 32, 32, int32)
4412
VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4413 4414
VFP_CONV_FIX(uh, s, 32, 32, uint16)
VFP_CONV_FIX(ul, s, 32, 32, uint32)
4415
VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
P
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4416
#undef VFP_CONV_FIX
4417 4418
#undef VFP_CONV_FIX_FLOAT
#undef VFP_CONV_FLOAT_FIX_ROUND
P
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4419

4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432
/* Set the current fp rounding mode and return the old one.
 * The argument is a softfloat float_round_ value.
 */
uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
{
    float_status *fp_status = &env->vfp.fp_status;

    uint32_t prev_rmode = get_float_rounding_mode(fp_status);
    set_float_rounding_mode(rmode, fp_status);

    return prev_rmode;
}

4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449
/* Set the current fp rounding mode in the standard fp status and return
 * the old one. This is for NEON instructions that need to change the
 * rounding mode but wish to use the standard FPSCR values for everything
 * else. Always set the rounding mode back to the correct value after
 * modifying it.
 * The argument is a softfloat float_round_ value.
 */
uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
{
    float_status *fp_status = &env->vfp.standard_fp_status;

    uint32_t prev_rmode = get_float_rounding_mode(fp_status);
    set_float_rounding_mode(rmode, fp_status);

    return prev_rmode;
}

P
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4450
/* Half precision conversions.  */
4451
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
P
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4452 4453
{
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4454 4455 4456 4457 4458
    float32 r = float16_to_float32(make_float16(a), ieee, s);
    if (ieee) {
        return float32_maybe_silence_nan(r);
    }
    return r;
P
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4459 4460
}

4461
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
P
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4462 4463
{
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4464 4465 4466 4467 4468
    float16 r = float32_to_float16(a, ieee, s);
    if (ieee) {
        r = float16_maybe_silence_nan(r);
    }
    return float16_val(r);
P
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4469 4470
}

4471
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4472 4473 4474 4475
{
    return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
}

4476
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4477 4478 4479 4480
{
    return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
}

4481
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4482 4483 4484 4485
{
    return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
}

4486
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4487 4488 4489 4490
{
    return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
}

4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510
float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
{
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
    float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
    if (ieee) {
        return float64_maybe_silence_nan(r);
    }
    return r;
}

uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
{
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
    float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
    if (ieee) {
        r = float16_maybe_silence_nan(r);
    }
    return float16_val(r);
}

4511
#define float32_two make_float32(0x40000000)
4512 4513
#define float32_three make_float32(0x40400000)
#define float32_one_point_five make_float32(0x3fc00000)
4514

4515
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
P
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4516
{
4517 4518 4519
    float_status *s = &env->vfp.standard_fp_status;
    if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
        (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4520 4521 4522
        if (!(float32_is_zero(a) || float32_is_zero(b))) {
            float_raise(float_flag_input_denormal, s);
        }
4523 4524 4525
        return float32_two;
    }
    return float32_sub(float32_two, float32_mul(a, b, s), s);
P
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4526 4527
}

4528
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
P
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4529
{
4530
    float_status *s = &env->vfp.standard_fp_status;
4531 4532 4533
    float32 product;
    if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
        (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4534 4535 4536
        if (!(float32_is_zero(a) || float32_is_zero(b))) {
            float_raise(float_flag_input_denormal, s);
        }
4537
        return float32_one_point_five;
4538
    }
4539 4540
    product = float32_mul(a, b, s);
    return float32_div(float32_sub(float32_three, product, s), float32_two, s);
P
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4541 4542
}

P
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4543 4544
/* NEON helpers.  */

4545 4546 4547 4548
/* Constants 256 and 512 are used in some helpers; we avoid relying on
 * int->float conversions at run-time.  */
#define float64_256 make_float64(0x4070000000000000LL)
#define float64_512 make_float64(0x4080000000000000LL)
4549 4550
#define float32_maxnorm make_float32(0x7f7fffff)
#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
4551

4552 4553 4554 4555
/* Reciprocal functions
 *
 * The algorithm that must be used to calculate the estimate
 * is specified by the ARM ARM, see FPRecipEstimate()
4556
 */
4557 4558

static float64 recip_estimate(float64 a, float_status *real_fp_status)
4559
{
4560 4561 4562
    /* These calculations mustn't set any fp exception flags,
     * so we use a local copy of the fp_status.
     */
4563
    float_status dummy_status = *real_fp_status;
4564
    float_status *s = &dummy_status;
4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583
    /* q = (int)(a * 512.0) */
    float64 q = float64_mul(float64_512, a, s);
    int64_t q_int = float64_to_int64_round_to_zero(q, s);

    /* r = 1.0 / (((double)q + 0.5) / 512.0) */
    q = int64_to_float64(q_int, s);
    q = float64_add(q, float64_half, s);
    q = float64_div(q, float64_512, s);
    q = float64_div(float64_one, q, s);

    /* s = (int)(256.0 * r + 0.5) */
    q = float64_mul(q, float64_256, s);
    q = float64_add(q, float64_half, s);
    q_int = float64_to_int64_round_to_zero(q, s);

    /* return (double)s / 256.0 */
    return float64_div(int64_to_float64(q_int, s), float64_256, s);
}

4584 4585
/* Common wrapper to call recip_estimate */
static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
P
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4586
{
4587 4588 4589 4590 4591
    uint64_t val64 = float64_val(num);
    uint64_t frac = extract64(val64, 0, 52);
    int64_t exp = extract64(val64, 52, 11);
    uint64_t sbit;
    float64 scaled, estimate;
4592

4593 4594 4595 4596 4597 4598 4599 4600 4601
    /* Generate the scaled number for the estimate function */
    if (exp == 0) {
        if (extract64(frac, 51, 1) == 0) {
            exp = -1;
            frac = extract64(frac, 0, 50) << 2;
        } else {
            frac = extract64(frac, 0, 51) << 1;
        }
    }
4602

4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658
    /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
    scaled = make_float64((0x3feULL << 52)
                          | extract64(frac, 44, 8) << 44);

    estimate = recip_estimate(scaled, fpst);

    /* Build new result */
    val64 = float64_val(estimate);
    sbit = 0x8000000000000000ULL & val64;
    exp = off - exp;
    frac = extract64(val64, 0, 52);

    if (exp == 0) {
        frac = 1ULL << 51 | extract64(frac, 1, 51);
    } else if (exp == -1) {
        frac = 1ULL << 50 | extract64(frac, 2, 50);
        exp = 0;
    }

    return make_float64(sbit | (exp << 52) | frac);
}

static bool round_to_inf(float_status *fpst, bool sign_bit)
{
    switch (fpst->float_rounding_mode) {
    case float_round_nearest_even: /* Round to Nearest */
        return true;
    case float_round_up: /* Round to +Inf */
        return !sign_bit;
    case float_round_down: /* Round to -Inf */
        return sign_bit;
    case float_round_to_zero: /* Round to Zero */
        return false;
    }

    g_assert_not_reached();
}

float32 HELPER(recpe_f32)(float32 input, void *fpstp)
{
    float_status *fpst = fpstp;
    float32 f32 = float32_squash_input_denormal(input, fpst);
    uint32_t f32_val = float32_val(f32);
    uint32_t f32_sbit = 0x80000000ULL & f32_val;
    int32_t f32_exp = extract32(f32_val, 23, 8);
    uint32_t f32_frac = extract32(f32_val, 0, 23);
    float64 f64, r64;
    uint64_t r64_val;
    int64_t r64_exp;
    uint64_t r64_frac;

    if (float32_is_any_nan(f32)) {
        float32 nan = f32;
        if (float32_is_signaling_nan(f32)) {
            float_raise(float_flag_invalid, fpst);
            nan = float32_maybe_silence_nan(f32);
4659
        }
4660 4661
        if (fpst->default_nan_mode) {
            nan =  float32_default_nan;
4662
        }
4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679
        return nan;
    } else if (float32_is_infinity(f32)) {
        return float32_set_sign(float32_zero, float32_is_neg(f32));
    } else if (float32_is_zero(f32)) {
        float_raise(float_flag_divbyzero, fpst);
        return float32_set_sign(float32_infinity, float32_is_neg(f32));
    } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
        /* Abs(value) < 2.0^-128 */
        float_raise(float_flag_overflow | float_flag_inexact, fpst);
        if (round_to_inf(fpst, f32_sbit)) {
            return float32_set_sign(float32_infinity, float32_is_neg(f32));
        } else {
            return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
        }
    } else if (f32_exp >= 253 && fpst->flush_to_zero) {
        float_raise(float_flag_underflow, fpst);
        return float32_set_sign(float32_zero, float32_is_neg(f32));
4680 4681 4682
    }


4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734
    f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
    r64 = call_recip_estimate(f64, 253, fpst);
    r64_val = float64_val(r64);
    r64_exp = extract64(r64_val, 52, 11);
    r64_frac = extract64(r64_val, 0, 52);

    /* result = sign : result_exp<7:0> : fraction<51:29>; */
    return make_float32(f32_sbit |
                        (r64_exp & 0xff) << 23 |
                        extract64(r64_frac, 29, 24));
}

float64 HELPER(recpe_f64)(float64 input, void *fpstp)
{
    float_status *fpst = fpstp;
    float64 f64 = float64_squash_input_denormal(input, fpst);
    uint64_t f64_val = float64_val(f64);
    uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
    int64_t f64_exp = extract64(f64_val, 52, 11);
    float64 r64;
    uint64_t r64_val;
    int64_t r64_exp;
    uint64_t r64_frac;

    /* Deal with any special cases */
    if (float64_is_any_nan(f64)) {
        float64 nan = f64;
        if (float64_is_signaling_nan(f64)) {
            float_raise(float_flag_invalid, fpst);
            nan = float64_maybe_silence_nan(f64);
        }
        if (fpst->default_nan_mode) {
            nan =  float64_default_nan;
        }
        return nan;
    } else if (float64_is_infinity(f64)) {
        return float64_set_sign(float64_zero, float64_is_neg(f64));
    } else if (float64_is_zero(f64)) {
        float_raise(float_flag_divbyzero, fpst);
        return float64_set_sign(float64_infinity, float64_is_neg(f64));
    } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
        /* Abs(value) < 2.0^-1024 */
        float_raise(float_flag_overflow | float_flag_inexact, fpst);
        if (round_to_inf(fpst, f64_sbit)) {
            return float64_set_sign(float64_infinity, float64_is_neg(f64));
        } else {
            return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
        }
    } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
        float_raise(float_flag_underflow, fpst);
        return float64_set_sign(float64_zero, float64_is_neg(f64));
    }
4735

4736 4737 4738 4739
    r64 = call_recip_estimate(f64, 2045, fpst);
    r64_val = float64_val(r64);
    r64_exp = extract64(r64_val, 52, 11);
    r64_frac = extract64(r64_val, 0, 52);
4740

4741 4742 4743 4744
    /* result = sign : result_exp<10:0> : fraction<51:0> */
    return make_float64(f64_sbit |
                        ((r64_exp & 0x7ff) << 52) |
                        r64_frac);
P
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4745 4746
}

4747 4748 4749
/* The algorithm that must be used to calculate the estimate
 * is specified by the ARM ARM.
 */
4750
static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
4751
{
4752 4753 4754
    /* These calculations mustn't set any fp exception flags,
     * so we use a local copy of the fp_status.
     */
4755
    float_status dummy_status = *real_fp_status;
4756
    float_status *s = &dummy_status;
4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801
    float64 q;
    int64_t q_int;

    if (float64_lt(a, float64_half, s)) {
        /* range 0.25 <= a < 0.5 */

        /* a in units of 1/512 rounded down */
        /* q0 = (int)(a * 512.0);  */
        q = float64_mul(float64_512, a, s);
        q_int = float64_to_int64_round_to_zero(q, s);

        /* reciprocal root r */
        /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
        q = int64_to_float64(q_int, s);
        q = float64_add(q, float64_half, s);
        q = float64_div(q, float64_512, s);
        q = float64_sqrt(q, s);
        q = float64_div(float64_one, q, s);
    } else {
        /* range 0.5 <= a < 1.0 */

        /* a in units of 1/256 rounded down */
        /* q1 = (int)(a * 256.0); */
        q = float64_mul(float64_256, a, s);
        int64_t q_int = float64_to_int64_round_to_zero(q, s);

        /* reciprocal root r */
        /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
        q = int64_to_float64(q_int, s);
        q = float64_add(q, float64_half, s);
        q = float64_div(q, float64_256, s);
        q = float64_sqrt(q, s);
        q = float64_div(float64_one, q, s);
    }
    /* r in units of 1/256 rounded to nearest */
    /* s = (int)(256.0 * r + 0.5); */

    q = float64_mul(q, float64_256,s );
    q = float64_add(q, float64_half, s);
    q_int = float64_to_int64_round_to_zero(q, s);

    /* return (double)s / 256.0;*/
    return float64_div(int64_to_float64(q_int, s), float64_256, s);
}

4802
float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
P
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4803
{
4804 4805 4806 4807 4808 4809 4810 4811
    float_status *s = fpstp;
    float32 f32 = float32_squash_input_denormal(input, s);
    uint32_t val = float32_val(f32);
    uint32_t f32_sbit = 0x80000000 & val;
    int32_t f32_exp = extract32(val, 23, 8);
    uint32_t f32_frac = extract32(val, 0, 23);
    uint64_t f64_frac;
    uint64_t val64;
4812 4813 4814
    int result_exp;
    float64 f64;

4815 4816 4817
    if (float32_is_any_nan(f32)) {
        float32 nan = f32;
        if (float32_is_signaling_nan(f32)) {
4818
            float_raise(float_flag_invalid, s);
4819
            nan = float32_maybe_silence_nan(f32);
4820
        }
4821 4822
        if (s->default_nan_mode) {
            nan =  float32_default_nan;
4823
        }
4824 4825
        return nan;
    } else if (float32_is_zero(f32)) {
4826
        float_raise(float_flag_divbyzero, s);
4827 4828
        return float32_set_sign(float32_infinity, float32_is_neg(f32));
    } else if (float32_is_neg(f32)) {
4829 4830
        float_raise(float_flag_invalid, s);
        return float32_default_nan;
4831
    } else if (float32_is_infinity(f32)) {
4832 4833 4834
        return float32_zero;
    }

4835
    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
4836
     * preserving the parity of the exponent.  */
4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848

    f64_frac = ((uint64_t) f32_frac) << 29;
    if (f32_exp == 0) {
        while (extract64(f64_frac, 51, 1) == 0) {
            f64_frac = f64_frac << 1;
            f32_exp = f32_exp-1;
        }
        f64_frac = extract64(f64_frac, 0, 51) << 1;
    }

    if (extract64(f32_exp, 0, 1) == 0) {
        f64 = make_float64(((uint64_t) f32_sbit) << 32
4849
                           | (0x3feULL << 52)
4850
                           | f64_frac);
4851
    } else {
4852
        f64 = make_float64(((uint64_t) f32_sbit) << 32
4853
                           | (0x3fdULL << 52)
4854
                           | f64_frac);
4855 4856
    }

4857
    result_exp = (380 - f32_exp) / 2;
4858

4859
    f64 = recip_sqrt_estimate(f64, s);
4860 4861 4862

    val64 = float64_val(f64);

4863
    val = ((result_exp & 0xff) << 23)
4864 4865
        | ((val64 >> 29)  & 0x7fffff);
    return make_float32(val);
P
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4866 4867
}

4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930
float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
{
    float_status *s = fpstp;
    float64 f64 = float64_squash_input_denormal(input, s);
    uint64_t val = float64_val(f64);
    uint64_t f64_sbit = 0x8000000000000000ULL & val;
    int64_t f64_exp = extract64(val, 52, 11);
    uint64_t f64_frac = extract64(val, 0, 52);
    int64_t result_exp;
    uint64_t result_frac;

    if (float64_is_any_nan(f64)) {
        float64 nan = f64;
        if (float64_is_signaling_nan(f64)) {
            float_raise(float_flag_invalid, s);
            nan = float64_maybe_silence_nan(f64);
        }
        if (s->default_nan_mode) {
            nan =  float64_default_nan;
        }
        return nan;
    } else if (float64_is_zero(f64)) {
        float_raise(float_flag_divbyzero, s);
        return float64_set_sign(float64_infinity, float64_is_neg(f64));
    } else if (float64_is_neg(f64)) {
        float_raise(float_flag_invalid, s);
        return float64_default_nan;
    } else if (float64_is_infinity(f64)) {
        return float64_zero;
    }

    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
     * preserving the parity of the exponent.  */

    if (f64_exp == 0) {
        while (extract64(f64_frac, 51, 1) == 0) {
            f64_frac = f64_frac << 1;
            f64_exp = f64_exp - 1;
        }
        f64_frac = extract64(f64_frac, 0, 51) << 1;
    }

    if (extract64(f64_exp, 0, 1) == 0) {
        f64 = make_float64(f64_sbit
                           | (0x3feULL << 52)
                           | f64_frac);
    } else {
        f64 = make_float64(f64_sbit
                           | (0x3fdULL << 52)
                           | f64_frac);
    }

    result_exp = (3068 - f64_exp) / 2;

    f64 = recip_sqrt_estimate(f64, s);

    result_frac = extract64(float64_val(f64), 0, 52);

    return make_float64(f64_sbit |
                        ((result_exp & 0x7ff) << 52) |
                        result_frac);
}

4931
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
P
pbrook 已提交
4932
{
4933
    float_status *s = fpstp;
4934 4935 4936 4937 4938 4939 4940 4941 4942
    float64 f64;

    if ((a & 0x80000000) == 0) {
        return 0xffffffff;
    }

    f64 = make_float64((0x3feULL << 52)
                       | ((int64_t)(a & 0x7fffffff) << 21));

4943
    f64 = recip_estimate(f64, s);
4944 4945

    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
P
pbrook 已提交
4946 4947
}

4948
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
P
pbrook 已提交
4949
{
4950
    float_status *fpst = fpstp;
4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964
    float64 f64;

    if ((a & 0xc0000000) == 0) {
        return 0xffffffff;
    }

    if (a & 0x80000000) {
        f64 = make_float64((0x3feULL << 52)
                           | ((uint64_t)(a & 0x7fffffff) << 21));
    } else { /* bits 31-30 == '01' */
        f64 = make_float64((0x3fdULL << 52)
                           | ((uint64_t)(a & 0x3fffffff) << 22));
    }

4965
    f64 = recip_sqrt_estimate(f64, fpst);
4966 4967

    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
P
pbrook 已提交
4968
}
4969

4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981
/* VFPv4 fused multiply-accumulate */
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
{
    float_status *fpst = fpstp;
    return float32_muladd(a, b, c, 0, fpst);
}

float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
{
    float_status *fpst = fpstp;
    return float64_muladd(a, b, c, 0, fpst);
}
4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026

/* ARMv8 round to integral */
float32 HELPER(rints_exact)(float32 x, void *fp_status)
{
    return float32_round_to_int(x, fp_status);
}

float64 HELPER(rintd_exact)(float64 x, void *fp_status)
{
    return float64_round_to_int(x, fp_status);
}

float32 HELPER(rints)(float32 x, void *fp_status)
{
    int old_flags = get_float_exception_flags(fp_status), new_flags;
    float32 ret;

    ret = float32_round_to_int(x, fp_status);

    /* Suppress any inexact exceptions the conversion produced */
    if (!(old_flags & float_flag_inexact)) {
        new_flags = get_float_exception_flags(fp_status);
        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
    }

    return ret;
}

float64 HELPER(rintd)(float64 x, void *fp_status)
{
    int old_flags = get_float_exception_flags(fp_status), new_flags;
    float64 ret;

    ret = float64_round_to_int(x, fp_status);

    new_flags = get_float_exception_flags(fp_status);

    /* Suppress any inexact exceptions the conversion produced */
    if (!(old_flags & float_flag_inexact)) {
        new_flags = get_float_exception_flags(fp_status);
        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
    }

    return ret;
}
5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054

/* Convert ARM rounding mode to softfloat */
int arm_rmode_to_sf(int rmode)
{
    switch (rmode) {
    case FPROUNDING_TIEAWAY:
        rmode = float_round_ties_away;
        break;
    case FPROUNDING_ODD:
        /* FIXME: add support for TIEAWAY and ODD */
        qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
                      rmode);
    case FPROUNDING_TIEEVEN:
    default:
        rmode = float_round_nearest_even;
        break;
    case FPROUNDING_POSINF:
        rmode = float_round_up;
        break;
    case FPROUNDING_NEGINF:
        rmode = float_round_down;
        break;
    case FPROUNDING_ZERO:
        rmode = float_round_to_zero;
        break;
    }
    return rmode;
}
5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091

static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
{
    memset(buf, 0, 4);

    if (bytes == 1) {
        buf[0] = val & 0xff;
    } else if (bytes == 2) {
        buf[0] = val & 0xff;
        buf[1] = (val >> 8) & 0xff;
    } else {
        buf[0] = val & 0xff;
        buf[1] = (val >> 8) & 0xff;
        buf[2] = (val >> 16) & 0xff;
        buf[3] = (val >> 24) & 0xff;
    }
}

uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
{
    uint8_t buf[4];

    crc_init_buffer(buf, val, bytes);

    /* zlib crc32 converts the accumulator and output to one's complement.  */
    return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
}

uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
{
    uint8_t buf[4];

    crc_init_buffer(buf, val, bytes);

    /* Linux crc32c converts the output to one's complement.  */
    return crc32c(acc, buf, bytes) ^ 0xffffffff;
}