1. 18 4月, 2014 7 次提交
    • P
      target-arm: Add support for generating exceptions with syndrome information · d4a2dc67
      Peter Maydell 提交于
      Add new helpers exception_with_syndrome (for generating an exception
      with syndrome information) and exception_uncategorized (for generating
      an exception with "Unknown or Uncategorized Reason", which have a syndrome
      register value of zero), and use them to generate the correct syndrome
      information for exceptions which are raised directly from generated code.
      
      This patch includes moving the A32/T32 gen_exception_insn functions
      further up in the source file; they will be needed for "VFP/Neon disabled"
      exception generation later.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      d4a2dc67
    • P
      target-arm: Provide correct syndrome information for cpreg access traps · 8bcbf37c
      Peter Maydell 提交于
      For exceptions taken to AArch64, if a coprocessor/system register
      access fails due to a trap or enable bit then the syndrome information
      must include details of the failing instruction (crn/crm/opc1/opc2
      fields, etc). Make the decoder construct the syndrome information
      at translate time so it can be passed at runtime to the access-check
      helper function and used as required.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      8bcbf37c
    • P
      target-arm: Define exception record for AArch64 exceptions · abf1172f
      Peter Maydell 提交于
      For AArch32 exceptions, the only information provided about
      the cause of an exception is the individual exception type (data
      abort, undef, etc), which we store in cs->exception_index. For
      AArch64, the CPU provides much more detail about the cause of
      the exception, which can be found in the syndrome register.
      Create a set of fields in CPUARMState which must be filled in
      whenever an exception is raised, so that exception entry can
      correctly fill in the syndrome register for the guest.
      This includes the information which in AArch32 appears in
      the DFAR and IFAR (fault address registers) and the DFSR
      and IFSR (fault status registers) for data aborts and
      prefetch aborts, since if we end up taking the MMU fault
      to AArch64 rather than AArch32 this will need to end up
      in different system registers.
      
      This patch does a refactoring which moves the setting of the
      AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception
      is raised to the point where it is taken. (This is no change
      for cores with an MMU, retains the existing clearly incorrect
      behaviour for ARM946 of trashing the MP access permissions
      registers which share the c5_data and c5_insn state fields,
      and has no effect for v7M because we don't implement its
      MPU fault status or address registers.)
      
      As a side effect of the cleanup we fix a bug in the AArch64
      linux-user mode code where we were passing a 64 bit fault
      address through the 32 bit c6_data/c6_insn fields: it now
      goes via the always-64-bit exception.vaddress.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      abf1172f
    • P
      target-arm: Implement AArch64 DAIF system register · c2b820fe
      Peter Maydell 提交于
      Implement the DAIF system register which is a view of the
      DAIF bits in PSTATE. To avoid needing a readfn, we widen
      the daif field in CPUARMState to uint64_t.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      c2b820fe
    • P
      target-arm: Split out private-to-target functions into internals.h · ccd38087
      Peter Maydell 提交于
      Currently cpu.h defines a mixture of functions and types needed by
      the rest of QEMU and those needed only by files within target-arm/.
      Split the latter out into a new header so they aren't needlessly
      exposed further than required.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      ccd38087
    • P
      Merge remote-tracking branch 'remotes/rth/tcg-aarch-6-5' into staging · c6138aab
      Peter Maydell 提交于
      * remotes/rth/tcg-aarch-6-5: (25 commits)
        tcg-aarch64: Use tcg_out_mov in preference to tcg_out_movr
        tcg-aarch64: Prefer unsigned offsets before signed offsets for ldst
        tcg-aarch64: Introduce tcg_out_insn_3312, _3310, _3313
        tcg-aarch64: Merge aarch64_ldst_get_data/type into tcg_out_op
        tcg-aarch64: Introduce tcg_out_insn_3507
        tcg-aarch64: Support stores of zero
        tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst
        tcg-aarch64: Pass qemu_ld/st arguments directly
        tcg-aarch64: Use TCGMemOp in qemu_ld/st
        tcg-aarch64: Use ADR to pass the return address to the ld/st helpers
        tcg-aarch64: Use tcg_out_call for qemu_ld/st
        tcg-aarch64: Avoid add with zero in tlb load
        tcg-aarch64: Implement tcg_register_jit
        tcg-aarch64: Introduce tcg_out_insn_3314
        tcg-aarch64: Reuse LR in translated code
        tcg-aarch64: Use CBZ and CBNZ
        tcg-aarch64: Create tcg_out_brcond
        tcg-aarch64: Use symbolic names for branches
        tcg-aarch64: Use adrp in tcg_out_movi
        tcg-aarch64: Special case small constants in tcg_out_movi
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      c6138aab
    • P
      Open 2.1 development tree · 5149e557
      Peter Maydell 提交于
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      5149e557
  2. 17 4月, 2014 26 次提交
  3. 15 4月, 2014 1 次提交
  4. 14 4月, 2014 6 次提交