intel_dp.c 38.8 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "drm_dp_helper.h"
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#define DP_LINK_STATUS_SIZE	6
#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

#define DP_LINK_CONFIGURATION_SIZE	9

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#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)

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struct intel_dp_priv {
	uint32_t output_reg;
	uint32_t DP;
	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
	bool has_audio;
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	int dpms_mode;
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	uint8_t link_bw;
	uint8_t lane_count;
	uint8_t dpcd[4];
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	struct intel_encoder *intel_encoder;
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	struct i2c_adapter adapter;
	struct i2c_algo_dp_aux_data algo;
};

static void
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intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
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		    uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);

static void
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intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
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void
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intel_edp_link_config (struct intel_encoder *intel_encoder,
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		int *lane_num, int *link_bw)
{
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	struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
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	*lane_num = dp_priv->lane_count;
	if (dp_priv->link_bw == DP_LINK_BW_1_62)
		*link_bw = 162000;
	else if (dp_priv->link_bw == DP_LINK_BW_2_7)
		*link_bw = 270000;
}

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static int
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intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
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{
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	struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
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	int max_lane_count = 4;

	if (dp_priv->dpcd[0] >= 0x11) {
		max_lane_count = dp_priv->dpcd[2] & 0x1f;
		switch (max_lane_count) {
		case 1: case 2: case 4:
			break;
		default:
			max_lane_count = 4;
		}
	}
	return max_lane_count;
}

static int
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intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
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{
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	struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
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	int max_link_bw = dp_priv->dpcd[1];

	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

static int
intel_dp_link_clock(uint8_t link_bw)
{
	if (link_bw == DP_LINK_BW_2_7)
		return 270000;
	else
		return 162000;
}

/* I think this is a fiction */
static int
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intel_dp_link_required(struct drm_device *dev,
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		       struct intel_encoder *intel_encoder, int pixel_clock)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	if (IS_eDP(intel_encoder))
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		return (pixel_clock * dev_priv->edp_bpp) / 8;
	else
		return pixel_clock * 3;
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}

static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct drm_encoder *encoder = intel_attached_encoder(connector);
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
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	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
	int max_lanes = intel_dp_max_lane_count(intel_encoder);
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	if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
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			> max_link_clock * max_lanes)
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		return MODE_CLOCK_HIGH;

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static int
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intel_dp_aux_ch(struct intel_encoder *intel_encoder,
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		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
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	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
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	uint32_t output_reg = dp_priv->output_reg;
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	struct drm_device *dev = intel_encoder->enc.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = output_reg + 0x10;
	uint32_t ch_data = ch_ctl + 4;
	int i;
	int recv_bytes;
	uint32_t ctl;
	uint32_t status;
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	uint32_t aux_clock_divider;
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	int try, precharge;
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 */
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	if (IS_eDP(intel_encoder)) {
		if (IS_GEN6(dev))
			aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
	} else if (HAS_PCH_SPLIT(dev))
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		aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
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	else
		aux_clock_divider = intel_hrawclk(dev) / 2;

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	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

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	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
		for (i = 0; i < send_bytes; i += 4) {
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			uint32_t    d = pack_aux(send + i, send_bytes - i);
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			I915_WRITE(ch_data + i, d);
		}
	
		ctl = (DP_AUX_CH_CTL_SEND_BUSY |
		       DP_AUX_CH_CTL_TIME_OUT_400us |
		       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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		       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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		       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
		       DP_AUX_CH_CTL_DONE |
		       DP_AUX_CH_CTL_TIME_OUT_ERROR |
		       DP_AUX_CH_CTL_RECEIVE_ERROR);
	
		/* Send the command and wait for it to complete */
		I915_WRITE(ch_ctl, ctl);
		(void) I915_READ(ch_ctl);
		for (;;) {
			udelay(100);
			status = I915_READ(ch_ctl);
			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
				break;
		}
	
		/* Clear done status and any errors */
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		I915_WRITE(ch_ctl, (status |
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				DP_AUX_CH_CTL_DONE |
				DP_AUX_CH_CTL_TIME_OUT_ERROR |
				DP_AUX_CH_CTL_RECEIVE_ERROR));
		(void) I915_READ(ch_ctl);
		if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		return -EBUSY;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		return -EIO;
	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		return -ETIMEDOUT;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);

	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
	
	for (i = 0; i < recv_bytes; i += 4) {
		uint32_t    d = I915_READ(ch_data + i);

		unpack_aux(d, recv + i, recv_bytes - i);
	}

	return recv_bytes;
}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
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		ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
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				      reply, reply_bytes);
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		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
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			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
}

static int
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intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
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{
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	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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	struct intel_dp_priv *dp_priv = container_of(adapter,
						     struct intel_dp_priv,
						     adapter);
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	struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
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	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
	int msg_bytes;
	int reply_bytes;
	int ret;

	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
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	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

	for (;;) {
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	  ret = intel_dp_aux_ch(intel_encoder,
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				msg, msg_bytes,
				reply, reply_bytes);
		if (ret < 0) {
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			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
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			return ret;
		}
		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
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			DRM_DEBUG_KMS("aux_ch nack\n");
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			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
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			DRM_DEBUG_KMS("aux_ch defer\n");
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			udelay(100);
			break;
		default:
			DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
			return -EREMOTEIO;
		}
	}
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}

static int
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intel_dp_i2c_init(struct intel_encoder *intel_encoder,
		  struct intel_connector *intel_connector, const char *name)
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{
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	struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
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Z
Zhenyu Wang 已提交
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	DRM_DEBUG_KMS("i2c_init %s\n", name);
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	dp_priv->algo.running = false;
	dp_priv->algo.address = 0;
	dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;

	memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
	dp_priv->adapter.owner = THIS_MODULE;
	dp_priv->adapter.class = I2C_CLASS_DDC;
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	strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
	dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
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	dp_priv->adapter.algo_data = &dp_priv->algo;
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	dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
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	return i2c_dp_aux_add_bus(&dp_priv->adapter);
}

static bool
intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
		    struct drm_display_mode *adjusted_mode)
{
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	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
	struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
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	int lane_count, clock;
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	int max_lane_count = intel_dp_max_lane_count(intel_encoder);
	int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
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	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		for (clock = 0; clock <= max_clock; clock++) {
			int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;

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			if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
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					<= link_avail) {
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				dp_priv->link_bw = bws[clock];
				dp_priv->lane_count = lane_count;
				adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
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				DRM_DEBUG_KMS("Display port link bw %02x lane "
						"count %d clock %d\n",
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				       dp_priv->link_bw, dp_priv->lane_count,
				       adjusted_mode->clock);
				return true;
			}
		}
	}
	return false;
}

struct intel_dp_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

static void
intel_reduce_ratio(uint32_t *num, uint32_t *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
intel_dp_compute_m_n(int bytes_per_pixel,
		     int nlanes,
		     int pixel_clock,
		     int link_clock,
		     struct intel_dp_m_n *m_n)
{
	m_n->tu = 64;
	m_n->gmch_m = pixel_clock * bytes_per_pixel;
	m_n->gmch_n = link_clock * nlanes;
	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
}

void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
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	struct drm_encoder *encoder;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int lane_count = 4;
	struct intel_dp_m_n m_n;

	/*
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	 * Find the lane count in the intel_encoder private
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	 */
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	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		struct intel_encoder *intel_encoder;
		struct intel_dp_priv *dp_priv;
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		if (!encoder || encoder->crtc != crtc)
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			continue;

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		intel_encoder = enc_to_intel_encoder(encoder);
		dp_priv = intel_encoder->dev_priv;

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		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
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			lane_count = dp_priv->lane_count;
			break;
		}
	}

	/*
	 * Compute the GMCH and Link ratios. The '3' here is
	 * the number of bytes_per_pixel post-LUT, which we always
	 * set up for 8-bits of R/G/B, or 3 bytes total.
	 */
	intel_dp_compute_m_n(3, lane_count,
			     mode->clock, adjusted_mode->clock, &m_n);

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	if (HAS_PCH_SPLIT(dev)) {
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		if (intel_crtc->pipe == 0) {
			I915_WRITE(TRANSA_DATA_M1,
				   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
				   m_n.gmch_m);
			I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
			I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
			I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
		} else {
			I915_WRITE(TRANSB_DATA_M1,
				   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
				   m_n.gmch_m);
			I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
			I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
			I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
		}
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	} else {
616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632
		if (intel_crtc->pipe == 0) {
			I915_WRITE(PIPEA_GMCH_DATA_M,
				   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
				   m_n.gmch_m);
			I915_WRITE(PIPEA_GMCH_DATA_N,
				   m_n.gmch_n);
			I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
			I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
		} else {
			I915_WRITE(PIPEB_GMCH_DATA_M,
				   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
				   m_n.gmch_m);
			I915_WRITE(PIPEB_GMCH_DATA_N,
					m_n.gmch_n);
			I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
			I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
		}
633 634 635 636 637 638 639
	}
}

static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
640
	struct drm_device *dev = encoder->dev;
641 642 643
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
	struct drm_crtc *crtc = intel_encoder->enc.crtc;
644 645
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

646
	dp_priv->DP = (DP_VOLTAGE_0_4 |
647 648 649 650 651 652
		       DP_PRE_EMPHASIS_0);

	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dp_priv->DP |= DP_SYNC_HS_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dp_priv->DP |= DP_SYNC_VS_HIGH;
653

654 655 656 657
	if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
		dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
	else
		dp_priv->DP |= DP_LINK_TRAIN_OFF;
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	switch (dp_priv->lane_count) {
	case 1:
		dp_priv->DP |= DP_PORT_WIDTH_1;
		break;
	case 2:
		dp_priv->DP |= DP_PORT_WIDTH_2;
		break;
	case 4:
		dp_priv->DP |= DP_PORT_WIDTH_4;
		break;
	}
	if (dp_priv->has_audio)
		dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;

	memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	dp_priv->link_configuration[0] = dp_priv->link_bw;
	dp_priv->link_configuration[1] = dp_priv->lane_count;

	/*
	 * Check for DPCD version > 1.1,
	 * enable enahanced frame stuff in that case
	 */
	if (dp_priv->dpcd[0] >= 0x11) {
		dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
		dp_priv->DP |= DP_ENHANCED_FRAMING;
	}

686 687
	/* CPT DP's pipe select is decided in TRANS_DP_CTL */
	if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
688
		dp_priv->DP |= DP_PIPEB_SELECT;
689

690
	if (IS_eDP(intel_encoder)) {
691 692 693 694 695 696 697
		/* don't miss out required setting for eDP */
		dp_priv->DP |= DP_PLL_ENABLE;
		if (adjusted_mode->clock < 200000)
			dp_priv->DP |= DP_PLL_FREQ_160MHZ;
		else
			dp_priv->DP |= DP_PLL_FREQ_270MHZ;
	}
698 699
}

700
static void ironlake_edp_backlight_on (struct drm_device *dev)
701 702 703 704
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

705
	DRM_DEBUG_KMS("\n");
706 707 708 709 710
	pp = I915_READ(PCH_PP_CONTROL);
	pp |= EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
}

711
static void ironlake_edp_backlight_off (struct drm_device *dev)
712 713 714 715
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

716
	DRM_DEBUG_KMS("\n");
717 718 719 720
	pp = I915_READ(PCH_PP_CONTROL);
	pp &= ~EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
}
721 722 723 724

static void
intel_dp_dpms(struct drm_encoder *encoder, int mode)
{
725 726
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
727
	struct drm_device *dev = encoder->dev;
728 729 730 731
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(dp_priv->output_reg);

	if (mode != DRM_MODE_DPMS_ON) {
732
		if (dp_reg & DP_PORT_EN) {
733 734
			intel_dp_link_down(intel_encoder, dp_priv->DP);
			if (IS_eDP(intel_encoder))
735
				ironlake_edp_backlight_off(dev);
736
		}
737
	} else {
738
		if (!(dp_reg & DP_PORT_EN)) {
739 740
			intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
			if (IS_eDP(intel_encoder))
741
				ironlake_edp_backlight_on(dev);
742
		}
743
	}
744
	dp_priv->dpms_mode = mode;
745 746 747 748 749 750 751
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
752
intel_dp_get_link_status(struct intel_encoder *intel_encoder,
753 754 755 756
			 uint8_t link_status[DP_LINK_STATUS_SIZE])
{
	int ret;

757
	ret = intel_dp_aux_native_read(intel_encoder,
758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
				       DP_LANE0_1_STATUS,
				       link_status, DP_LINK_STATUS_SIZE);
	if (ret != DP_LINK_STATUS_SIZE)
		return false;
	return true;
}

static uint8_t
intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		     int r)
{
	return link_status[r - DP_LANE0_1_STATUS];
}

static uint8_t
intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
				 int lane)
{
	int	    i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	int	    s = ((lane & 1) ?
			 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
			 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
	uint8_t l = intel_dp_link_status(link_status, i);

	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
}

static uint8_t
intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
				      int lane)
{
	int	    i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	int	    s = ((lane & 1) ?
			 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
			 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
	uint8_t l = intel_dp_link_status(link_status, i);

	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
}


#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */
#define I830_DP_VOLTAGE_MAX	    DP_TRAIN_VOLTAGE_SWING_800

static uint8_t
intel_dp_pre_emphasis_max(uint8_t voltage_swing)
{
	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
	case DP_TRAIN_VOLTAGE_SWING_400:
		return DP_TRAIN_PRE_EMPHASIS_6;
	case DP_TRAIN_VOLTAGE_SWING_600:
		return DP_TRAIN_PRE_EMPHASIS_6;
	case DP_TRAIN_VOLTAGE_SWING_800:
		return DP_TRAIN_PRE_EMPHASIS_3_5;
	case DP_TRAIN_VOLTAGE_SWING_1200:
	default:
		return DP_TRAIN_PRE_EMPHASIS_0;
	}
}

static void
834
intel_get_adjust_train(struct intel_encoder *intel_encoder,
835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900
		       uint8_t link_status[DP_LINK_STATUS_SIZE],
		       int lane_count,
		       uint8_t train_set[4])
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;

	for (lane = 0; lane < lane_count; lane++) {
		uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

	if (v >= I830_DP_VOLTAGE_MAX)
		v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;

	if (p >= intel_dp_pre_emphasis_max(v))
		p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

	for (lane = 0; lane < 4; lane++)
		train_set[lane] = v | p;
}

static uint32_t
intel_dp_signal_levels(uint8_t train_set, int lane_count)
{
	uint32_t	signal_levels = 0;

	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
	switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
		return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
	}
}

920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969
static uint8_t
intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		      int lane)
{
	int i = DP_LANE0_1_STATUS + (lane >> 1);
	int s = (lane & 1) * 4;
	uint8_t l = intel_dp_link_status(link_status, i);

	return (l >> s) & 0xf;
}

/* Check for clock recovery is done on all channels */
static bool
intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
{
	int lane;
	uint8_t lane_status;

	for (lane = 0; lane < lane_count; lane++) {
		lane_status = intel_get_lane_status(link_status, lane);
		if ((lane_status & DP_LANE_CR_DONE) == 0)
			return false;
	}
	return true;
}

/* Check to see if channel eq is done on all channels */
#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
			 DP_LANE_CHANNEL_EQ_DONE|\
			 DP_LANE_SYMBOL_LOCKED)
static bool
intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
{
	uint8_t lane_align;
	uint8_t lane_status;
	int lane;

	lane_align = intel_dp_link_status(link_status,
					  DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		return false;
	for (lane = 0; lane < lane_count; lane++) {
		lane_status = intel_get_lane_status(link_status, lane);
		if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
			return false;
	}
	return true;
}

static bool
970
intel_dp_set_link_train(struct intel_encoder *intel_encoder,
971 972 973 974 975
			uint32_t dp_reg_value,
			uint8_t dp_train_pat,
			uint8_t train_set[4],
			bool first)
{
976
	struct drm_device *dev = intel_encoder->enc.dev;
977
	struct drm_i915_private *dev_priv = dev->dev_private;
978
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
979 980 981 982 983 984 985
	int ret;

	I915_WRITE(dp_priv->output_reg, dp_reg_value);
	POSTING_READ(dp_priv->output_reg);
	if (first)
		intel_wait_for_vblank(dev);

986
	intel_dp_aux_native_write_1(intel_encoder,
987 988 989
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

990
	ret = intel_dp_aux_native_write(intel_encoder,
991 992 993 994 995 996 997 998
					DP_TRAINING_LANE0_SET, train_set, 4);
	if (ret != 4)
		return false;

	return true;
}

static void
999
intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1000 1001
		    uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
{
1002
	struct drm_device *dev = intel_encoder->enc.dev;
1003
	struct drm_i915_private *dev_priv = dev->dev_private;
1004
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1005 1006 1007 1008 1009 1010 1011 1012
	uint8_t	train_set[4];
	uint8_t link_status[DP_LINK_STATUS_SIZE];
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
	bool channel_eq = false;
	bool first = true;
	int tries;
1013
	u32 reg;
1014 1015

	/* Write the link configuration data */
1016
	intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
1017 1018 1019
				  link_configuration, DP_LINK_CONFIGURATION_SIZE);

	DP |= DP_PORT_EN;
1020 1021 1022 1023
	if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
	else
		DP &= ~DP_LINK_TRAIN_MASK;
1024 1025 1026 1027 1028 1029
	memset(train_set, 0, 4);
	voltage = 0xff;
	tries = 0;
	clock_recovery = false;
	for (;;) {
		/* Use train_set[0] to set the voltage and pre emphasis values */
1030 1031 1032 1033 1034 1035 1036 1037
		uint32_t    signal_levels;
		if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
			signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
			signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}
1038

1039 1040 1041 1042 1043 1044
		if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
			reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
		else
			reg = DP | DP_LINK_TRAIN_PAT_1;

		if (!intel_dp_set_link_train(intel_encoder, reg,
1045 1046 1047 1048 1049 1050
					     DP_TRAINING_PATTERN_1, train_set, first))
			break;
		first = false;
		/* Set training pattern 1 */

		udelay(100);
1051
		if (!intel_dp_get_link_status(intel_encoder, link_status))
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
			break;

		if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < dp_priv->lane_count; i++)
			if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
				break;
		if (i == dp_priv->lane_count)
			break;

		/* Check to see if we've tried the same voltage 5 times */
		if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
			++tries;
			if (tries == 5)
				break;
		} else
			tries = 0;
		voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

		/* Compute new train_set as requested by target */
1076
		intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1077 1078 1079 1080 1081 1082 1083
	}

	/* channel equalization */
	tries = 0;
	channel_eq = false;
	for (;;) {
		/* Use train_set[0] to set the voltage and pre emphasis values */
1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
		uint32_t    signal_levels;

		if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
			signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
			signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}

		if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
			reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
		else
			reg = DP | DP_LINK_TRAIN_PAT_2;
1098 1099

		/* channel eq pattern */
1100
		if (!intel_dp_set_link_train(intel_encoder, reg,
1101 1102 1103 1104 1105
					     DP_TRAINING_PATTERN_2, train_set,
					     false))
			break;

		udelay(400);
1106
		if (!intel_dp_get_link_status(intel_encoder, link_status))
1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
			break;

		if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
			channel_eq = true;
			break;
		}

		/* Try 5 times */
		if (tries > 5)
			break;

		/* Compute new train_set as requested by target */
1119
		intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1120 1121 1122
		++tries;
	}

1123 1124 1125 1126 1127 1128
	if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
		reg = DP | DP_LINK_TRAIN_OFF_CPT;
	else
		reg = DP | DP_LINK_TRAIN_OFF;

	I915_WRITE(dp_priv->output_reg, reg);
1129
	POSTING_READ(dp_priv->output_reg);
1130
	intel_dp_aux_native_write_1(intel_encoder,
1131 1132 1133 1134
				    DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
}

static void
1135
intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1136
{
1137
	struct drm_device *dev = intel_encoder->enc.dev;
1138
	struct drm_i915_private *dev_priv = dev->dev_private;
1139
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1140

1141
	DRM_DEBUG_KMS("\n");
1142

1143
	if (IS_eDP(intel_encoder)) {
1144 1145 1146 1147 1148 1149
		DP &= ~DP_PLL_ENABLE;
		I915_WRITE(dp_priv->output_reg, DP);
		POSTING_READ(dp_priv->output_reg);
		udelay(100);
	}

1150 1151 1152 1153 1154 1155 1156 1157 1158
	if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
		I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
		POSTING_READ(dp_priv->output_reg);
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
		I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
		POSTING_READ(dp_priv->output_reg);
	}
1159 1160 1161

	udelay(17000);

1162
	if (IS_eDP(intel_encoder))
1163
		DP |= DP_LINK_TRAIN_OFF;
1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177
	I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(dp_priv->output_reg);
}

/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

static void
1178
intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1179
{
1180
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1181 1182
	uint8_t link_status[DP_LINK_STATUS_SIZE];

1183
	if (!intel_encoder->enc.crtc)
1184 1185
		return;

1186 1187
	if (!intel_dp_get_link_status(intel_encoder, link_status)) {
		intel_dp_link_down(intel_encoder, dp_priv->DP);
1188 1189 1190 1191
		return;
	}

	if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1192
		intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1193 1194
}

1195
static enum drm_connector_status
1196
ironlake_dp_detect(struct drm_connector *connector)
1197
{
1198 1199
	struct drm_encoder *encoder = intel_attached_encoder(connector);
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1200
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1201 1202 1203
	enum drm_connector_status status;

	status = connector_status_disconnected;
1204
	if (intel_dp_aux_native_read(intel_encoder,
1205 1206 1207 1208 1209 1210 1211 1212 1213
				     0x000, dp_priv->dpcd,
				     sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
	{
		if (dp_priv->dpcd[0] != 0)
			status = connector_status_connected;
	}
	return status;
}

1214 1215 1216 1217 1218 1219 1220 1221 1222
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
 *
 * \return true if DP port is connected.
 * \return false if DP port is disconnected.
 */
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector)
{
1223 1224 1225
	struct drm_encoder *encoder = intel_attached_encoder(connector);
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
	struct drm_device *dev = intel_encoder->enc.dev;
1226
	struct drm_i915_private *dev_priv = dev->dev_private;
1227
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1228 1229 1230 1231 1232
	uint32_t temp, bit;
	enum drm_connector_status status;

	dp_priv->has_audio = false;

1233
	if (HAS_PCH_SPLIT(dev))
1234
		return ironlake_dp_detect(connector);
1235

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
	switch (dp_priv->output_reg) {
	case DP_B:
		bit = DPB_HOTPLUG_INT_STATUS;
		break;
	case DP_C:
		bit = DPC_HOTPLUG_INT_STATUS;
		break;
	case DP_D:
		bit = DPD_HOTPLUG_INT_STATUS;
		break;
	default:
		return connector_status_unknown;
	}

	temp = I915_READ(PORT_HOTPLUG_STAT);

	if ((temp & bit) == 0)
		return connector_status_disconnected;

	status = connector_status_disconnected;
1256
	if (intel_dp_aux_native_read(intel_encoder,
1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267
				     0x000, dp_priv->dpcd,
				     sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
	{
		if (dp_priv->dpcd[0] != 0)
			status = connector_status_connected;
	}
	return status;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
1268 1269 1270
	struct drm_encoder *encoder = intel_attached_encoder(connector);
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
	struct drm_device *dev = intel_encoder->enc.dev;
1271 1272
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
1273 1274 1275 1276

	/* We should parse the EDID data and find out if it has an audio sink
	 */

1277
	ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1278 1279 1280 1281
	if (ret)
		return ret;

	/* if eDP has no EDID, try to use fixed panel mode from VBT */
1282
	if (IS_eDP(intel_encoder)) {
1283 1284 1285 1286 1287 1288 1289 1290
		if (dev_priv->panel_fixed_mode != NULL) {
			struct drm_display_mode *mode;
			mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
1291 1292 1293 1294 1295 1296 1297
}

static void
intel_dp_destroy (struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
1298
	kfree(connector);
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
}

static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.dpms = intel_dp_dpms,
	.mode_fixup = intel_dp_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_dp_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
1319
	.best_encoder = intel_attached_encoder,
1320 1321 1322 1323
};

static void intel_dp_enc_destroy(struct drm_encoder *encoder)
{
1324 1325 1326 1327
	struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);

	if (intel_encoder->i2c_bus)
		intel_i2c_destroy(intel_encoder->i2c_bus);
1328
	drm_encoder_cleanup(encoder);
1329
	kfree(intel_encoder);
1330 1331 1332 1333 1334 1335
}

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
	.destroy = intel_dp_enc_destroy,
};

1336
void
1337
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1338
{
1339
	struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1340 1341

	if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1342
		intel_dp_check_link_status(intel_encoder);
1343
}
1344

1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366
/* Return which DP Port should be selected for Transcoder DP control */
int
intel_trans_dp_port_sel (struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_encoder *encoder;
	struct intel_encoder *intel_encoder = NULL;

	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
		if (!encoder || encoder->crtc != crtc)
			continue;

		intel_encoder = enc_to_intel_encoder(encoder);
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
			struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
			return dp_priv->output_reg;
		}
	}
	return -1;
}

1367 1368 1369 1370 1371
void
intel_dp_init(struct drm_device *dev, int output_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
1372
	struct intel_encoder *intel_encoder;
1373
	struct intel_connector *intel_connector;
1374
	struct intel_dp_priv *dp_priv;
1375
	const char *name = NULL;
1376

1377
	intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1378
			       sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1379
	if (!intel_encoder)
1380 1381
		return;

1382 1383 1384 1385 1386 1387
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_encoder);
		return;
	}

1388
	dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1389

1390
	connector = &intel_connector->base;
1391 1392 1393 1394
	drm_connector_init(dev, connector, &intel_dp_connector_funcs,
			   DRM_MODE_CONNECTOR_DisplayPort);
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

1395
	if (output_reg == DP_A)
1396
		intel_encoder->type = INTEL_OUTPUT_EDP;
1397
	else
1398
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1399

1400
	if (output_reg == DP_B || output_reg == PCH_DP_B)
1401
		intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1402
	else if (output_reg == DP_C || output_reg == PCH_DP_C)
1403
		intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1404
	else if (output_reg == DP_D || output_reg == PCH_DP_D)
1405
		intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1406

1407 1408
	if (IS_eDP(intel_encoder))
		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
Z
Zhenyu Wang 已提交
1409

1410
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1411 1412 1413
	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

1414
	dp_priv->intel_encoder = intel_encoder;
1415 1416
	dp_priv->output_reg = output_reg;
	dp_priv->has_audio = false;
1417
	dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1418
	intel_encoder->dev_priv = dp_priv;
1419

1420
	drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1421
			 DRM_MODE_ENCODER_TMDS);
1422
	drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1423

1424
	drm_mode_connector_attach_encoder(&intel_connector->base,
1425
					  &intel_encoder->enc);
1426 1427 1428
	drm_sysfs_connector_add(connector);

	/* Set up the DDC bus. */
1429
	switch (output_reg) {
1430 1431 1432
		case DP_A:
			name = "DPDDC-A";
			break;
1433 1434
		case DP_B:
		case PCH_DP_B:
1435 1436
			dev_priv->hotplug_supported_mask |=
				HDMIB_HOTPLUG_INT_STATUS;
1437 1438 1439 1440
			name = "DPDDC-B";
			break;
		case DP_C:
		case PCH_DP_C:
1441 1442
			dev_priv->hotplug_supported_mask |=
				HDMIC_HOTPLUG_INT_STATUS;
1443 1444 1445 1446
			name = "DPDDC-C";
			break;
		case DP_D:
		case PCH_DP_D:
1447 1448
			dev_priv->hotplug_supported_mask |=
				HDMID_HOTPLUG_INT_STATUS;
1449 1450 1451 1452
			name = "DPDDC-D";
			break;
	}

1453
	intel_dp_i2c_init(intel_encoder, intel_connector, name);
1454

1455 1456
	intel_encoder->ddc_bus = &dp_priv->adapter;
	intel_encoder->hot_plug = intel_dp_hot_plug;
1457

1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
	if (output_reg == DP_A) {
		/* initialize panel mode from VBT if available for eDP */
		if (dev_priv->lfp_lvds_vbt_mode) {
			dev_priv->panel_fixed_mode =
				drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
			if (dev_priv->panel_fixed_mode) {
				dev_priv->panel_fixed_mode->type |=
					DRM_MODE_TYPE_PREFERRED;
			}
		}
	}

1470 1471 1472 1473 1474 1475 1476 1477 1478
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}