intel_dp.c 70.3 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
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#include "drm_edid.h"
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#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

#define DP_LINK_STATUS_SIZE	6
#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
	return intel_dp->base.type == INTEL_OUTPUT_EDP;
}

/**
 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a PCH DP port attached
 * to an eDP panel, false otherwise.  Helpful for determining whether we
 * may need FDI resources for a given DP output or not.
 */
static bool is_pch_edp(struct intel_dp *intel_dp)
{
	return intel_dp->is_pch_edp;
}

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/**
 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a CPU eDP port.
 */
static bool is_cpu_edp(struct intel_dp *intel_dp)
{
	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
}

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static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
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	return container_of(encoder, struct intel_dp, base.base);
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}
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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_dp, base);
}

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/**
 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 * @encoder: DRM encoder
 *
 * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 * by intel_display.c.
 */
bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp;

	if (!encoder)
		return false;

	intel_dp = enc_to_intel_dp(encoder);

	return is_pch_edp(intel_dp);
}

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static void intel_dp_start_link_train(struct intel_dp *intel_dp);
static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
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static void intel_dp_link_down(struct intel_dp *intel_dp);
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void
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intel_edp_link_config(struct intel_encoder *intel_encoder,
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		       int *lane_num, int *link_bw)
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{
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	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
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	*lane_num = intel_dp->lane_count;
	if (intel_dp->link_bw == DP_LINK_BW_1_62)
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		*link_bw = 162000;
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	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
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		*link_bw = 270000;
}

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int
intel_edp_target_clock(struct intel_encoder *intel_encoder,
		       struct drm_display_mode *mode)
{
	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);

	if (intel_dp->panel_fixed_mode)
		return intel_dp->panel_fixed_mode->clock;
	else
		return mode->clock;
}

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static int
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intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
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	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
	switch (max_lane_count) {
	case 1: case 2: case 4:
		break;
	default:
		max_lane_count = 4;
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	}
	return max_lane_count;
}

static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

static int
intel_dp_link_clock(uint8_t link_bw)
{
	if (link_bw == DP_LINK_BW_2_7)
		return 270000;
	else
		return 162000;
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static bool
intel_dp_adjust_dithering(struct intel_dp *intel_dp,
			  struct drm_display_mode *mode,
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			  bool adjust_mode)
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{
	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
	int max_lanes = intel_dp_max_lane_count(intel_dp);
	int max_rate, mode_rate;

	mode_rate = intel_dp_link_required(mode->clock, 24);
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);

	if (mode_rate > max_rate) {
		mode_rate = intel_dp_link_required(mode->clock, 18);
		if (mode_rate > max_rate)
			return false;

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		if (adjust_mode)
			mode->private_flags
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				|= INTEL_MODE_DP_FORCE_6BPC;

		return true;
	}

	return true;
}

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static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
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			return MODE_PANEL;
	}

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	if (!intel_dp_adjust_dithering(intel_dp, mode, false))
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(PCH_PP_STATUS),
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			      I915_READ(PCH_PP_CONTROL));
	}
}

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static int
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intel_dp_aux_ch(struct intel_dp *intel_dp,
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		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
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	uint32_t output_reg = intel_dp->output_reg;
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	struct drm_device *dev = intel_dp->base.base.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = output_reg + 0x10;
	uint32_t ch_data = ch_ctl + 4;
	int i;
	int recv_bytes;
	uint32_t status;
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	uint32_t aux_clock_divider;
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	int try, precharge;
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	intel_dp_check_edp(intel_dp);
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
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	 */
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	if (is_cpu_edp(intel_dp)) {
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		if (IS_GEN6(dev) || IS_GEN7(dev))
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
	} else if (HAS_PCH_SPLIT(dev))
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		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
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	else
		aux_clock_divider = intel_hrawclk(dev) / 2;

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	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
		status = I915_READ(ch_ctl);
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		return -EBUSY;
	}

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	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
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		for (i = 0; i < send_bytes; i += 4)
			I915_WRITE(ch_data + i,
				   pack_aux(send + i, send_bytes - i));
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		/* Send the command and wait for it to complete */
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		I915_WRITE(ch_ctl,
			   DP_AUX_CH_CTL_SEND_BUSY |
			   DP_AUX_CH_CTL_TIME_OUT_400us |
			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		for (;;) {
			status = I915_READ(ch_ctl);
			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
				break;
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			udelay(100);
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		}
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		/* Clear done status and any errors */
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		I915_WRITE(ch_ctl,
			   status |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
			continue;
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		return -EBUSY;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		return -EIO;
	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		return -ETIMEDOUT;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	return recv_bytes;
}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_dp *intel_dp,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

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	intel_dp_check_edp(intel_dp);
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	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
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				      reply, reply_bytes);
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		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
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			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
}

static int
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intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
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{
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	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
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	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
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	unsigned retry;
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	int msg_bytes;
	int reply_bytes;
	int ret;

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	intel_dp_check_edp(intel_dp);
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	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
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	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

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	for (retry = 0; retry < 5; retry++) {
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
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		if (ret < 0) {
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			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
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			return ret;
		}
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		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
			udelay(100);
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

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		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
629
			DRM_DEBUG_KMS("aux_i2c nack\n");
630 631
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
632
			DRM_DEBUG_KMS("aux_i2c defer\n");
633 634 635
			udelay(100);
			break;
		default:
636
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
637 638 639
			return -EREMOTEIO;
		}
	}
640 641 642

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
643 644
}

645
static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
646
static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
647

648
static int
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Chris Wilson 已提交
649
intel_dp_i2c_init(struct intel_dp *intel_dp,
650
		  struct intel_connector *intel_connector, const char *name)
651
{
652 653
	int	ret;

Z
Zhenyu Wang 已提交
654
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
655 656 657 658
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

659
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
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Chris Wilson 已提交
660 661
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
662
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
663 664 665 666
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

667 668
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
669
	ironlake_edp_panel_vdd_off(intel_dp, false);
670
	return ret;
671 672 673
}

static bool
674 675
intel_dp_mode_fixup(struct drm_encoder *encoder,
		    const struct drm_display_mode *mode,
676 677
		    struct drm_display_mode *adjusted_mode)
{
678
	struct drm_device *dev = encoder->dev;
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Chris Wilson 已提交
679
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
680
	int lane_count, clock;
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Chris Wilson 已提交
681 682
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
683
	int bpp, mode_rate;
684 685
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

686 687
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
688 689
		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
					mode, adjusted_mode);
690 691
	}

692
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
693 694
		return false;

695 696
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
697
		      max_lane_count, bws[max_clock], adjusted_mode->clock);
698

699
	if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
700 701 702
		return false;

	bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
703
	mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
704

705 706
	for (clock = 0; clock <= max_clock; clock++) {
		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
707
			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
708

709
			if (mode_rate <= link_avail) {
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710 711 712
				intel_dp->link_bw = bws[clock];
				intel_dp->lane_count = lane_count;
				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
713 714
				DRM_DEBUG_KMS("DP link bw %02x lane "
						"count %d clock %d bpp %d\n",
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715
				       intel_dp->link_bw, intel_dp->lane_count,
716 717 718
				       adjusted_mode->clock, bpp);
				DRM_DEBUG_KMS("DP link bw required %i available %i\n",
					      mode_rate, link_avail);
719 720 721 722
				return true;
			}
		}
	}
723

724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
	return false;
}

struct intel_dp_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

static void
intel_reduce_ratio(uint32_t *num, uint32_t *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
745
intel_dp_compute_m_n(int bpp,
746 747 748 749 750 751
		     int nlanes,
		     int pixel_clock,
		     int link_clock,
		     struct intel_dp_m_n *m_n)
{
	m_n->tu = 64;
752
	m_n->gmch_m = (pixel_clock * bpp) >> 3;
753 754 755 756 757 758 759 760 761 762 763 764
	m_n->gmch_n = link_clock * nlanes;
	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
}

void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
765
	struct intel_encoder *encoder;
766 767
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
768
	int lane_count = 4;
769
	struct intel_dp_m_n m_n;
770
	int pipe = intel_crtc->pipe;
771 772

	/*
773
	 * Find the lane count in the intel_encoder private
774
	 */
775 776
	for_each_encoder_on_crtc(dev, crtc, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
777

778 779 780
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
		{
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Chris Wilson 已提交
781
			lane_count = intel_dp->lane_count;
782
			break;
783 784 785 786 787 788 789 790
		}
	}

	/*
	 * Compute the GMCH and Link ratios. The '3' here is
	 * the number of bytes_per_pixel post-LUT, which we always
	 * set up for 8-bits of R/G/B, or 3 bytes total.
	 */
791
	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
792 793
			     mode->clock, adjusted_mode->clock, &m_n);

794
	if (HAS_PCH_SPLIT(dev)) {
795 796 797 798 799 800
		I915_WRITE(TRANSDATA_M1(pipe),
			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
			   m_n.gmch_m);
		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
801
	} else {
802 803 804 805 806 807
		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
			   m_n.gmch_m);
		I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
808 809 810
	}
}

811 812 813
static void ironlake_edp_pll_on(struct drm_encoder *encoder);
static void ironlake_edp_pll_off(struct drm_encoder *encoder);

814 815 816 817
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
818
	struct drm_device *dev = encoder->dev;
819
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
820
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
821
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
822 823
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

824 825 826 827 828 829 830 831
	/* Turn on the eDP PLL if needed */
	if (is_edp(intel_dp)) {
		if (!is_pch_edp(intel_dp))
			ironlake_edp_pll_on(encoder);
		else
			ironlake_edp_pll_off(encoder);
	}

832
	/*
K
Keith Packard 已提交
833
	 * There are four kinds of DP registers:
834 835
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
836 837
	 * 	SNB CPU
	 *	IVB CPU
838 839 840 841 842 843 844 845 846 847
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
848

849 850 851 852 853
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
854

855 856 857
	/* Handle DP bits in common between all three register formats */

	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
858

C
Chris Wilson 已提交
859
	switch (intel_dp->lane_count) {
860
	case 1:
C
Chris Wilson 已提交
861
		intel_dp->DP |= DP_PORT_WIDTH_1;
862 863
		break;
	case 2:
C
Chris Wilson 已提交
864
		intel_dp->DP |= DP_PORT_WIDTH_2;
865 866
		break;
	case 4:
C
Chris Wilson 已提交
867
		intel_dp->DP |= DP_PORT_WIDTH_4;
868 869
		break;
	}
870 871 872
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
C
Chris Wilson 已提交
873
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
874 875
		intel_write_eld(encoder, adjusted_mode);
	}
C
Chris Wilson 已提交
876 877 878
	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	intel_dp->link_configuration[0] = intel_dp->link_bw;
	intel_dp->link_configuration[1] = intel_dp->lane_count;
879
	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
880
	/*
881
	 * Check for DPCD version > 1.1 and enhanced framing support
882
	 */
883 884
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
C
Chris Wilson 已提交
885
		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
886 887
	}

888
	/* Split out the IBX/CPU vs CPT settings */
889

K
Keith Packard 已提交
890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		intel_dp->DP |= intel_crtc->pipe << 29;

		/* don't miss out required setting for eDP */
		intel_dp->DP |= DP_PLL_ENABLE;
		if (adjusted_mode->clock < 200000)
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
		else
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932
		intel_dp->DP |= intel_dp->color_range;

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		if (intel_crtc->pipe == 1)
			intel_dp->DP |= DP_PIPEB_SELECT;

		if (is_cpu_edp(intel_dp)) {
			/* don't miss out required setting for eDP */
			intel_dp->DP |= DP_PLL_ENABLE;
			if (adjusted_mode->clock < 200000)
				intel_dp->DP |= DP_PLL_FREQ_160MHZ;
			else
				intel_dp->DP |= DP_PLL_FREQ_270MHZ;
		}
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
933
	}
934 935
}

936 937 938 939 940 941 942 943 944 945 946 947
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
948
{
949 950
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
951

952 953 954 955
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		      mask, value,
		      I915_READ(PCH_PP_STATUS),
		      I915_READ(PCH_PP_CONTROL));
956

957 958 959 960
	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
			  I915_READ(PCH_PP_STATUS),
			  I915_READ(PCH_PP_CONTROL));
961
	}
962
}
963

964 965 966 967
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
968 969
}

970 971 972 973 974 975 976 977 978 979 980 981 982
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


983 984 985 986 987 988 989 990 991 992 993
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
{
	u32	control = I915_READ(PCH_PP_CONTROL);

	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
994 995
}

996 997 998 999 1000 1001
static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1002 1003
	if (!is_edp(intel_dp))
		return;
1004
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
1005

1006 1007 1008 1009
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1010

1011 1012 1013 1014 1015
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1016 1017 1018
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1019
	pp = ironlake_get_pp_control(dev_priv);
1020 1021 1022
	pp |= EDP_FORCE_VDD;
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1023 1024
	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1025 1026 1027 1028 1029

	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1030
		DRM_DEBUG_KMS("eDP was not running\n");
1031 1032
		msleep(intel_dp->panel_power_up_delay);
	}
1033 1034
}

1035
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1036 1037 1038 1039 1040
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1041
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042
		pp = ironlake_get_pp_control(dev_priv);
1043 1044 1045 1046 1047 1048 1049
		pp &= ~EDP_FORCE_VDD;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);

		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1050 1051

		msleep(intel_dp->panel_power_down_delay);
1052 1053
	}
}
1054

1055 1056 1057 1058 1059 1060
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
	struct drm_device *dev = intel_dp->base.base.dev;

1061
	mutex_lock(&dev->mode_config.mutex);
1062
	ironlake_panel_vdd_off_sync(intel_dp);
1063
	mutex_unlock(&dev->mode_config.mutex);
1064 1065 1066 1067
}

static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
1068 1069
	if (!is_edp(intel_dp))
		return;
1070

1071 1072
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1073

1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1087 1088
}

1089
static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1090
{
1091
	struct drm_device *dev = intel_dp->base.base.dev;
1092
	struct drm_i915_private *dev_priv = dev->dev_private;
1093
	u32 pp;
1094

1095
	if (!is_edp(intel_dp))
1096
		return;
1097 1098 1099 1100 1101

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1102
		return;
1103
	}
1104

1105
	ironlake_wait_panel_power_cycle(intel_dp);
1106

1107
	pp = ironlake_get_pp_control(dev_priv);
1108 1109 1110 1111 1112 1113
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1114

1115
	pp |= POWER_TARGET_ON;
1116 1117 1118
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1119
	I915_WRITE(PCH_PP_CONTROL, pp);
1120
	POSTING_READ(PCH_PP_CONTROL);
1121

1122
	ironlake_wait_panel_on(intel_dp);
1123

1124 1125 1126 1127 1128
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1129 1130
}

1131
static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1132
{
1133
	struct drm_device *dev = intel_dp->base.base.dev;
1134
	struct drm_i915_private *dev_priv = dev->dev_private;
1135
	u32 pp;
1136

1137 1138
	if (!is_edp(intel_dp))
		return;
1139

1140
	DRM_DEBUG_KMS("Turn eDP power off\n");
1141

1142
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1143

1144
	pp = ironlake_get_pp_control(dev_priv);
1145 1146 1147
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1148 1149
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1150

1151 1152
	intel_dp->want_panel_vdd = false;

1153
	ironlake_wait_panel_off(intel_dp);
1154 1155
}

1156
static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1157
{
1158
	struct drm_device *dev = intel_dp->base.base.dev;
1159 1160 1161
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1162 1163 1164
	if (!is_edp(intel_dp))
		return;

1165
	DRM_DEBUG_KMS("\n");
1166 1167 1168 1169 1170 1171
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1172
	msleep(intel_dp->backlight_on_delay);
1173
	pp = ironlake_get_pp_control(dev_priv);
1174 1175
	pp |= EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1176
	POSTING_READ(PCH_PP_CONTROL);
1177 1178
}

1179
static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1180
{
1181
	struct drm_device *dev = intel_dp->base.base.dev;
1182 1183 1184
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1185 1186 1187
	if (!is_edp(intel_dp))
		return;

1188
	DRM_DEBUG_KMS("\n");
1189
	pp = ironlake_get_pp_control(dev_priv);
1190 1191
	pp &= ~EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1192 1193
	POSTING_READ(PCH_PP_CONTROL);
	msleep(intel_dp->backlight_off_delay);
1194
}
1195

1196 1197 1198 1199 1200 1201 1202 1203
static void ironlake_edp_pll_on(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1204
	dpa_ctl |= DP_PLL_ENABLE;
1205
	I915_WRITE(DP_A, dpa_ctl);
1206 1207
	POSTING_READ(DP_A);
	udelay(200);
1208 1209 1210 1211 1212 1213 1214 1215 1216
}

static void ironlake_edp_pll_off(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	dpa_ctl = I915_READ(DP_A);
1217
	dpa_ctl &= ~DP_PLL_ENABLE;
1218
	I915_WRITE(DP_A, dpa_ctl);
1219
	POSTING_READ(DP_A);
1220 1221 1222
	udelay(200);
}

1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252
/* If the sink supports it, try to set the power state appropriately */
static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		*pipe = PORT_TO_PIPE_CPT(tmp);
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}
	}

	DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);

	return true;
}

1301
static void intel_disable_dp(struct intel_encoder *encoder)
1302
{
1303
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1304 1305 1306 1307

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
	ironlake_edp_panel_vdd_on(intel_dp);
1308
	ironlake_edp_backlight_off(intel_dp);
1309
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1310
	ironlake_edp_panel_off(intel_dp);
1311
	intel_dp_link_down(intel_dp);
1312 1313
}

1314
static void intel_enable_dp(struct intel_encoder *encoder)
1315
{
1316 1317 1318 1319
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1320

1321
	ironlake_edp_panel_vdd_on(intel_dp);
1322
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1323 1324 1325 1326 1327 1328 1329
	if (!(dp_reg & DP_PORT_EN)) {
		intel_dp_start_link_train(intel_dp);
		ironlake_edp_panel_on(intel_dp);
		ironlake_edp_panel_vdd_off(intel_dp, true);
		intel_dp_complete_link_train(intel_dp);
	} else
		ironlake_edp_panel_vdd_off(intel_dp, false);
1330
	ironlake_edp_backlight_on(intel_dp);
1331 1332
}

1333
static void
1334
intel_dp_dpms(struct drm_connector *connector, int mode)
1335
{
1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351
	struct intel_dp *intel_dp = intel_attached_dp(connector);

	/* DP supports only 2 dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;

	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	if (!intel_dp->base.base.crtc) {
		intel_dp->base.connectors_active = false;
		return;
	}
1352 1353

	if (mode != DRM_MODE_DPMS_ON) {
1354
		intel_encoder_dpms(&intel_dp->base, mode);
1355 1356

		if (is_cpu_edp(intel_dp))
1357
			ironlake_edp_pll_off(&intel_dp->base.base);
1358
	} else {
1359
		if (is_cpu_edp(intel_dp))
1360
			ironlake_edp_pll_on(&intel_dp->base.base);
1361

1362
		intel_encoder_dpms(&intel_dp->base, mode);
1363
	}
1364 1365

	intel_connector_check_state(to_intel_connector(connector));
1366 1367 1368
}

/*
1369 1370
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1371 1372
 */
static bool
1373 1374
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1375
{
1376 1377
	int ret, i;

1378 1379 1380 1381
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1382
	for (i = 0; i < 3; i++) {
1383 1384 1385
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1386 1387 1388
			return true;
		msleep(1);
	}
1389

1390
	return false;
1391 1392 1393 1394 1395 1396 1397
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1398
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1399
{
1400 1401
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1402
					      link_status,
1403
					      DP_LINK_STATUS_SIZE);
1404 1405 1406 1407 1408 1409 1410 1411 1412 1413
}

static uint8_t
intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		     int r)
{
	return link_status[r - DP_LANE0_1_STATUS];
}

static uint8_t
1414
intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1415 1416 1417 1418 1419
				 int lane)
{
	int	    s = ((lane & 1) ?
			 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
			 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1420
	uint8_t l = adjust_request[lane>>1];
1421 1422 1423 1424 1425

	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
}

static uint8_t
1426
intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1427 1428 1429 1430 1431
				      int lane)
{
	int	    s = ((lane & 1) ?
			 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
			 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1432
	uint8_t l = adjust_request[lane>>1];
1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455

	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
}


#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
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1456
intel_dp_voltage_max(struct intel_dp *intel_dp)
1457
{
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1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
	struct drm_device *dev = intel_dp->base.base.dev;

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_800;
	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
	struct drm_device *dev = intel_dp->base.base.dev;

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1495 1496 1497 1498
	}
}

static void
1499
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1500 1501 1502 1503
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
1504
	uint8_t	*adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
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Keith Packard 已提交
1505 1506
	uint8_t voltage_max;
	uint8_t preemph_max;
1507

1508
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1509 1510
		uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
		uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1511 1512 1513 1514 1515 1516 1517

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

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1518
	voltage_max = intel_dp_voltage_max(intel_dp);
1519 1520
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1521

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1522 1523 1524
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1525 1526

	for (lane = 0; lane < 4; lane++)
1527
		intel_dp->train_set[lane] = v | p;
1528 1529 1530
}

static uint32_t
1531
intel_dp_signal_levels(uint8_t train_set)
1532
{
1533
	uint32_t	signal_levels = 0;
1534

1535
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
1550
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

1568 1569 1570 1571
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
1572 1573 1574
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
1575
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1576 1577 1578 1579
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1580
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1581 1582
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1583
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584 1585
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1586
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1587 1588
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1589
	default:
1590 1591 1592
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593 1594 1595
	}
}

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1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

1627 1628 1629 1630 1631
static uint8_t
intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		      int lane)
{
	int s = (lane & 1) * 4;
1632
	uint8_t l = link_status[lane>>1];
1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656

	return (l >> s) & 0xf;
}

/* Check for clock recovery is done on all channels */
static bool
intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
{
	int lane;
	uint8_t lane_status;

	for (lane = 0; lane < lane_count; lane++) {
		lane_status = intel_get_lane_status(link_status, lane);
		if ((lane_status & DP_LANE_CR_DONE) == 0)
			return false;
	}
	return true;
}

/* Check to see if channel eq is done on all channels */
#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
			 DP_LANE_CHANNEL_EQ_DONE|\
			 DP_LANE_SYMBOL_LOCKED)
static bool
1657
intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1658 1659 1660 1661 1662
{
	uint8_t lane_align;
	uint8_t lane_status;
	int lane;

1663
	lane_align = intel_dp_link_status(link_status,
1664 1665 1666
					  DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		return false;
1667
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1668
		lane_status = intel_get_lane_status(link_status, lane);
1669 1670 1671 1672 1673 1674 1675
		if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
			return false;
	}
	return true;
}

static bool
C
Chris Wilson 已提交
1676
intel_dp_set_link_train(struct intel_dp *intel_dp,
1677
			uint32_t dp_reg_value,
1678
			uint8_t dp_train_pat)
1679
{
1680
	struct drm_device *dev = intel_dp->base.base.dev;
1681 1682 1683
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
		dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		dp_reg_value &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		}
	}

C
Chris Wilson 已提交
1723 1724
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
	POSTING_READ(intel_dp->output_reg);
1725

C
Chris Wilson 已提交
1726
	intel_dp_aux_native_write_1(intel_dp,
1727 1728 1729
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

1730 1731 1732 1733 1734 1735 1736 1737 1738
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
	    DP_TRAINING_PATTERN_DISABLE) {
		ret = intel_dp_aux_native_write(intel_dp,
						DP_TRAINING_LANE0_SET,
						intel_dp->train_set,
						intel_dp->lane_count);
		if (ret != intel_dp->lane_count)
			return false;
	}
1739 1740 1741 1742

	return true;
}

1743
/* Enable corresponding port and start training pattern 1 */
1744
static void
1745
intel_dp_start_link_train(struct intel_dp *intel_dp)
1746
{
1747
	struct drm_device *dev = intel_dp->base.base.dev;
1748
	struct drm_i915_private *dev_priv = dev->dev_private;
1749
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1750 1751 1752
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
1753
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
1754
	uint32_t DP = intel_dp->DP;
1755

1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
	/*
	 * On CPT we have to enable the port in training pattern 1, which
	 * will happen below in intel_dp_set_link_train.  Otherwise, enable
	 * the port and wait for it to become active.
	 */
	if (!HAS_PCH_CPT(dev)) {
		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
		POSTING_READ(intel_dp->output_reg);
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	}
1766

1767 1768 1769 1770
	/* Write the link configuration data */
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
				  intel_dp->link_configuration,
				  DP_LINK_CONFIGURATION_SIZE);
1771 1772

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
1773

1774
	memset(intel_dp->train_set, 0, 4);
1775
	voltage = 0xff;
1776 1777
	voltage_tries = 0;
	loop_tries = 0;
1778 1779
	clock_recovery = false;
	for (;;) {
1780
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1781
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1782
		uint32_t    signal_levels;
1783

K
Keith Packard 已提交
1784 1785 1786 1787 1788

		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1789
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1790 1791
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
1792 1793
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1794 1795
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}
1796

1797
		if (!intel_dp_set_link_train(intel_dp, DP,
1798 1799
					     DP_TRAINING_PATTERN_1 |
					     DP_LINK_SCRAMBLING_DISABLE))
1800 1801 1802
			break;
		/* Set training pattern 1 */

1803
		udelay(100);
1804 1805
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
1806
			break;
1807
		}
1808

1809 1810
		if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
			DRM_DEBUG_KMS("clock recovery OK\n");
1811 1812 1813 1814 1815 1816 1817
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1818
				break;
1819
		if (i == intel_dp->lane_count && voltage_tries == 5) {
1820 1821 1822 1823 1824 1825 1826 1827 1828
			++loop_tries;
			if (loop_tries == 5) {
				DRM_DEBUG_KMS("too many full retries, give up\n");
				break;
			}
			memset(intel_dp->train_set, 0, 4);
			voltage_tries = 0;
			continue;
		}
1829

1830 1831
		/* Check to see if we've tried the same voltage 5 times */
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1832 1833 1834
			++voltage_tries;
			if (voltage_tries == 5) {
				DRM_DEBUG_KMS("too many voltage retries, give up\n");
1835
				break;
1836
			}
1837
		} else
1838
			voltage_tries = 0;
1839
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1840

1841
		/* Compute new intel_dp->train_set as requested by target */
1842
		intel_get_adjust_train(intel_dp, link_status);
1843 1844
	}

1845 1846 1847 1848 1849 1850
	intel_dp->DP = DP;
}

static void
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
1851
	struct drm_device *dev = intel_dp->base.base.dev;
1852
	bool channel_eq = false;
1853
	int tries, cr_tries;
1854 1855
	uint32_t DP = intel_dp->DP;

1856 1857
	/* channel equalization */
	tries = 0;
1858
	cr_tries = 0;
1859 1860
	channel_eq = false;
	for (;;) {
1861
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1862
		uint32_t    signal_levels;
1863
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1864

1865 1866 1867 1868 1869 1870
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

K
Keith Packard 已提交
1871 1872 1873 1874
		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1875
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1876 1877
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
1878
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1879 1880 1881
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}

1882
		/* channel eq pattern */
1883
		if (!intel_dp_set_link_train(intel_dp, DP,
1884 1885
					     DP_TRAINING_PATTERN_2 |
					     DP_LINK_SCRAMBLING_DISABLE))
1886 1887
			break;

1888
		udelay(400);
1889
		if (!intel_dp_get_link_status(intel_dp, link_status))
1890 1891
			break;

1892
		/* Make sure clock is still ok */
1893
		if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1894 1895 1896 1897 1898
			intel_dp_start_link_train(intel_dp);
			cr_tries++;
			continue;
		}

1899
		if (intel_channel_eq_ok(intel_dp, link_status)) {
1900 1901 1902
			channel_eq = true;
			break;
		}
1903

1904 1905 1906 1907 1908 1909 1910 1911
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
			tries = 0;
			cr_tries++;
			continue;
		}
1912

1913
		/* Compute new intel_dp->train_set as requested by target */
1914
		intel_get_adjust_train(intel_dp, link_status);
1915
		++tries;
1916
	}
1917

1918
	intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1919 1920 1921
}

static void
C
Chris Wilson 已提交
1922
intel_dp_link_down(struct intel_dp *intel_dp)
1923
{
1924
	struct drm_device *dev = intel_dp->base.base.dev;
1925
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
1926
	uint32_t DP = intel_dp->DP;
1927

1928 1929 1930
	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
		return;

1931
	DRM_DEBUG_KMS("\n");
1932

1933
	if (is_edp(intel_dp)) {
1934
		DP &= ~DP_PLL_ENABLE;
C
Chris Wilson 已提交
1935 1936
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);
1937 1938 1939
		udelay(100);
	}

K
Keith Packard 已提交
1940
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1941
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
1942
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1943 1944
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
1945
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1946
	}
1947
	POSTING_READ(intel_dp->output_reg);
1948

1949
	msleep(17);
1950

1951
	if (is_edp(intel_dp)) {
K
Keith Packard 已提交
1952
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1953 1954 1955 1956
			DP |= DP_LINK_TRAIN_OFF_CPT;
		else
			DP |= DP_LINK_TRAIN_OFF;
	}
1957

1958
	if (HAS_PCH_IBX(dev) &&
1959
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1960 1961
		struct drm_crtc *crtc = intel_dp->base.base.crtc;

1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988
		if (crtc == NULL) {
			/* We can arrive here never having been attached
			 * to a CRTC, for instance, due to inheriting
			 * random state from the BIOS.
			 *
			 * If the pipe is not running, play safe and
			 * wait for the clocks to stabilise before
			 * continuing.
			 */
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
			intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1989 1990
	}

1991
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
1992 1993
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
1994
	msleep(intel_dp->panel_power_down_delay);
1995 1996
}

1997 1998
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
1999 2000
{
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2001
					   sizeof(intel_dp->dpcd)) &&
2002
	    (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
2003
		return true;
2004 2005
	}

2006
	return false;
2007 2008
}

2009 2010 2011 2012 2013 2014 2015 2016
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

D
Daniel Vetter 已提交
2017 2018
	ironlake_edp_panel_vdd_on(intel_dp);

2019 2020 2021 2022 2023 2024 2025
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2026 2027

	ironlake_edp_panel_vdd_off(intel_dp, false);
2028 2029
}

2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
}

2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

static void
C
Chris Wilson 已提交
2061
intel_dp_check_link_status(struct intel_dp *intel_dp)
2062
{
2063
	u8 sink_irq_vector;
2064
	u8 link_status[DP_LINK_STATUS_SIZE];
2065

2066
	if (!intel_dp->base.connectors_active)
2067
		return;
2068

2069
	if (WARN_ON(!intel_dp->base.base.crtc))
2070 2071
		return;

2072
	/* Try to read receiver status if the link appears to be up */
2073
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
2074
		intel_dp_link_down(intel_dp);
2075 2076 2077
		return;
	}

2078
	/* Now read the DPCD to see if it's actually running */
2079
	if (!intel_dp_get_dpcd(intel_dp)) {
2080 2081 2082 2083
		intel_dp_link_down(intel_dp);
		return;
	}

2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2098
	if (!intel_channel_eq_ok(intel_dp, link_status)) {
2099 2100
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
			      drm_get_encoder_name(&intel_dp->base.base));
2101 2102 2103
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
	}
2104 2105
}

2106
static enum drm_connector_status
2107
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2108
{
2109 2110 2111
	if (intel_dp_get_dpcd(intel_dp))
		return connector_status_connected;
	return connector_status_disconnected;
2112 2113
}

2114
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2115
ironlake_dp_detect(struct intel_dp *intel_dp)
2116 2117 2118
{
	enum drm_connector_status status;

2119 2120 2121 2122 2123 2124 2125
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		status = intel_panel_detect(intel_dp->base.base.dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2126

2127
	return intel_dp_detect_dpcd(intel_dp);
2128 2129
}

2130
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2131
g4x_dp_detect(struct intel_dp *intel_dp)
2132
{
2133
	struct drm_device *dev = intel_dp->base.base.dev;
2134
	struct drm_i915_private *dev_priv = dev->dev_private;
2135
	uint32_t bit;
2136

C
Chris Wilson 已提交
2137
	switch (intel_dp->output_reg) {
2138
	case DP_B:
2139
		bit = DPB_HOTPLUG_LIVE_STATUS;
2140 2141
		break;
	case DP_C:
2142
		bit = DPC_HOTPLUG_LIVE_STATUS;
2143 2144
		break;
	case DP_D:
2145
		bit = DPD_HOTPLUG_LIVE_STATUS;
2146 2147 2148 2149 2150
		break;
	default:
		return connector_status_unknown;
	}

2151
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2152 2153
		return connector_status_disconnected;

2154
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2155 2156
}

2157 2158 2159 2160 2161
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid	*edid;
2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
	int size;

	if (is_edp(intel_dp)) {
		if (!intel_dp->edid)
			return NULL;

		size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
		edid = kmalloc(size, GFP_KERNEL);
		if (!edid)
			return NULL;

		memcpy(edid, intel_dp->edid, size);
		return edid;
	}
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186

	edid = drm_get_edid(connector, adapter);
	return edid;
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	int	ret;

2187 2188 2189 2190 2191 2192 2193 2194 2195 2196
	if (is_edp(intel_dp)) {
		drm_mode_connector_update_edid_property(connector,
							intel_dp->edid);
		ret = drm_add_edid_modes(connector, intel_dp->edid);
		drm_edid_to_eld(connector,
				intel_dp->edid);
		connector->display_info.raw_edid = NULL;
		return intel_dp->edid_mode_count;
	}

2197 2198 2199 2200 2201
	ret = intel_ddc_get_modes(connector, adapter);
	return ret;
}


Z
Zhenyu Wang 已提交
2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
 *
 * \return true if DP port is connected.
 * \return false if DP port is disconnected.
 */
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct drm_device *dev = intel_dp->base.base.dev;
	enum drm_connector_status status;
	struct edid *edid = NULL;

	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
2222

2223 2224 2225 2226
	DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
		      intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
		      intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
		      intel_dp->dpcd[6], intel_dp->dpcd[7]);
2227

Z
Zhenyu Wang 已提交
2228 2229 2230
	if (status != connector_status_connected)
		return status;

2231 2232
	intel_dp_probe_oui(intel_dp);

2233 2234
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2235
	} else {
2236
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2237 2238 2239 2240 2241
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			connector->display_info.raw_edid = NULL;
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
2242 2243 2244
	}

	return connector_status_connected;
2245 2246 2247 2248
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
2249
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2250
	struct drm_device *dev = intel_dp->base.base.dev;
2251 2252
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
2253 2254 2255 2256

	/* We should parse the EDID data and find out if it has an audio sink
	 */

2257
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2258
	if (ret) {
2259
		if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2260 2261 2262
			struct drm_display_mode *newmode;
			list_for_each_entry(newmode, &connector->probed_modes,
					    head) {
2263 2264
				if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
					intel_dp->panel_fixed_mode =
2265 2266 2267 2268 2269
						drm_mode_duplicate(dev, newmode);
					break;
				}
			}
		}
2270
		return ret;
2271
	}
2272 2273

	/* if eDP has no EDID, try to use fixed panel mode from VBT */
2274
	if (is_edp(intel_dp)) {
2275
		/* initialize panel mode from VBT if available for eDP */
2276 2277
		if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
			intel_dp->panel_fixed_mode =
2278
				drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2279 2280
			if (intel_dp->panel_fixed_mode) {
				intel_dp->panel_fixed_mode->type |=
2281 2282 2283
					DRM_MODE_TYPE_PREFERRED;
			}
		}
2284
		if (intel_dp->panel_fixed_mode) {
2285
			struct drm_display_mode *mode;
2286
			mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2287 2288 2289 2290 2291
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
2292 2293
}

2294 2295 2296 2297 2298 2299 2300
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

2301
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2302 2303 2304 2305 2306 2307 2308 2309 2310 2311
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

2312 2313 2314 2315 2316
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
2317
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
2318 2319 2320 2321 2322 2323 2324
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

2325
	if (property == dev_priv->force_audio_property) {
2326 2327 2328 2329
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
2330 2331
			return 0;

2332
		intel_dp->force_audio = i;
2333

2334
		if (i == HDMI_AUDIO_AUTO)
2335 2336
			has_audio = intel_dp_detect_audio(connector);
		else
2337
			has_audio = (i == HDMI_AUDIO_ON);
2338 2339

		if (has_audio == intel_dp->has_audio)
2340 2341
			return 0;

2342
		intel_dp->has_audio = has_audio;
2343 2344 2345
		goto done;
	}

2346 2347 2348 2349 2350 2351 2352 2353
	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_dp->color_range)
			return 0;

		intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
		goto done;
	}

2354 2355 2356 2357 2358
	return -EINVAL;

done:
	if (intel_dp->base.base.crtc) {
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
2359 2360
		intel_set_mode(crtc, &crtc->mode,
			       crtc->x, crtc->y, crtc->fb);
2361 2362 2363 2364 2365
	}

	return 0;
}

2366
static void
2367
intel_dp_destroy(struct drm_connector *connector)
2368
{
2369 2370 2371 2372 2373
	struct drm_device *dev = connector->dev;

	if (intel_dpd_is_edp(dev))
		intel_panel_destroy_backlight(dev);

2374 2375
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
2376
	kfree(connector);
2377 2378
}

2379 2380 2381 2382 2383 2384
static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
2385
	if (is_edp(intel_dp)) {
2386
		kfree(intel_dp->edid);
2387 2388 2389
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		ironlake_panel_vdd_off_sync(intel_dp);
	}
2390 2391 2392
	kfree(intel_dp);
}

2393 2394 2395
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.mode_fixup = intel_dp_mode_fixup,
	.mode_set = intel_dp_mode_set,
2396
	.disable = intel_encoder_disable,
2397 2398 2399
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
2400
	.dpms = intel_dp_dpms,
2401 2402
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
2403
	.set_property = intel_dp_set_property,
2404 2405 2406 2407 2408 2409
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
2410
	.best_encoder = intel_best_encoder,
2411 2412 2413
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2414
	.destroy = intel_dp_encoder_destroy,
2415 2416
};

2417
static void
2418
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2419
{
C
Chris Wilson 已提交
2420
	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2421

2422
	intel_dp_check_link_status(intel_dp);
2423
}
2424

2425 2426
/* Return which DP Port should be selected for Transcoder DP control */
int
2427
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2428 2429
{
	struct drm_device *dev = crtc->dev;
2430
	struct intel_encoder *encoder;
2431

2432 2433
	for_each_encoder_on_crtc(dev, crtc, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2434

2435 2436
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
2437
			return intel_dp->output_reg;
2438
	}
C
Chris Wilson 已提交
2439

2440 2441 2442
	return -1;
}

2443
/* check the VBT to see whether the eDP is on DP-D port */
2444
bool intel_dpd_is_edp(struct drm_device *dev)
2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i;

	if (!dev_priv->child_dev_num)
		return false;

	for (i = 0; i < dev_priv->child_dev_num; i++) {
		p_child = dev_priv->child_dev + i;

		if (p_child->dvo_port == PORT_IDPD &&
		    p_child->device_type == DEVICE_TYPE_eDP)
			return true;
	}
	return false;
}

2463 2464 2465
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
2466
	intel_attach_force_audio_property(connector);
2467
	intel_attach_broadcast_rgb_property(connector);
2468 2469
}

2470
void
2471
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2472 2473 2474
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
C
Chris Wilson 已提交
2475
	struct intel_dp *intel_dp;
2476
	struct intel_encoder *intel_encoder;
2477
	struct intel_connector *intel_connector;
2478
	const char *name = NULL;
2479
	int type;
2480

C
Chris Wilson 已提交
2481 2482
	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
	if (!intel_dp)
2483 2484
		return;

2485
	intel_dp->output_reg = output_reg;
2486
	intel_dp->port = port;
2487

2488 2489
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
C
Chris Wilson 已提交
2490
		kfree(intel_dp);
2491 2492
		return;
	}
C
Chris Wilson 已提交
2493
	intel_encoder = &intel_dp->base;
2494

C
Chris Wilson 已提交
2495
	if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2496
		if (intel_dpd_is_edp(dev))
C
Chris Wilson 已提交
2497
			intel_dp->is_pch_edp = true;
2498

2499
	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2500 2501 2502 2503 2504 2505 2506
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
	} else {
		type = DRM_MODE_CONNECTOR_DisplayPort;
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
	}

2507
	connector = &intel_connector->base;
2508
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2509 2510
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

2511 2512
	connector->polled = DRM_CONNECTOR_POLL_HPD;

2513
	intel_encoder->cloneable = false;
2514

2515 2516
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
			  ironlake_panel_vdd_work);
Z
Zhenyu Wang 已提交
2517

J
Jesse Barnes 已提交
2518
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2519

2520 2521 2522
	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

2523
	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2524
			 DRM_MODE_ENCODER_TMDS);
2525
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2526

2527
	intel_connector_attach_encoder(intel_connector, intel_encoder);
2528 2529
	drm_sysfs_connector_add(connector);

2530 2531
	intel_encoder->enable = intel_enable_dp;
	intel_encoder->disable = intel_disable_dp;
2532 2533
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
	intel_connector->get_hw_state = intel_connector_get_hw_state;
2534

2535
	/* Set up the DDC bus. */
2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554
	switch (port) {
	case PORT_A:
		name = "DPDDC-A";
		break;
	case PORT_B:
		dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
		name = "DPDDC-B";
		break;
	case PORT_C:
		dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
		name = "DPDDC-C";
		break;
	case PORT_D:
		dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
		name = "DPDDC-D";
		break;
	default:
		WARN(1, "Invalid port %c\n", port_name(port));
		break;
2555 2556
	}

2557 2558
	intel_dp_i2c_init(intel_dp, intel_connector, name);

J
Jesse Barnes 已提交
2559 2560
	/* Cache some DPCD data in the eDP case */
	if (is_edp(intel_dp)) {
2561
		bool ret;
2562 2563
		struct edp_power_seq	cur, vbt;
		u32 pp_on, pp_off, pp_div;
2564
		struct edid *edid;
2565 2566

		pp_on = I915_READ(PCH_PP_ON_DELAYS);
2567
		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2568
		pp_div = I915_READ(PCH_PP_DIVISOR);
J
Jesse Barnes 已提交
2569

2570 2571 2572 2573 2574 2575 2576
		if (!pp_on || !pp_off || !pp_div) {
			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
			intel_dp_encoder_destroy(&intel_dp->base.base);
			intel_dp_destroy(&intel_connector->base);
			return;
		}

2577 2578 2579 2580 2581 2582
		/* Pull timing values out of registers */
		cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
			PANEL_POWER_UP_DELAY_SHIFT;

		cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
			PANEL_LIGHT_ON_DELAY_SHIFT;
2583

2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614
		cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
			PANEL_LIGHT_OFF_DELAY_SHIFT;

		cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
			PANEL_POWER_DOWN_DELAY_SHIFT;

		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
			       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

		DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
			      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

		vbt = dev_priv->edp.pps;

		DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
			      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

#define get_delay(field)	((max(cur.field, vbt.field) + 9) / 10)

		intel_dp->panel_power_up_delay = get_delay(t1_t3);
		intel_dp->backlight_on_delay = get_delay(t8);
		intel_dp->backlight_off_delay = get_delay(t9);
		intel_dp->panel_power_down_delay = get_delay(t10);
		intel_dp->panel_power_cycle_delay = get_delay(t11_t12);

		DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
			      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
			      intel_dp->panel_power_cycle_delay);

		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
			      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2615 2616

		ironlake_edp_panel_vdd_on(intel_dp);
2617
		ret = intel_dp_get_dpcd(intel_dp);
2618
		ironlake_edp_panel_vdd_off(intel_dp, false);
2619

2620
		if (ret) {
2621 2622 2623
			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
				dev_priv->no_aux_handshake =
					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
J
Jesse Barnes 已提交
2624 2625
					DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		} else {
2626
			/* if this fails, presume the device is a ghost */
2627
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2628
			intel_dp_encoder_destroy(&intel_dp->base.base);
2629
			intel_dp_destroy(&intel_connector->base);
2630
			return;
J
Jesse Barnes 已提交
2631 2632
		}

2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644
		ironlake_edp_panel_vdd_on(intel_dp);
		edid = drm_get_edid(connector, &intel_dp->adapter);
		if (edid) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			intel_dp->edid_mode_count =
				drm_add_edid_modes(connector, edid);
			drm_edid_to_eld(connector, edid);
			intel_dp->edid = edid;
		}
		ironlake_edp_panel_vdd_off(intel_dp, false);
	}
2645

2646
	intel_encoder->hot_plug = intel_dp_hot_plug;
2647

2648
	if (is_edp(intel_dp)) {
2649 2650
		dev_priv->int_edp_connector = connector;
		intel_panel_setup_backlight(dev);
2651 2652
	}

2653 2654
	intel_dp_add_properties(intel_dp, connector);

2655 2656 2657 2658 2659 2660 2661 2662 2663
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}