amdgpu_device.c 91.7 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
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#include <linux/power_supply.h>
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#include <linux/kthread.h>
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#include <linux/console.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/amdgpu_drm.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>
#include <linux/efi.h>
#include "amdgpu.h"
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#include "amdgpu_trace.h"
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#include "amdgpu_i2c.h"
#include "atom.h"
#include "amdgpu_atombios.h"
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#include "amdgpu_atomfirmware.h"
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#include "amd_pcie.h"
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#ifdef CONFIG_DRM_AMDGPU_SI
#include "si.h"
#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
#include "cik.h"
#endif
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#include "vi.h"
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#include "soc15.h"
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#include "bif/bif_4_1_d.h"
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include "amdgpu_vf_error.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_pm.h"
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MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
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#define AMDGPU_RESUME_MS		2000

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static const char *amdgpu_asic_name[] = {
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	"TAHITI",
	"PITCAIRN",
	"VERDE",
	"OLAND",
	"HAINAN",
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	"BONAIRE",
	"KAVERI",
	"KABINI",
	"HAWAII",
	"MULLINS",
	"TOPAZ",
	"TONGA",
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	"FIJI",
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	"CARRIZO",
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	"STONEY",
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	"POLARIS10",
	"POLARIS11",
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	"POLARIS12",
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	"VEGAM",
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	"VEGA10",
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	"VEGA12",
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	"VEGA20",
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	"RAVEN",
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	"LAST",
};

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static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);

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/**
 * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 *
 * @dev: drm_device pointer
 *
 * Returns true if the device is a dGPU with HG/PX power control,
 * otherwise return false.
 */
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bool amdgpu_device_is_px(struct drm_device *dev)
{
	struct amdgpu_device *adev = dev->dev_private;

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	if (adev->flags & AMD_IS_PX)
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		return true;
	return false;
}

/*
 * MMIO register access helper functions.
 */
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/**
 * amdgpu_mm_rreg - read a memory mapped IO register
 *
 * @adev: amdgpu_device pointer
 * @reg: dword aligned register offset
 * @acc_flags: access flags which require special behavior
 *
 * Returns the 32 bit value from the offset specified.
 */
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uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
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			uint32_t acc_flags)
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{
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	uint32_t ret;

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	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
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		return amdgpu_virt_kiq_rreg(adev, reg);

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	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
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		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
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	else {
		unsigned long flags;

		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
	}
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	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
	return ret;
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}

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/*
 * MMIO register read with bytes helper functions
 * @offset:bytes offset from MMIO start
 *
*/

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/**
 * amdgpu_mm_rreg8 - read a memory mapped IO register
 *
 * @adev: amdgpu_device pointer
 * @offset: byte aligned register offset
 *
 * Returns the 8 bit value from the offset specified.
 */
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uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
	if (offset < adev->rmmio_size)
		return (readb(adev->rmmio + offset));
	BUG();
}

/*
 * MMIO register write with bytes helper functions
 * @offset:bytes offset from MMIO start
 * @value: the value want to be written to the register
 *
*/
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/**
 * amdgpu_mm_wreg8 - read a memory mapped IO register
 *
 * @adev: amdgpu_device pointer
 * @offset: byte aligned register offset
 * @value: 8 bit value to write
 *
 * Writes the value specified to the offset specified.
 */
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void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
	if (offset < adev->rmmio_size)
		writeb(value, adev->rmmio + offset);
	else
		BUG();
}

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/**
 * amdgpu_mm_wreg - write to a memory mapped IO register
 *
 * @adev: amdgpu_device pointer
 * @reg: dword aligned register offset
 * @v: 32 bit value to write to the register
 * @acc_flags: access flags which require special behavior
 *
 * Writes the value specified to the offset specified.
 */
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void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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		    uint32_t acc_flags)
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{
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	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
		adev->last_mm_index = v;
	}

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	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
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		return amdgpu_virt_kiq_wreg(adev, reg, v);

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	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
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		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
	else {
		unsigned long flags;

		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
	}
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
		udelay(500);
	}
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}

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/**
 * amdgpu_io_rreg - read an IO register
 *
 * @adev: amdgpu_device pointer
 * @reg: dword aligned register offset
 *
 * Returns the 32 bit value from the offset specified.
 */
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u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
{
	if ((reg * 4) < adev->rio_mem_size)
		return ioread32(adev->rio_mem + (reg * 4));
	else {
		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
		return ioread32(adev->rio_mem + (mmMM_DATA * 4));
	}
}

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/**
 * amdgpu_io_wreg - write to an IO register
 *
 * @adev: amdgpu_device pointer
 * @reg: dword aligned register offset
 * @v: 32 bit value to write to the register
 *
 * Writes the value specified to the offset specified.
 */
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void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
		adev->last_mm_index = v;
	}
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	if ((reg * 4) < adev->rio_mem_size)
		iowrite32(v, adev->rio_mem + (reg * 4));
	else {
		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
		iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
	}
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
		udelay(500);
	}
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}

/**
 * amdgpu_mm_rdoorbell - read a doorbell dword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 *
 * Returns the value in the doorbell aperture at the
 * requested doorbell index (CIK).
 */
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
{
	if (index < adev->doorbell.num_doorbells) {
		return readl(adev->doorbell.ptr + index);
	} else {
		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
		return 0;
	}
}

/**
 * amdgpu_mm_wdoorbell - write a doorbell dword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 * @v: value to write
 *
 * Writes @v to the doorbell aperture at the
 * requested doorbell index (CIK).
 */
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
{
	if (index < adev->doorbell.num_doorbells) {
		writel(v, adev->doorbell.ptr + index);
	} else {
		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
	}
}

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/**
 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 *
 * Returns the value in the doorbell aperture at the
 * requested doorbell index (VEGA10+).
 */
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
{
	if (index < adev->doorbell.num_doorbells) {
		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
	} else {
		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
		return 0;
	}
}

/**
 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 * @v: value to write
 *
 * Writes @v to the doorbell aperture at the
 * requested doorbell index (VEGA10+).
 */
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
{
	if (index < adev->doorbell.num_doorbells) {
		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
	} else {
		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
	}
}

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/**
 * amdgpu_invalid_rreg - dummy reg read function
 *
 * @adev: amdgpu device pointer
 * @reg: offset of register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 * Returns the value in the register.
 */
static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
{
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
	BUG();
	return 0;
}

/**
 * amdgpu_invalid_wreg - dummy reg write function
 *
 * @adev: amdgpu device pointer
 * @reg: offset of register
 * @v: value to write to the register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 */
static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
{
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		  reg, v);
	BUG();
}

/**
 * amdgpu_block_invalid_rreg - dummy reg read function
 *
 * @adev: amdgpu device pointer
 * @block: offset of instance
 * @reg: offset of register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 * Returns the value in the register.
 */
static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
					  uint32_t block, uint32_t reg)
{
	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
		  reg, block);
	BUG();
	return 0;
}

/**
 * amdgpu_block_invalid_wreg - dummy reg write function
 *
 * @adev: amdgpu device pointer
 * @block: offset of instance
 * @reg: offset of register
 * @v: value to write to the register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 */
static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
				      uint32_t block,
				      uint32_t reg, uint32_t v)
{
	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
		  reg, block, v);
	BUG();
}

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/**
 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 *
 * @adev: amdgpu device pointer
 *
 * Allocates a scratch page of VRAM for use by various things in the
 * driver.
 */
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static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
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{
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	return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
				       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
				       &adev->vram_scratch.robj,
				       &adev->vram_scratch.gpu_addr,
				       (void **)&adev->vram_scratch.ptr);
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}

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/**
 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 *
 * @adev: amdgpu device pointer
 *
 * Frees the VRAM scratch page.
 */
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static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
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{
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	amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
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}

/**
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 * amdgpu_device_program_register_sequence - program an array of registers.
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 *
 * @adev: amdgpu_device pointer
 * @registers: pointer to the register array
 * @array_size: size of the register array
 *
 * Programs an array or registers with and and or masks.
 * This is a helper for setting golden registers.
 */
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void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
					     const u32 *registers,
					     const u32 array_size)
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{
	u32 tmp, reg, and_mask, or_mask;
	int i;

	if (array_size % 3)
		return;

	for (i = 0; i < array_size; i +=3) {
		reg = registers[i + 0];
		and_mask = registers[i + 1];
		or_mask = registers[i + 2];

		if (and_mask == 0xffffffff) {
			tmp = or_mask;
		} else {
			tmp = RREG32(reg);
			tmp &= ~and_mask;
			tmp |= or_mask;
		}
		WREG32(reg, tmp);
	}
}

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/**
 * amdgpu_device_pci_config_reset - reset the GPU
 *
 * @adev: amdgpu_device pointer
 *
 * Resets the GPU using the pci config reset sequence.
 * Only applicable to asics prior to vega10.
 */
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void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
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{
	pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
}

/*
 * GPU doorbell aperture helpers function.
 */
/**
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 * amdgpu_device_doorbell_init - Init doorbell driver information.
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 *
 * @adev: amdgpu_device pointer
 *
 * Init doorbell driver information (CIK)
 * Returns 0 on success, error on failure.
 */
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static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
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{
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	/* No doorbell on SI hardware generation */
	if (adev->asic_type < CHIP_BONAIRE) {
		adev->doorbell.base = 0;
		adev->doorbell.size = 0;
		adev->doorbell.num_doorbells = 0;
		adev->doorbell.ptr = NULL;
		return 0;
	}

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	if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
		return -EINVAL;

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	/* doorbell bar mapping */
	adev->doorbell.base = pci_resource_start(adev->pdev, 2);
	adev->doorbell.size = pci_resource_len(adev->pdev, 2);

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	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
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					     AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
	if (adev->doorbell.num_doorbells == 0)
		return -EINVAL;

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	adev->doorbell.ptr = ioremap(adev->doorbell.base,
				     adev->doorbell.num_doorbells *
				     sizeof(u32));
	if (adev->doorbell.ptr == NULL)
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		return -ENOMEM;

	return 0;
}

/**
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 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
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 *
 * @adev: amdgpu_device pointer
 *
 * Tear down doorbell driver information (CIK)
 */
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static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
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{
	iounmap(adev->doorbell.ptr);
	adev->doorbell.ptr = NULL;
}

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/*
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 * amdgpu_device_wb_*()
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 * Writeback is the method by which the GPU updates special pages in memory
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 * with the status of certain GPU events (fences, ring pointers,etc.).
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 */

/**
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 * amdgpu_device_wb_fini - Disable Writeback and free memory
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 *
 * @adev: amdgpu_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
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static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
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{
	if (adev->wb.wb_obj) {
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		amdgpu_bo_free_kernel(&adev->wb.wb_obj,
				      &adev->wb.gpu_addr,
				      (void **)&adev->wb.wb);
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		adev->wb.wb_obj = NULL;
	}
}

/**
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 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
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 *
 * @adev: amdgpu_device pointer
 *
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 * Initializes writeback and allocates writeback memory (all asics).
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 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
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static int amdgpu_device_wb_init(struct amdgpu_device *adev)
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{
	int r;

	if (adev->wb.wb_obj == NULL) {
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		/* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
		r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
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					    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
					    &adev->wb.wb_obj, &adev->wb.gpu_addr,
					    (void **)&adev->wb.wb);
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Alex Deucher 已提交
604 605 606 607 608 609 610 611 612
		if (r) {
			dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}

		adev->wb.num_wb = AMDGPU_MAX_WB;
		memset(&adev->wb.used, 0, sizeof(adev->wb.used));

		/* clear wb memory */
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		memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
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Alex Deucher 已提交
614 615 616 617 618 619
	}

	return 0;
}

/**
620
 * amdgpu_device_wb_get - Allocate a wb entry
A
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621 622 623 624 625 626 627
 *
 * @adev: amdgpu_device pointer
 * @wb: wb index
 *
 * Allocate a wb slot for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
628
int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
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Alex Deucher 已提交
629 630 631
{
	unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);

632
	if (offset < adev->wb.num_wb) {
K
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633
		__set_bit(offset, adev->wb.used);
M
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634
		*wb = offset << 3; /* convert to dw offset */
635 636 637 638 639 640
		return 0;
	} else {
		return -EINVAL;
	}
}

A
Alex Deucher 已提交
641
/**
642
 * amdgpu_device_wb_free - Free a wb entry
A
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643 644 645 646 647 648
 *
 * @adev: amdgpu_device pointer
 * @wb: wb index
 *
 * Free a wb slot allocated for use by the driver (all asics)
 */
649
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
A
Alex Deucher 已提交
650
{
M
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651
	wb >>= 3;
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652
	if (wb < adev->wb.num_wb)
M
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653
		__clear_bit(wb, adev->wb.used);
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654 655
}

656 657 658 659 660 661 662 663 664 665 666
/**
 * amdgpu_device_resize_fb_bar - try to resize FB BAR
 *
 * @adev: amdgpu_device pointer
 *
 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 * to fail, but if any of the BARs is not accessible after the size we abort
 * driver loading by returning -ENODEV.
 */
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
{
667
	u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
668
	u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
669 670 671
	struct pci_bus *root;
	struct resource *res;
	unsigned i;
672 673 674
	u16 cmd;
	int r;

675 676 677 678
	/* Bypass for VF */
	if (amdgpu_sriov_vf(adev))
		return 0;

679 680 681 682 683 684
	/* Check if the root BUS has 64bit memory resources */
	root = adev->pdev->bus;
	while (root->parent)
		root = root->parent;

	pci_bus_for_each_resource(root, res, i) {
685
		if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
686 687 688 689 690 691 692 693
		    res->start > 0x100000000ull)
			break;
	}

	/* Trying to resize is pointless without a root hub window above 4GB */
	if (!res)
		return 0;

694 695 696 697 698 699
	/* Disable memory decoding while we change the BAR addresses and size */
	pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
	pci_write_config_word(adev->pdev, PCI_COMMAND,
			      cmd & ~PCI_COMMAND_MEMORY);

	/* Free the VRAM and doorbell BAR, we most likely need to move both. */
700
	amdgpu_device_doorbell_fini(adev);
701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716
	if (adev->asic_type >= CHIP_BONAIRE)
		pci_release_resource(adev->pdev, 2);

	pci_release_resource(adev->pdev, 0);

	r = pci_resize_resource(adev->pdev, 0, rbar_size);
	if (r == -ENOSPC)
		DRM_INFO("Not enough PCI address space for a large BAR.");
	else if (r && r != -ENOTSUPP)
		DRM_ERROR("Problem resizing BAR0 (%d).", r);

	pci_assign_unassigned_bus_resources(adev->pdev->bus);

	/* When the doorbell or fb BAR isn't available we have no chance of
	 * using the device.
	 */
717
	r = amdgpu_device_doorbell_init(adev);
718 719 720 721 722 723 724
	if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
		return -ENODEV;

	pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);

	return 0;
}
725

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Alex Deucher 已提交
726 727 728 729
/*
 * GPU helpers function.
 */
/**
A
Alex Deucher 已提交
730
 * amdgpu_device_need_post - check if the hw need post or not
A
Alex Deucher 已提交
731 732 733
 *
 * @adev: amdgpu_device pointer
 *
734 735 736
 * Check if the asic has been initialized (all asics) at driver startup
 * or post is needed if  hw reset is performed.
 * Returns true if need or false if not.
A
Alex Deucher 已提交
737
 */
A
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738
bool amdgpu_device_need_post(struct amdgpu_device *adev)
A
Alex Deucher 已提交
739 740 741
{
	uint32_t reg;

742 743 744 745
	if (amdgpu_sriov_vf(adev))
		return false;

	if (amdgpu_passthrough(adev)) {
M
Monk Liu 已提交
746 747 748 749
		/* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
		 * some old smc fw still need driver do vPost otherwise gpu hang, while
		 * those smc fw version above 22.15 doesn't have this flaw, so we force
		 * vpost executed for smc version below 22.15
750 751 752 753 754 755 756 757 758 759
		 */
		if (adev->asic_type == CHIP_FIJI) {
			int err;
			uint32_t fw_ver;
			err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
			/* force vPost if error occured */
			if (err)
				return true;

			fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
M
Monk Liu 已提交
760 761
			if (fw_ver < 0x00160e00)
				return true;
762 763
		}
	}
764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780

	if (adev->has_hw_reset) {
		adev->has_hw_reset = false;
		return true;
	}

	/* bios scratch used on CIK+ */
	if (adev->asic_type >= CHIP_BONAIRE)
		return amdgpu_atombios_scratch_need_asic_init(adev);

	/* check MEM_SIZE for older asics */
	reg = amdgpu_asic_get_config_memsize(adev);

	if ((reg != 0) && (reg != 0xffffffff))
		return false;

	return true;
781 782
}

A
Alex Deucher 已提交
783 784
/* if we get transitioned to only one device, take VGA back */
/**
785
 * amdgpu_device_vga_set_decode - enable/disable vga decode
A
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786 787 788 789 790 791 792
 *
 * @cookie: amdgpu_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
793
static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
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794 795 796 797 798 799 800 801 802 803
{
	struct amdgpu_device *adev = cookie;
	amdgpu_asic_set_vga_state(adev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

804 805 806 807 808 809 810 811 812 813
/**
 * amdgpu_device_check_block_size - validate the vm block size
 *
 * @adev: amdgpu_device pointer
 *
 * Validates the vm block size specified via module parameter.
 * The vm block size defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 * page table and the remaining bits are in the page directory.
 */
814
static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
815 816 817 818
{
	/* defines number of bits in page table versus page directory,
	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
	 * page table and the remaining bits are in the page directory */
819 820
	if (amdgpu_vm_block_size == -1)
		return;
821

822
	if (amdgpu_vm_block_size < 9) {
823 824
		dev_warn(adev->dev, "VM page table size (%d) too small\n",
			 amdgpu_vm_block_size);
825
		amdgpu_vm_block_size = -1;
826 827 828
	}
}

829 830 831 832 833 834 835 836
/**
 * amdgpu_device_check_vm_size - validate the vm size
 *
 * @adev: amdgpu_device pointer
 *
 * Validates the vm size in GB specified via module parameter.
 * The VM size is the size of the GPU virtual memory space in GB.
 */
837
static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
838
{
839 840 841 842
	/* no need to check the default value */
	if (amdgpu_vm_size == -1)
		return;

843 844 845
	if (amdgpu_vm_size < 1) {
		dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
			 amdgpu_vm_size);
846
		amdgpu_vm_size = -1;
847 848 849
	}
}

850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889
static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
{
	struct sysinfo si;
	bool is_os_64 = (sizeof(void *) == 8) ? true : false;
	uint64_t total_memory;
	uint64_t dram_size_seven_GB = 0x1B8000000;
	uint64_t dram_size_three_GB = 0xB8000000;

	if (amdgpu_smu_memory_pool_size == 0)
		return;

	if (!is_os_64) {
		DRM_WARN("Not 64-bit OS, feature not supported\n");
		goto def_value;
	}
	si_meminfo(&si);
	total_memory = (uint64_t)si.totalram * si.mem_unit;

	if ((amdgpu_smu_memory_pool_size == 1) ||
		(amdgpu_smu_memory_pool_size == 2)) {
		if (total_memory < dram_size_three_GB)
			goto def_value1;
	} else if ((amdgpu_smu_memory_pool_size == 4) ||
		(amdgpu_smu_memory_pool_size == 8)) {
		if (total_memory < dram_size_seven_GB)
			goto def_value1;
	} else {
		DRM_WARN("Smu memory pool size not supported\n");
		goto def_value;
	}
	adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;

	return;

def_value1:
	DRM_WARN("No enough system memory\n");
def_value:
	adev->pm.smu_prv_buffer_size = 0;
}

A
Alex Deucher 已提交
890
/**
891
 * amdgpu_device_check_arguments - validate module params
A
Alex Deucher 已提交
892 893 894 895 896 897
 *
 * @adev: amdgpu_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
898
static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
A
Alex Deucher 已提交
899
{
900 901 902 903
	if (amdgpu_sched_jobs < 4) {
		dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
			 amdgpu_sched_jobs);
		amdgpu_sched_jobs = 4;
904
	} else if (!is_power_of_2(amdgpu_sched_jobs)){
905 906 907 908
		dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
			 amdgpu_sched_jobs);
		amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
	}
A
Alex Deucher 已提交
909

910
	if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
911 912 913
		/* gart size must be greater or equal to 32M */
		dev_warn(adev->dev, "gart size (%d) too small\n",
			 amdgpu_gart_size);
914
		amdgpu_gart_size = -1;
A
Alex Deucher 已提交
915 916
	}

917
	if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
918
		/* gtt size must be greater or equal to 32M */
919 920 921
		dev_warn(adev->dev, "gtt size (%d) too small\n",
				 amdgpu_gtt_size);
		amdgpu_gtt_size = -1;
A
Alex Deucher 已提交
922 923
	}

924 925 926 927 928 929 930
	/* valid range is between 4 and 9 inclusive */
	if (amdgpu_vm_fragment_size != -1 &&
	    (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
		dev_warn(adev->dev, "valid range is between 4 and 9\n");
		amdgpu_vm_fragment_size = -1;
	}

931 932
	amdgpu_device_check_smu_prv_buffer_size(adev);

933
	amdgpu_device_check_vm_size(adev);
A
Alex Deucher 已提交
934

935
	amdgpu_device_check_block_size(adev);
C
Christian König 已提交
936

937
	if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
938
	    !is_power_of_2(amdgpu_vram_page_split))) {
C
Christian König 已提交
939 940 941 942
		dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
			 amdgpu_vram_page_split);
		amdgpu_vram_page_split = 1024;
	}
943 944 945 946 947

	if (amdgpu_lockup_timeout == 0) {
		dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
		amdgpu_lockup_timeout = 10000;
	}
948 949

	adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
A
Alex Deucher 已提交
950 951 952 953 954 955
}

/**
 * amdgpu_switcheroo_set_state - set switcheroo state
 *
 * @pdev: pci dev pointer
956
 * @state: vga_switcheroo state
A
Alex Deucher 已提交
957 958 959 960 961 962 963 964 965 966 967 968
 *
 * Callback for the switcheroo driver.  Suspends or resumes the
 * the asics before or after it is powered up using ACPI methods.
 */
static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
		return;

	if (state == VGA_SWITCHEROO_ON) {
969
		pr_info("amdgpu: switched on\n");
A
Alex Deucher 已提交
970 971 972
		/* don't suspend or resume card normally */
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

973
		amdgpu_device_resume(dev, true, true);
A
Alex Deucher 已提交
974 975 976 977

		dev->switch_power_state = DRM_SWITCH_POWER_ON;
		drm_kms_helper_poll_enable(dev);
	} else {
978
		pr_info("amdgpu: switched off\n");
A
Alex Deucher 已提交
979 980
		drm_kms_helper_poll_disable(dev);
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
981
		amdgpu_device_suspend(dev, true, true);
A
Alex Deucher 已提交
982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
	}
}

/**
 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
 *
 * @pdev: pci dev pointer
 *
 * Callback for the switcheroo driver.  Check of the switcheroo
 * state can be changed.
 * Returns true if the state can be changed, false if not.
 */
static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	/*
	* FIXME: open_count is protected by drm_global_mutex but that would lead to
	* locking inversion with the driver load path. And the access here is
	* completely racy anyway. So don't bother with locking for now.
	*/
	return dev->open_count == 0;
}

static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
	.set_gpu_state = amdgpu_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = amdgpu_switcheroo_can_switch,
};

1013 1014 1015
/**
 * amdgpu_device_ip_set_clockgating_state - set the CG state
 *
1016
 * @dev: amdgpu_device pointer
1017 1018 1019 1020 1021 1022 1023
 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
 * @state: clockgating state (gate or ungate)
 *
 * Sets the requested clockgating state for all instances of
 * the hardware IP specified.
 * Returns the error code from the last instance.
 */
1024
int amdgpu_device_ip_set_clockgating_state(void *dev,
1025 1026
					   enum amd_ip_block_type block_type,
					   enum amd_clockgating_state state)
A
Alex Deucher 已提交
1027
{
1028
	struct amdgpu_device *adev = dev;
A
Alex Deucher 已提交
1029 1030 1031
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1032
		if (!adev->ip_blocks[i].status.valid)
1033
			continue;
1034 1035 1036 1037 1038 1039 1040 1041 1042
		if (adev->ip_blocks[i].version->type != block_type)
			continue;
		if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
			continue;
		r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
			(void *)adev, state);
		if (r)
			DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1043 1044 1045 1046
	}
	return r;
}

1047 1048 1049
/**
 * amdgpu_device_ip_set_powergating_state - set the PG state
 *
1050
 * @dev: amdgpu_device pointer
1051 1052 1053 1054 1055 1056 1057
 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
 * @state: powergating state (gate or ungate)
 *
 * Sets the requested powergating state for all instances of
 * the hardware IP specified.
 * Returns the error code from the last instance.
 */
1058
int amdgpu_device_ip_set_powergating_state(void *dev,
1059 1060
					   enum amd_ip_block_type block_type,
					   enum amd_powergating_state state)
A
Alex Deucher 已提交
1061
{
1062
	struct amdgpu_device *adev = dev;
A
Alex Deucher 已提交
1063 1064 1065
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1066
		if (!adev->ip_blocks[i].status.valid)
1067
			continue;
1068 1069 1070 1071 1072 1073 1074 1075 1076
		if (adev->ip_blocks[i].version->type != block_type)
			continue;
		if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
			continue;
		r = adev->ip_blocks[i].version->funcs->set_powergating_state(
			(void *)adev, state);
		if (r)
			DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1077 1078 1079 1080
	}
	return r;
}

1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091
/**
 * amdgpu_device_ip_get_clockgating_state - get the CG state
 *
 * @adev: amdgpu_device pointer
 * @flags: clockgating feature flags
 *
 * Walks the list of IPs on the device and updates the clockgating
 * flags for each IP.
 * Updates @flags with the feature flags for each hardware IP where
 * clockgating is enabled.
 */
1092 1093
void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
					    u32 *flags)
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
			adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
	}
}

1105 1106 1107 1108 1109 1110 1111 1112 1113
/**
 * amdgpu_device_ip_wait_for_idle - wait for idle
 *
 * @adev: amdgpu_device pointer
 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
 *
 * Waits for the request hardware IP to be idle.
 * Returns 0 for success or a negative error code on failure.
 */
1114 1115
int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
				   enum amd_ip_block_type block_type)
1116 1117 1118 1119
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1120
		if (!adev->ip_blocks[i].status.valid)
1121
			continue;
1122 1123
		if (adev->ip_blocks[i].version->type == block_type) {
			r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1124 1125 1126 1127 1128 1129 1130 1131 1132
			if (r)
				return r;
			break;
		}
	}
	return 0;

}

1133 1134 1135 1136 1137 1138 1139 1140 1141
/**
 * amdgpu_device_ip_is_idle - is the hardware IP idle
 *
 * @adev: amdgpu_device pointer
 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
 *
 * Check if the hardware IP is idle or not.
 * Returns true if it the IP is idle, false if not.
 */
1142 1143
bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
			      enum amd_ip_block_type block_type)
1144 1145 1146 1147
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1148
		if (!adev->ip_blocks[i].status.valid)
1149
			continue;
1150 1151
		if (adev->ip_blocks[i].version->type == block_type)
			return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1152 1153 1154 1155 1156
	}
	return true;

}

1157 1158 1159 1160
/**
 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
 *
 * @adev: amdgpu_device pointer
1161
 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1162 1163 1164 1165
 *
 * Returns a pointer to the hardware IP block structure
 * if it exists for the asic, otherwise NULL.
 */
1166 1167 1168
struct amdgpu_ip_block *
amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
			      enum amd_ip_block_type type)
A
Alex Deucher 已提交
1169 1170 1171 1172
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++)
1173
		if (adev->ip_blocks[i].version->type == type)
A
Alex Deucher 已提交
1174 1175 1176 1177 1178 1179
			return &adev->ip_blocks[i];

	return NULL;
}

/**
1180
 * amdgpu_device_ip_block_version_cmp
A
Alex Deucher 已提交
1181 1182
 *
 * @adev: amdgpu_device pointer
1183
 * @type: enum amd_ip_block_type
A
Alex Deucher 已提交
1184 1185 1186 1187 1188 1189
 * @major: major version
 * @minor: minor version
 *
 * return 0 if equal or greater
 * return 1 if smaller or the ip_block doesn't exist
 */
1190 1191 1192
int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
				       enum amd_ip_block_type type,
				       u32 major, u32 minor)
A
Alex Deucher 已提交
1193
{
1194
	struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
A
Alex Deucher 已提交
1195

1196 1197 1198
	if (ip_block && ((ip_block->version->major > major) ||
			((ip_block->version->major == major) &&
			(ip_block->version->minor >= minor))))
A
Alex Deucher 已提交
1199 1200 1201 1202 1203
		return 0;

	return 1;
}

1204
/**
1205
 * amdgpu_device_ip_block_add
1206 1207 1208 1209 1210 1211 1212
 *
 * @adev: amdgpu_device pointer
 * @ip_block_version: pointer to the IP to add
 *
 * Adds the IP block driver information to the collection of IPs
 * on the asic.
 */
1213 1214
int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
			       const struct amdgpu_ip_block_version *ip_block_version)
1215 1216 1217 1218
{
	if (!ip_block_version)
		return -EINVAL;

1219
	DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1220 1221
		  ip_block_version->funcs->name);

1222 1223 1224 1225 1226
	adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;

	return 0;
}

1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238
/**
 * amdgpu_device_enable_virtual_display - enable virtual display feature
 *
 * @adev: amdgpu_device pointer
 *
 * Enabled the virtual display feature if the user has enabled it via
 * the module parameter virtual_display.  This feature provides a virtual
 * display hardware on headless boards or in virtualized environments.
 * This function parses and validates the configuration string specified by
 * the user and configues the virtual display configuration (number of
 * virtual connectors, crtcs, etc.) specified.
 */
1239
static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1240 1241 1242 1243 1244 1245
{
	adev->enable_virtual_display = false;

	if (amdgpu_virtual_display) {
		struct drm_device *ddev = adev->ddev;
		const char *pci_address_name = pci_name(ddev->pdev);
1246
		char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1247 1248 1249

		pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
		pciaddstr_tmp = pciaddstr;
1250 1251
		while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
			pciaddname = strsep(&pciaddname_tmp, ",");
1252 1253
			if (!strcmp("all", pciaddname)
			    || !strcmp(pci_address_name, pciaddname)) {
1254 1255 1256
				long num_crtc;
				int res = -1;

1257
				adev->enable_virtual_display = true;
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271

				if (pciaddname_tmp)
					res = kstrtol(pciaddname_tmp, 10,
						      &num_crtc);

				if (!res) {
					if (num_crtc < 1)
						num_crtc = 1;
					if (num_crtc > 6)
						num_crtc = 6;
					adev->mode_info.num_crtc = num_crtc;
				} else {
					adev->mode_info.num_crtc = 1;
				}
1272 1273 1274 1275
				break;
			}
		}

1276 1277 1278
		DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
			 amdgpu_virtual_display, pci_address_name,
			 adev->enable_virtual_display, adev->mode_info.num_crtc);
1279 1280 1281 1282 1283

		kfree(pciaddstr);
	}
}

1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
/**
 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
 *
 * @adev: amdgpu_device pointer
 *
 * Parses the asic configuration parameters specified in the gpu info
 * firmware and makes them availale to the driver for use in configuring
 * the asic.
 * Returns 0 on success, -EINVAL on failure.
 */
1294 1295 1296 1297 1298 1299 1300
static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
{
	const char *chip_name;
	char fw_name[30];
	int err;
	const struct gpu_info_firmware_header_v1_0 *hdr;

1301 1302
	adev->firmware.gpu_info_fw = NULL;

1303 1304 1305 1306 1307
	switch (adev->asic_type) {
	case CHIP_TOPAZ:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_POLARIS10:
1308
	case CHIP_POLARIS11:
1309
	case CHIP_POLARIS12:
1310
	case CHIP_VEGAM:
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
	case CHIP_CARRIZO:
	case CHIP_STONEY:
#ifdef CONFIG_DRM_AMDGPU_SI
	case CHIP_VERDE:
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_OLAND:
	case CHIP_HAINAN:
#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
#endif
1327
	case CHIP_VEGA20:
1328 1329 1330 1331 1332
	default:
		return 0;
	case CHIP_VEGA10:
		chip_name = "vega10";
		break;
1333 1334 1335
	case CHIP_VEGA12:
		chip_name = "vega12";
		break;
1336
	case CHIP_RAVEN:
1337 1338
		if (adev->rev_id >= 8)
			chip_name = "raven2";
1339 1340
		else if (adev->pdev->device == 0x15d8)
			chip_name = "picasso";
1341 1342
		else
			chip_name = "raven";
1343
		break;
1344 1345 1346
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1347
	err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1348 1349 1350 1351 1352 1353
	if (err) {
		dev_err(adev->dev,
			"Failed to load gpu_info firmware \"%s\"\n",
			fw_name);
		goto out;
	}
1354
	err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1355 1356 1357 1358 1359 1360 1361
	if (err) {
		dev_err(adev->dev,
			"Failed to validate gpu_info firmware \"%s\"\n",
			fw_name);
		goto out;
	}

1362
	hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1363 1364 1365 1366 1367 1368
	amdgpu_ucode_print_gpu_info_hdr(&hdr->header);

	switch (hdr->version_major) {
	case 1:
	{
		const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1369
			(const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1370 1371
								le32_to_cpu(hdr->header.ucode_array_offset_bytes));

1372 1373 1374 1375
		adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
		adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
		adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
		adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1376
		adev->gfx.config.max_texture_channel_caches =
1377 1378 1379 1380 1381
			le32_to_cpu(gpu_info_fw->gc_num_tccs);
		adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
		adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
		adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
		adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1382
		adev->gfx.config.double_offchip_lds_buf =
1383 1384
			le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
		adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1385 1386 1387 1388 1389
		adev->gfx.cu_info.max_waves_per_simd =
			le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
		adev->gfx.cu_info.max_scratch_slots_per_cu =
			le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
		adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
		break;
	}
	default:
		dev_err(adev->dev,
			"Unsupported gpu_info table %d\n", hdr->header.ucode_version);
		err = -EINVAL;
		goto out;
	}
out:
	return err;
}

1402 1403 1404 1405 1406 1407 1408 1409 1410 1411
/**
 * amdgpu_device_ip_early_init - run early init for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Early initialization pass for hardware IPs.  The hardware IPs that make
 * up each asic are discovered each IP's early_init callback is run.  This
 * is the first stage in initializing the asic.
 * Returns 0 on success, negative error code on failure.
 */
1412
static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1413
{
1414
	int i, r;
A
Alex Deucher 已提交
1415

1416
	amdgpu_device_enable_virtual_display(adev);
1417

A
Alex Deucher 已提交
1418
	switch (adev->asic_type) {
1419 1420
	case CHIP_TOPAZ:
	case CHIP_TONGA:
1421
	case CHIP_FIJI:
1422
	case CHIP_POLARIS10:
1423
	case CHIP_POLARIS11:
1424
	case CHIP_POLARIS12:
1425
	case CHIP_VEGAM:
1426
	case CHIP_CARRIZO:
1427 1428
	case CHIP_STONEY:
		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1429 1430 1431 1432 1433 1434 1435 1436
			adev->family = AMDGPU_FAMILY_CZ;
		else
			adev->family = AMDGPU_FAMILY_VI;

		r = vi_set_ip_blocks(adev);
		if (r)
			return r;
		break;
K
Ken Wang 已提交
1437 1438 1439 1440 1441 1442
#ifdef CONFIG_DRM_AMDGPU_SI
	case CHIP_VERDE:
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_OLAND:
	case CHIP_HAINAN:
K
Ken Wang 已提交
1443
		adev->family = AMDGPU_FAMILY_SI;
K
Ken Wang 已提交
1444 1445 1446 1447 1448
		r = si_set_ip_blocks(adev);
		if (r)
			return r;
		break;
#endif
1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
		if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
			adev->family = AMDGPU_FAMILY_CI;
		else
			adev->family = AMDGPU_FAMILY_KV;

		r = cik_set_ip_blocks(adev);
		if (r)
			return r;
		break;
#endif
1465 1466
	case CHIP_VEGA10:
	case CHIP_VEGA12:
1467
	case CHIP_VEGA20:
1468
	case CHIP_RAVEN:
1469
		if (adev->asic_type == CHIP_RAVEN)
1470 1471 1472
			adev->family = AMDGPU_FAMILY_RV;
		else
			adev->family = AMDGPU_FAMILY_AI;
1473 1474 1475 1476 1477

		r = soc15_set_ip_blocks(adev);
		if (r)
			return r;
		break;
A
Alex Deucher 已提交
1478 1479 1480 1481 1482
	default:
		/* FIXME: not supported yet */
		return -EINVAL;
	}

1483 1484 1485 1486
	r = amdgpu_device_parse_gpu_info_fw(adev);
	if (r)
		return r;

1487 1488
	amdgpu_amdkfd_device_probe(adev);

1489 1490 1491
	if (amdgpu_sriov_vf(adev)) {
		r = amdgpu_virt_request_full_gpu(adev, true);
		if (r)
1492
			return -EAGAIN;
1493 1494
	}

1495
	adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1496 1497
	if (amdgpu_sriov_vf(adev))
		adev->powerplay.pp_feature &= ~PP_GFXOFF_MASK;
1498

A
Alex Deucher 已提交
1499 1500
	for (i = 0; i < adev->num_ip_blocks; i++) {
		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1501 1502
			DRM_ERROR("disabled ip block: %d <%s>\n",
				  i, adev->ip_blocks[i].version->funcs->name);
1503
			adev->ip_blocks[i].status.valid = false;
A
Alex Deucher 已提交
1504
		} else {
1505 1506
			if (adev->ip_blocks[i].version->funcs->early_init) {
				r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1507
				if (r == -ENOENT) {
1508
					adev->ip_blocks[i].status.valid = false;
1509
				} else if (r) {
1510 1511
					DRM_ERROR("early_init of IP block <%s> failed %d\n",
						  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1512
					return r;
1513
				} else {
1514
					adev->ip_blocks[i].status.valid = true;
1515
				}
1516
			} else {
1517
				adev->ip_blocks[i].status.valid = true;
A
Alex Deucher 已提交
1518 1519 1520 1521
			}
		}
	}

1522 1523 1524
	adev->cg_flags &= amdgpu_cg_mask;
	adev->pg_flags &= amdgpu_pg_mask;

A
Alex Deucher 已提交
1525 1526 1527
	return 0;
}

1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
/**
 * amdgpu_device_ip_init - run init for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Main initialization pass for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
 * are run.  sw_init initializes the software state associated with each IP
 * and hw_init initializes the hardware associated with each IP.
 * Returns 0 on success, negative error code on failure.
 */
1539
static int amdgpu_device_ip_init(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1540 1541 1542 1543
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1544
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
1545
			continue;
1546
		r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1547
		if (r) {
1548 1549
			DRM_ERROR("sw_init of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1550
			return r;
1551
		}
1552
		adev->ip_blocks[i].status.sw = true;
1553

A
Alex Deucher 已提交
1554
		/* need to do gmc hw init early so we can allocate gpu mem */
1555
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1556
			r = amdgpu_device_vram_scratch_init(adev);
1557 1558
			if (r) {
				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
A
Alex Deucher 已提交
1559
				return r;
1560
			}
1561
			r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1562 1563
			if (r) {
				DRM_ERROR("hw_init %d failed %d\n", i, r);
A
Alex Deucher 已提交
1564
				return r;
1565
			}
1566
			r = amdgpu_device_wb_init(adev);
1567
			if (r) {
1568
				DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
A
Alex Deucher 已提交
1569
				return r;
1570
			}
1571
			adev->ip_blocks[i].status.hw = true;
M
Monk Liu 已提交
1572 1573 1574 1575 1576 1577 1578 1579 1580

			/* right after GMC hw init, we create CSA */
			if (amdgpu_sriov_vf(adev)) {
				r = amdgpu_allocate_static_csa(adev);
				if (r) {
					DRM_ERROR("allocate CSA failed %d\n", r);
					return r;
				}
			}
A
Alex Deucher 已提交
1581 1582 1583
		}
	}

1584 1585 1586
	r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
	if (r)
		return r;
A
Alex Deucher 已提交
1587
	for (i = 0; i < adev->num_ip_blocks; i++) {
1588
		if (!adev->ip_blocks[i].status.sw)
A
Alex Deucher 已提交
1589
			continue;
1590
		if (adev->ip_blocks[i].status.hw)
A
Alex Deucher 已提交
1591
			continue;
1592
		r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1593
		if (r) {
1594 1595
			DRM_ERROR("hw_init of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1596
			return r;
1597
		}
1598
		adev->ip_blocks[i].status.hw = true;
A
Alex Deucher 已提交
1599 1600
	}

1601
	amdgpu_xgmi_add_device(adev);
1602
	amdgpu_amdkfd_device_init(adev);
1603 1604 1605 1606

	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_release_full_gpu(adev, true);

A
Alex Deucher 已提交
1607 1608 1609
	return 0;
}

1610 1611 1612 1613 1614 1615 1616 1617 1618
/**
 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
 *
 * @adev: amdgpu_device pointer
 *
 * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
 * this function before a GPU reset.  If the value is retained after a
 * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
 */
1619
static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1620 1621 1622 1623
{
	memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
}

1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
/**
 * amdgpu_device_check_vram_lost - check if vram is valid
 *
 * @adev: amdgpu_device pointer
 *
 * Checks the reset magic value written to the gart pointer in VRAM.
 * The driver calls this after a GPU reset to see if the contents of
 * VRAM is lost or now.
 * returns true if vram is lost, false if not.
 */
1634
static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1635 1636 1637 1638 1639
{
	return !!memcmp(adev->gart.ptr, adev->reset_magic,
			AMDGPU_RESET_MAGIC_NUM);
}

1640
/**
1641
 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1642 1643 1644 1645
 *
 * @adev: amdgpu_device pointer
 *
 * The list of all the hardware IPs that make up the asic is walked and the
1646 1647 1648
 * set_clockgating_state callbacks are run.
 * Late initialization pass enabling clockgating for hardware IPs.
 * Fini or suspend, pass disabling clockgating for hardware IPs.
1649 1650
 * Returns 0 on success, negative error code on failure.
 */
1651

1652 1653
static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
						enum amd_clockgating_state state)
A
Alex Deucher 已提交
1654
{
1655
	int i, j, r;
A
Alex Deucher 已提交
1656

1657 1658 1659
	if (amdgpu_emu_mode == 1)
		return 0;

1660 1661
	for (j = 0; j < adev->num_ip_blocks; j++) {
		i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1662
		if (!adev->ip_blocks[i].status.late_initialized)
A
Alex Deucher 已提交
1663
			continue;
1664
		/* skip CG for VCE/UVD, it's handled specially */
1665
		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1666
		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1667
		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1668
		    adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1669
			/* enable clockgating to save power */
1670
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1671
										     state);
1672 1673
			if (r) {
				DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1674
					  adev->ip_blocks[i].version->funcs->name, r);
1675 1676
				return r;
			}
1677
		}
A
Alex Deucher 已提交
1678
	}
1679

1680 1681 1682
	return 0;
}

1683
static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1684
{
1685
	int i, j, r;
1686

1687 1688 1689
	if (amdgpu_emu_mode == 1)
		return 0;

1690 1691
	for (j = 0; j < adev->num_ip_blocks; j++) {
		i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1692
		if (!adev->ip_blocks[i].status.late_initialized)
1693 1694 1695 1696 1697 1698 1699 1700
			continue;
		/* skip CG for VCE/UVD, it's handled specially */
		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
		    adev->ip_blocks[i].version->funcs->set_powergating_state) {
			/* enable powergating to save power */
			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1701
											state);
1702 1703 1704 1705 1706 1707 1708
			if (r) {
				DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
		}
	}
1709 1710 1711
	return 0;
}

1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
/**
 * amdgpu_device_ip_late_init - run late init for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Late initialization pass for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked and the late_init callbacks are run.
 * late_init covers any special initialization that an IP requires
 * after all of the have been initialized or something that needs to happen
 * late in the init process.
 * Returns 0 on success, negative error code on failure.
 */
1724
static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1725 1726 1727 1728
{
	int i = 0, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1729
		if (!adev->ip_blocks[i].status.hw)
1730 1731 1732 1733 1734 1735 1736 1737 1738
			continue;
		if (adev->ip_blocks[i].version->funcs->late_init) {
			r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
			if (r) {
				DRM_ERROR("late_init of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
		}
1739
		adev->ip_blocks[i].status.late_initialized = true;
1740 1741
	}

1742 1743
	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1744

1745 1746
	queue_delayed_work(system_wq, &adev->late_init_work,
			   msecs_to_jiffies(AMDGPU_RESUME_MS));
A
Alex Deucher 已提交
1747

1748
	amdgpu_device_fill_reset_magic(adev);
A
Alex Deucher 已提交
1749 1750 1751 1752

	return 0;
}

1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
/**
 * amdgpu_device_ip_fini - run fini for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Main teardown pass for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
 * are run.  hw_fini tears down the hardware associated with each IP
 * and sw_fini tears down any software state associated with each IP.
 * Returns 0 on success, negative error code on failure.
 */
1764
static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1765 1766 1767
{
	int i, r;

1768
	amdgpu_amdkfd_device_fini(adev);
1769 1770

	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1771 1772
	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);

1773 1774
	/* need to disable SMC first */
	for (i = 0; i < adev->num_ip_blocks; i++) {
1775
		if (!adev->ip_blocks[i].status.hw)
1776
			continue;
1777
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1778
			r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1779 1780 1781
			/* XXX handle errors */
			if (r) {
				DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1782
					  adev->ip_blocks[i].version->funcs->name, r);
1783
			}
1784
			adev->ip_blocks[i].status.hw = false;
1785 1786 1787 1788
			break;
		}
	}

A
Alex Deucher 已提交
1789
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1790
		if (!adev->ip_blocks[i].status.hw)
A
Alex Deucher 已提交
1791
			continue;
1792

1793
		r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
A
Alex Deucher 已提交
1794
		/* XXX handle errors */
1795
		if (r) {
1796 1797
			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1798
		}
1799

1800
		adev->ip_blocks[i].status.hw = false;
A
Alex Deucher 已提交
1801 1802
	}

1803

A
Alex Deucher 已提交
1804
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1805
		if (!adev->ip_blocks[i].status.sw)
A
Alex Deucher 已提交
1806
			continue;
1807 1808

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1809
			amdgpu_ucode_free_bo(adev);
1810 1811 1812 1813 1814
			amdgpu_free_static_csa(adev);
			amdgpu_device_wb_fini(adev);
			amdgpu_device_vram_scratch_fini(adev);
		}

1815
		r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
A
Alex Deucher 已提交
1816
		/* XXX handle errors */
1817
		if (r) {
1818 1819
			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1820
		}
1821 1822
		adev->ip_blocks[i].status.sw = false;
		adev->ip_blocks[i].status.valid = false;
A
Alex Deucher 已提交
1823 1824
	}

M
Monk Liu 已提交
1825
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1826
		if (!adev->ip_blocks[i].status.late_initialized)
1827
			continue;
1828 1829 1830
		if (adev->ip_blocks[i].version->funcs->late_fini)
			adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
		adev->ip_blocks[i].status.late_initialized = false;
M
Monk Liu 已提交
1831 1832
	}

1833
	if (amdgpu_sriov_vf(adev))
1834 1835
		if (amdgpu_virt_release_full_gpu(adev, false))
			DRM_ERROR("failed to release exclusive mode on fini\n");
M
Monk Liu 已提交
1836

A
Alex Deucher 已提交
1837 1838 1839
	return 0;
}

1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
static int amdgpu_device_enable_mgpu_fan_boost(void)
{
	struct amdgpu_gpu_instance *gpu_ins;
	struct amdgpu_device *adev;
	int i, ret = 0;

	mutex_lock(&mgpu_info.mutex);

	/*
	 * MGPU fan boost feature should be enabled
	 * only when there are two or more dGPUs in
	 * the system
	 */
	if (mgpu_info.num_dgpu < 2)
		goto out;

	for (i = 0; i < mgpu_info.num_dgpu; i++) {
		gpu_ins = &(mgpu_info.gpu_ins[i]);
		adev = gpu_ins->adev;
		if (!(adev->flags & AMD_IS_APU) &&
		    !gpu_ins->mgpu_fan_enabled &&
		    adev->powerplay.pp_funcs &&
		    adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
			ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
			if (ret)
				break;

			gpu_ins->mgpu_fan_enabled = 1;
		}
	}

out:
	mutex_unlock(&mgpu_info.mutex);

	return ret;
}

1877
/**
1878
 * amdgpu_device_ip_late_init_func_handler - work handler for ib test
1879
 *
1880
 * @work: work_struct.
1881
 */
1882
static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1883 1884 1885
{
	struct amdgpu_device *adev =
		container_of(work, struct amdgpu_device, late_init_work.work);
1886 1887 1888 1889 1890
	int r;

	r = amdgpu_ib_ring_tests(adev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);
1891 1892 1893 1894

	r = amdgpu_device_enable_mgpu_fan_boost();
	if (r)
		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
1895 1896
}

1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
{
	struct amdgpu_device *adev =
		container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);

	mutex_lock(&adev->gfx.gfx_off_mutex);
	if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
		if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
			adev->gfx.gfx_off_state = true;
	}
	mutex_unlock(&adev->gfx.gfx_off_mutex);
}

1910
/**
1911
 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
1912 1913 1914 1915 1916 1917 1918 1919 1920
 *
 * @adev: amdgpu_device pointer
 *
 * Main suspend function for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked, clockgating is disabled and the
 * suspend callbacks are run.  suspend puts the hardware and software state
 * in each IP into a state suitable for suspend.
 * Returns 0 on success, negative error code on failure.
 */
1921 1922 1923 1924
static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
{
	int i, r;

1925
	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1926
	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1927

1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		/* displays are handled separately */
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
			/* XXX handle errors */
			r = adev->ip_blocks[i].version->funcs->suspend(adev);
			/* XXX handle errors */
			if (r) {
				DRM_ERROR("suspend of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
			}
		}
	}

	return 0;
}

/**
 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
 *
 * @adev: amdgpu_device pointer
 *
 * Main suspend function for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked, clockgating is disabled and the
 * suspend callbacks are run.  suspend puts the hardware and software state
 * in each IP into a state suitable for suspend.
 * Returns 0 on success, negative error code on failure.
 */
static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1958 1959 1960 1961
{
	int i, r;

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1962
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
1963
			continue;
1964 1965 1966
		/* displays are handled in phase1 */
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
			continue;
A
Alex Deucher 已提交
1967
		/* XXX handle errors */
1968
		r = adev->ip_blocks[i].version->funcs->suspend(adev);
A
Alex Deucher 已提交
1969
		/* XXX handle errors */
1970
		if (r) {
1971 1972
			DRM_ERROR("suspend of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1973
		}
A
Alex Deucher 已提交
1974 1975 1976 1977 1978
	}

	return 0;
}

1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993
/**
 * amdgpu_device_ip_suspend - run suspend for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Main suspend function for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked, clockgating is disabled and the
 * suspend callbacks are run.  suspend puts the hardware and software state
 * in each IP into a state suitable for suspend.
 * Returns 0 on success, negative error code on failure.
 */
int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
{
	int r;

1994 1995 1996
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_request_full_gpu(adev, false);

1997 1998 1999 2000 2001
	r = amdgpu_device_ip_suspend_phase1(adev);
	if (r)
		return r;
	r = amdgpu_device_ip_suspend_phase2(adev);

2002 2003 2004
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_release_full_gpu(adev, false);

2005 2006 2007
	return r;
}

2008
static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2009 2010 2011
{
	int i, r;

2012 2013 2014
	static enum amd_ip_block_type ip_order[] = {
		AMD_IP_BLOCK_TYPE_GMC,
		AMD_IP_BLOCK_TYPE_COMMON,
2015
		AMD_IP_BLOCK_TYPE_PSP,
2016 2017
		AMD_IP_BLOCK_TYPE_IH,
	};
2018

2019 2020 2021
	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
		int j;
		struct amdgpu_ip_block *block;
2022

2023 2024 2025 2026 2027 2028 2029 2030
		for (j = 0; j < adev->num_ip_blocks; j++) {
			block = &adev->ip_blocks[j];

			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				continue;

			r = block->version->funcs->hw_init(adev);
2031
			DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2032 2033
			if (r)
				return r;
2034 2035 2036 2037 2038 2039
		}
	}

	return 0;
}

2040
static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2041 2042 2043
{
	int i, r;

2044 2045 2046 2047 2048
	static enum amd_ip_block_type ip_order[] = {
		AMD_IP_BLOCK_TYPE_SMC,
		AMD_IP_BLOCK_TYPE_DCE,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_IP_BLOCK_TYPE_SDMA,
2049 2050
		AMD_IP_BLOCK_TYPE_UVD,
		AMD_IP_BLOCK_TYPE_VCE
2051
	};
2052

2053 2054 2055
	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
		int j;
		struct amdgpu_ip_block *block;
2056

2057 2058 2059 2060 2061 2062 2063 2064
		for (j = 0; j < adev->num_ip_blocks; j++) {
			block = &adev->ip_blocks[j];

			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				continue;

			r = block->version->funcs->hw_init(adev);
2065
			DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2066 2067
			if (r)
				return r;
2068 2069 2070 2071 2072 2073
		}
	}

	return 0;
}

2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085
/**
 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * First resume function for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked and the resume callbacks are run for
 * COMMON, GMC, and IH.  resume puts the hardware into a functional state
 * after a suspend and updates the software state as necessary.  This
 * function is also used for restoring the GPU after a GPU reset.
 * Returns 0 on success, negative error code on failure.
 */
2086
static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
A
Alex Deucher 已提交
2087 2088 2089
{
	int i, r;

2090 2091 2092 2093
	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2094 2095
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2096 2097 2098 2099 2100 2101
			r = adev->ip_blocks[i].version->funcs->resume(adev);
			if (r) {
				DRM_ERROR("resume of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
2102 2103 2104 2105 2106 2107
		}
	}

	return 0;
}

2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
/**
 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * First resume function for hardware IPs.  The list of all the hardware
 * IPs that make up the asic is walked and the resume callbacks are run for
 * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
 * functional state after a suspend and updates the software state as
 * necessary.  This function is also used for restoring the GPU after a GPU
 * reset.
 * Returns 0 on success, negative error code on failure.
 */
2121
static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
A
Alex Deucher 已提交
2122 2123 2124 2125
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2126
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
2127
			continue;
2128
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2129 2130
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
2131
			continue;
2132
		r = adev->ip_blocks[i].version->funcs->resume(adev);
2133
		if (r) {
2134 2135
			DRM_ERROR("resume of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
2136
			return r;
2137
		}
A
Alex Deucher 已提交
2138 2139 2140 2141 2142
	}

	return 0;
}

2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
/**
 * amdgpu_device_ip_resume - run resume for hardware IPs
 *
 * @adev: amdgpu_device pointer
 *
 * Main resume function for hardware IPs.  The hardware IPs
 * are split into two resume functions because they are
 * are also used in in recovering from a GPU reset and some additional
 * steps need to be take between them.  In this case (S3/S4) they are
 * run sequentially.
 * Returns 0 on success, negative error code on failure.
 */
2155
static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2156 2157 2158
{
	int r;

2159
	r = amdgpu_device_ip_resume_phase1(adev);
2160 2161
	if (r)
		return r;
2162
	r = amdgpu_device_ip_resume_phase2(adev);
2163 2164 2165 2166

	return r;
}

2167 2168 2169 2170 2171 2172 2173
/**
 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
 *
 * @adev: amdgpu_device pointer
 *
 * Query the VBIOS data tables to determine if the board supports SR-IOV.
 */
2174
static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2175
{
M
Monk Liu 已提交
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
	if (amdgpu_sriov_vf(adev)) {
		if (adev->is_atom_fw) {
			if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
		} else {
			if (amdgpu_atombios_has_gpu_virtualization_table(adev))
				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
		}

		if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2187
	}
2188 2189
}

2190 2191 2192 2193 2194 2195 2196 2197
/**
 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
 *
 * @asic_type: AMD asic type
 *
 * Check if there is DC (new modesetting infrastructre) support for an asic.
 * returns true if DC has support, false if not.
 */
2198 2199 2200 2201 2202
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
{
	switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
	case CHIP_BONAIRE:
2203
	case CHIP_KAVERI:
2204 2205
	case CHIP_KABINI:
	case CHIP_MULLINS:
2206 2207 2208 2209 2210 2211 2212 2213 2214
		/*
		 * We have systems in the wild with these ASICs that require
		 * LVDS and VGA support which is not supported with DC.
		 *
		 * Fallback to the non-DC driver here by default so as not to
		 * cause regressions.
		 */
		return amdgpu_dc > 0;
	case CHIP_HAWAII:
2215 2216 2217
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS10:
L
Leo Liu 已提交
2218
	case CHIP_POLARIS11:
2219
	case CHIP_POLARIS12:
L
Leo Liu 已提交
2220
	case CHIP_VEGAM:
2221 2222
	case CHIP_TONGA:
	case CHIP_FIJI:
2223
	case CHIP_VEGA10:
2224
	case CHIP_VEGA12:
2225
	case CHIP_VEGA20:
2226
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2227
	case CHIP_RAVEN:
2228
#endif
2229
		return amdgpu_dc != 0;
2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244
#endif
	default:
		return false;
	}
}

/**
 * amdgpu_device_has_dc_support - check if dc is supported
 *
 * @adev: amdgpu_device_pointer
 *
 * Returns true for supported, false for not supported
 */
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
{
X
Xiangliang Yu 已提交
2245 2246 2247
	if (amdgpu_sriov_vf(adev))
		return false;

2248 2249 2250
	return amdgpu_device_asic_has_dc_support(adev->asic_type);
}

A
Alex Deucher 已提交
2251 2252 2253 2254
/**
 * amdgpu_device_init - initialize the driver
 *
 * @adev: amdgpu_device pointer
2255
 * @ddev: drm dev pointer
A
Alex Deucher 已提交
2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
 * @pdev: pci dev pointer
 * @flags: driver flags
 *
 * Initializes the driver info and hw (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver startup.
 */
int amdgpu_device_init(struct amdgpu_device *adev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags)
{
	int r, i;
	bool runtime = false;
2270
	u32 max_MBps;
A
Alex Deucher 已提交
2271 2272 2273 2274 2275 2276

	adev->shutdown = false;
	adev->dev = &pdev->dev;
	adev->ddev = ddev;
	adev->pdev = pdev;
	adev->flags = flags;
2277
	adev->asic_type = flags & AMD_ASIC_MASK;
A
Alex Deucher 已提交
2278
	adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2279 2280
	if (amdgpu_emu_mode == 1)
		adev->usec_timeout *= 2;
2281
	adev->gmc.gart_size = 512 * 1024 * 1024;
A
Alex Deucher 已提交
2282 2283 2284 2285 2286
	adev->accel_working = false;
	adev->num_rings = 0;
	adev->mman.buffer_funcs = NULL;
	adev->mman.buffer_funcs_ring = NULL;
	adev->vm_manager.vm_pte_funcs = NULL;
2287
	adev->vm_manager.vm_pte_num_rqs = 0;
2288
	adev->gmc.gmc_funcs = NULL;
2289
	adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2290
	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
A
Alex Deucher 已提交
2291 2292 2293 2294 2295

	adev->smc_rreg = &amdgpu_invalid_rreg;
	adev->smc_wreg = &amdgpu_invalid_wreg;
	adev->pcie_rreg = &amdgpu_invalid_rreg;
	adev->pcie_wreg = &amdgpu_invalid_wreg;
2296 2297
	adev->pciep_rreg = &amdgpu_invalid_rreg;
	adev->pciep_wreg = &amdgpu_invalid_wreg;
A
Alex Deucher 已提交
2298 2299 2300 2301
	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
	adev->didt_rreg = &amdgpu_invalid_rreg;
	adev->didt_wreg = &amdgpu_invalid_wreg;
2302 2303
	adev->gc_cac_rreg = &amdgpu_invalid_rreg;
	adev->gc_cac_wreg = &amdgpu_invalid_wreg;
A
Alex Deucher 已提交
2304 2305 2306
	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;

2307 2308 2309
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
		 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
A
Alex Deucher 已提交
2310 2311 2312 2313

	/* mutex initialization are all done here so we
	 * can recall function without having locking issues */
	atomic_set(&adev->irq.ih.lock, 0);
2314
	mutex_init(&adev->firmware.mutex);
A
Alex Deucher 已提交
2315 2316 2317
	mutex_init(&adev->pm.mutex);
	mutex_init(&adev->gfx.gpu_clock_mutex);
	mutex_init(&adev->srbm_mutex);
2318
	mutex_init(&adev->gfx.pipe_reserve_mutex);
2319
	mutex_init(&adev->gfx.gfx_off_mutex);
A
Alex Deucher 已提交
2320 2321
	mutex_init(&adev->grbm_idx_mutex);
	mutex_init(&adev->mn_lock);
A
Alex Deucher 已提交
2322
	mutex_init(&adev->virt.vf_errors.lock);
A
Alex Deucher 已提交
2323
	hash_init(adev->mn_hash);
2324
	mutex_init(&adev->lock_reset);
A
Alex Deucher 已提交
2325

2326
	amdgpu_device_check_arguments(adev);
A
Alex Deucher 已提交
2327 2328 2329 2330 2331 2332

	spin_lock_init(&adev->mmio_idx_lock);
	spin_lock_init(&adev->smc_idx_lock);
	spin_lock_init(&adev->pcie_idx_lock);
	spin_lock_init(&adev->uvd_ctx_idx_lock);
	spin_lock_init(&adev->didt_idx_lock);
2333
	spin_lock_init(&adev->gc_cac_idx_lock);
2334
	spin_lock_init(&adev->se_cac_idx_lock);
A
Alex Deucher 已提交
2335
	spin_lock_init(&adev->audio_endpt_idx_lock);
2336
	spin_lock_init(&adev->mm_stats.lock);
A
Alex Deucher 已提交
2337

2338 2339 2340
	INIT_LIST_HEAD(&adev->shadow_list);
	mutex_init(&adev->shadow_list_lock);

2341 2342 2343
	INIT_LIST_HEAD(&adev->ring_lru_list);
	spin_lock_init(&adev->ring_lru_list_lock);

2344 2345
	INIT_DELAYED_WORK(&adev->late_init_work,
			  amdgpu_device_ip_late_init_func_handler);
2346 2347
	INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
			  amdgpu_device_delay_enable_gfx_off);
2348

2349
	adev->gfx.gfx_off_req_count = 1;
2350 2351
	adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;

2352 2353
	/* Registers mapping */
	/* TODO: block userspace mapping of io register */
2354 2355 2356 2357 2358 2359 2360
	if (adev->asic_type >= CHIP_BONAIRE) {
		adev->rmmio_base = pci_resource_start(adev->pdev, 5);
		adev->rmmio_size = pci_resource_len(adev->pdev, 5);
	} else {
		adev->rmmio_base = pci_resource_start(adev->pdev, 2);
		adev->rmmio_size = pci_resource_len(adev->pdev, 2);
	}
A
Alex Deucher 已提交
2361 2362 2363 2364 2365 2366 2367 2368

	adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
	if (adev->rmmio == NULL) {
		return -ENOMEM;
	}
	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
	DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);

2369
	/* doorbell bar mapping */
2370
	amdgpu_device_doorbell_init(adev);
A
Alex Deucher 已提交
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380

	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
			adev->rio_mem_size = pci_resource_len(adev->pdev, i);
			adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
			break;
		}
	}
	if (adev->rio_mem == NULL)
2381
		DRM_INFO("PCI I/O BAR is not found.\n");
A
Alex Deucher 已提交
2382

2383 2384
	amdgpu_device_get_pcie_info(adev);

A
Alex Deucher 已提交
2385
	/* early init functions */
2386
	r = amdgpu_device_ip_early_init(adev);
A
Alex Deucher 已提交
2387 2388 2389 2390 2391 2392
	if (r)
		return r;

	/* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
	/* this will fail for cards that aren't VGA class devices, just
	 * ignore it */
2393
	vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
A
Alex Deucher 已提交
2394

2395
	if (amdgpu_device_is_px(ddev))
A
Alex Deucher 已提交
2396
		runtime = true;
2397 2398 2399
	if (!pci_is_thunderbolt_attached(adev->pdev))
		vga_switcheroo_register_client(adev->pdev,
					       &amdgpu_switcheroo_ops, runtime);
A
Alex Deucher 已提交
2400 2401 2402
	if (runtime)
		vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);

2403 2404 2405
	if (amdgpu_emu_mode == 1) {
		/* post the asic on emulation mode */
		emu_soc_asic_init(adev);
2406
		goto fence_driver_init;
2407
	}
2408

A
Alex Deucher 已提交
2409
	/* Read BIOS */
2410 2411 2412 2413
	if (!amdgpu_get_bios(adev)) {
		r = -EINVAL;
		goto failed;
	}
2414

A
Alex Deucher 已提交
2415
	r = amdgpu_atombios_init(adev);
2416 2417
	if (r) {
		dev_err(adev->dev, "amdgpu_atombios_init failed\n");
A
Alex Deucher 已提交
2418
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2419
		goto failed;
2420
	}
A
Alex Deucher 已提交
2421

2422 2423
	/* detect if we are with an SRIOV vbios */
	amdgpu_device_detect_sriov_bios(adev);
2424

A
Alex Deucher 已提交
2425
	/* Post card if necessary */
A
Alex Deucher 已提交
2426
	if (amdgpu_device_need_post(adev)) {
A
Alex Deucher 已提交
2427
		if (!adev->bios) {
2428
			dev_err(adev->dev, "no vBIOS found\n");
2429 2430
			r = -EINVAL;
			goto failed;
A
Alex Deucher 已提交
2431
		}
2432
		DRM_INFO("GPU posting now...\n");
2433 2434 2435 2436 2437
		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
		if (r) {
			dev_err(adev->dev, "gpu post error!\n");
			goto failed;
		}
A
Alex Deucher 已提交
2438 2439
	}

2440 2441 2442 2443 2444
	if (adev->is_atom_fw) {
		/* Initialize clocks */
		r = amdgpu_atomfirmware_get_clock_info(adev);
		if (r) {
			dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
A
Alex Deucher 已提交
2445
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2446 2447 2448
			goto failed;
		}
	} else {
2449 2450 2451 2452
		/* Initialize clocks */
		r = amdgpu_atombios_get_clock_info(adev);
		if (r) {
			dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
A
Alex Deucher 已提交
2453
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2454
			goto failed;
2455 2456
		}
		/* init i2c buses */
2457 2458
		if (!amdgpu_device_has_dc_support(adev))
			amdgpu_atombios_i2c_init(adev);
2459
	}
A
Alex Deucher 已提交
2460

2461
fence_driver_init:
A
Alex Deucher 已提交
2462 2463
	/* Fence driver */
	r = amdgpu_fence_driver_init(adev);
2464 2465
	if (r) {
		dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
A
Alex Deucher 已提交
2466
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2467
		goto failed;
2468
	}
A
Alex Deucher 已提交
2469 2470 2471 2472

	/* init the mode config */
	drm_mode_config_init(adev->ddev);

2473
	r = amdgpu_device_ip_init(adev);
A
Alex Deucher 已提交
2474
	if (r) {
2475 2476 2477 2478 2479 2480
		/* failed in exclusive mode due to timeout */
		if (amdgpu_sriov_vf(adev) &&
		    !amdgpu_sriov_runtime(adev) &&
		    amdgpu_virt_mmio_blocked(adev) &&
		    !amdgpu_virt_wait_reset(adev)) {
			dev_err(adev->dev, "VF exclusive mode timeout\n");
2481 2482 2483
			/* Don't send request since VF is inactive. */
			adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
			adev->virt.ops = NULL;
2484 2485 2486
			r = -EAGAIN;
			goto failed;
		}
2487
		dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
A
Alex Deucher 已提交
2488
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2489
		goto failed;
A
Alex Deucher 已提交
2490 2491 2492 2493
	}

	adev->accel_working = true;

2494 2495
	amdgpu_vm_check_compute_bug(adev);

2496 2497 2498 2499 2500 2501 2502 2503
	/* Initialize the buffer migration limit. */
	if (amdgpu_moverate >= 0)
		max_MBps = amdgpu_moverate;
	else
		max_MBps = 8; /* Allow 8 MB/s. */
	/* Get a log2 for easy divisions. */
	adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));

A
Alex Deucher 已提交
2504 2505 2506
	r = amdgpu_ib_pool_init(adev);
	if (r) {
		dev_err(adev->dev, "IB initialization failed (%d).\n", r);
A
Alex Deucher 已提交
2507
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2508
		goto failed;
A
Alex Deucher 已提交
2509 2510
	}

2511 2512 2513
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_init_data_exchange(adev);

2514 2515
	amdgpu_fbdev_init(adev);

2516 2517 2518 2519
	r = amdgpu_pm_sysfs_init(adev);
	if (r)
		DRM_ERROR("registering pm debugfs failed (%d).\n", r);

2520
	r = amdgpu_debugfs_gem_init(adev);
M
Monk Liu 已提交
2521
	if (r)
A
Alex Deucher 已提交
2522 2523 2524
		DRM_ERROR("registering gem debugfs failed (%d).\n", r);

	r = amdgpu_debugfs_regs_init(adev);
M
Monk Liu 已提交
2525
	if (r)
A
Alex Deucher 已提交
2526 2527
		DRM_ERROR("registering register debugfs failed (%d).\n", r);

2528
	r = amdgpu_debugfs_firmware_init(adev);
M
Monk Liu 已提交
2529
	if (r)
2530 2531
		DRM_ERROR("registering firmware debugfs failed (%d).\n", r);

2532
	r = amdgpu_debugfs_init(adev);
2533
	if (r)
2534
		DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2535

A
Alex Deucher 已提交
2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551
	if ((amdgpu_testing & 1)) {
		if (adev->accel_working)
			amdgpu_test_moves(adev);
		else
			DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
	}
	if (amdgpu_benchmarking) {
		if (adev->accel_working)
			amdgpu_benchmark(adev, amdgpu_benchmarking);
		else
			DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
	}

	/* enable clockgating, etc. after ib tests, etc. since some blocks require
	 * explicit gating rather than handling it automatically.
	 */
2552
	r = amdgpu_device_ip_late_init(adev);
2553
	if (r) {
2554
		dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
A
Alex Deucher 已提交
2555
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2556
		goto failed;
2557
	}
A
Alex Deucher 已提交
2558 2559

	return 0;
2560 2561

failed:
2562
	amdgpu_vf_error_trans_all(adev);
2563 2564
	if (runtime)
		vga_switcheroo_fini_domain_pm_ops(adev->dev);
2565

2566
	return r;
A
Alex Deucher 已提交
2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582
}

/**
 * amdgpu_device_fini - tear down the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Tear down the driver info (all asics).
 * Called at driver shutdown.
 */
void amdgpu_device_fini(struct amdgpu_device *adev)
{
	int r;

	DRM_INFO("amdgpu: finishing device.\n");
	adev->shutdown = true;
2583 2584
	/* disable all interrupts */
	amdgpu_irq_disable_all(adev);
2585 2586 2587 2588 2589 2590
	if (adev->mode_info.mode_config_initialized){
		if (!amdgpu_device_has_dc_support(adev))
			drm_crtc_force_disable_all(adev->ddev);
		else
			drm_atomic_helper_shutdown(adev->ddev);
	}
A
Alex Deucher 已提交
2591 2592
	amdgpu_ib_pool_fini(adev);
	amdgpu_fence_driver_fini(adev);
2593
	amdgpu_pm_sysfs_fini(adev);
A
Alex Deucher 已提交
2594
	amdgpu_fbdev_fini(adev);
2595
	r = amdgpu_device_ip_fini(adev);
2596 2597 2598 2599
	if (adev->firmware.gpu_info_fw) {
		release_firmware(adev->firmware.gpu_info_fw);
		adev->firmware.gpu_info_fw = NULL;
	}
A
Alex Deucher 已提交
2600
	adev->accel_working = false;
2601
	cancel_delayed_work_sync(&adev->late_init_work);
A
Alex Deucher 已提交
2602
	/* free i2c buses */
2603 2604
	if (!amdgpu_device_has_dc_support(adev))
		amdgpu_i2c_fini(adev);
2605 2606 2607 2608

	if (amdgpu_emu_mode != 1)
		amdgpu_atombios_fini(adev);

A
Alex Deucher 已提交
2609 2610
	kfree(adev->bios);
	adev->bios = NULL;
2611 2612
	if (!pci_is_thunderbolt_attached(adev->pdev))
		vga_switcheroo_unregister_client(adev->pdev);
2613 2614
	if (adev->flags & AMD_IS_PX)
		vga_switcheroo_fini_domain_pm_ops(adev->dev);
A
Alex Deucher 已提交
2615 2616 2617 2618 2619 2620
	vga_client_register(adev->pdev, NULL, NULL, NULL);
	if (adev->rio_mem)
		pci_iounmap(adev->pdev, adev->rio_mem);
	adev->rio_mem = NULL;
	iounmap(adev->rmmio);
	adev->rmmio = NULL;
2621
	amdgpu_device_doorbell_fini(adev);
A
Alex Deucher 已提交
2622 2623 2624 2625 2626 2627 2628 2629
	amdgpu_debugfs_regs_cleanup(adev);
}


/*
 * Suspend & resume.
 */
/**
2630
 * amdgpu_device_suspend - initiate device suspend
A
Alex Deucher 已提交
2631
 *
2632 2633 2634
 * @dev: drm dev pointer
 * @suspend: suspend state
 * @fbcon : notify the fbdev of suspend
A
Alex Deucher 已提交
2635 2636 2637 2638 2639
 *
 * Puts the hw in the suspend state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver suspend.
 */
2640
int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
A
Alex Deucher 已提交
2641 2642 2643 2644
{
	struct amdgpu_device *adev;
	struct drm_crtc *crtc;
	struct drm_connector *connector;
2645
	int r;
A
Alex Deucher 已提交
2646 2647 2648 2649 2650 2651 2652 2653 2654 2655

	if (dev == NULL || dev->dev_private == NULL) {
		return -ENODEV;
	}

	adev = dev->dev_private;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

2656
	adev->in_suspend = true;
A
Alex Deucher 已提交
2657 2658
	drm_kms_helper_poll_disable(dev);

2659 2660 2661
	if (fbcon)
		amdgpu_fbdev_set_suspend(adev, 1);

2662 2663
	cancel_delayed_work_sync(&adev->late_init_work);

2664 2665 2666 2667 2668 2669 2670
	if (!amdgpu_device_has_dc_support(adev)) {
		/* turn off display hw */
		drm_modeset_lock_all(dev);
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
		}
		drm_modeset_unlock_all(dev);
2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683
			/* unpin the front buffers and cursors */
		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
			struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
			struct drm_framebuffer *fb = crtc->primary->fb;
			struct amdgpu_bo *robj;

			if (amdgpu_crtc->cursor_bo) {
				struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
				r = amdgpu_bo_reserve(aobj, true);
				if (r == 0) {
					amdgpu_bo_unpin(aobj);
					amdgpu_bo_unreserve(aobj);
				}
2684 2685
			}

2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696
			if (fb == NULL || fb->obj[0] == NULL) {
				continue;
			}
			robj = gem_to_amdgpu_bo(fb->obj[0]);
			/* don't unpin kernel fb objects */
			if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
				r = amdgpu_bo_reserve(robj, true);
				if (r == 0) {
					amdgpu_bo_unpin(robj);
					amdgpu_bo_unreserve(robj);
				}
A
Alex Deucher 已提交
2697 2698 2699
			}
		}
	}
2700 2701 2702 2703 2704

	amdgpu_amdkfd_suspend(adev);

	r = amdgpu_device_ip_suspend_phase1(adev);

A
Alex Deucher 已提交
2705 2706 2707
	/* evict vram memory */
	amdgpu_bo_evict_vram(adev);

2708
	amdgpu_fence_driver_suspend(adev);
A
Alex Deucher 已提交
2709

2710
	r = amdgpu_device_ip_suspend_phase2(adev);
A
Alex Deucher 已提交
2711

2712 2713 2714 2715
	/* evict remaining vram memory
	 * This second call to evict vram is to evict the gart page table
	 * using the CPU.
	 */
A
Alex Deucher 已提交
2716 2717 2718 2719 2720 2721 2722
	amdgpu_bo_evict_vram(adev);

	pci_save_state(dev->pdev);
	if (suspend) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
J
jimqu 已提交
2723 2724 2725 2726
	} else {
		r = amdgpu_asic_reset(adev);
		if (r)
			DRM_ERROR("amdgpu asic reset failed\n");
A
Alex Deucher 已提交
2727 2728 2729 2730 2731 2732
	}

	return 0;
}

/**
2733
 * amdgpu_device_resume - initiate device resume
A
Alex Deucher 已提交
2734
 *
2735 2736 2737
 * @dev: drm dev pointer
 * @resume: resume state
 * @fbcon : notify the fbdev of resume
A
Alex Deucher 已提交
2738 2739 2740 2741 2742
 *
 * Bring the hw back to operating state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver resume.
 */
2743
int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
A
Alex Deucher 已提交
2744 2745 2746
{
	struct drm_connector *connector;
	struct amdgpu_device *adev = dev->dev_private;
2747
	struct drm_crtc *crtc;
2748
	int r = 0;
A
Alex Deucher 已提交
2749 2750 2751 2752 2753 2754 2755

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	if (resume) {
		pci_set_power_state(dev->pdev, PCI_D0);
		pci_restore_state(dev->pdev);
J
jimqu 已提交
2756
		r = pci_enable_device(dev->pdev);
2757
		if (r)
2758
			return r;
A
Alex Deucher 已提交
2759 2760 2761
	}

	/* post card */
A
Alex Deucher 已提交
2762
	if (amdgpu_device_need_post(adev)) {
J
jimqu 已提交
2763 2764 2765 2766
		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
		if (r)
			DRM_ERROR("amdgpu asic init failed\n");
	}
A
Alex Deucher 已提交
2767

2768
	r = amdgpu_device_ip_resume(adev);
2769
	if (r) {
2770
		DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2771
		return r;
2772
	}
2773 2774
	amdgpu_fence_driver_resume(adev);

A
Alex Deucher 已提交
2775

2776
	r = amdgpu_device_ip_late_init(adev);
2777
	if (r)
2778
		return r;
A
Alex Deucher 已提交
2779

2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794
	if (!amdgpu_device_has_dc_support(adev)) {
		/* pin cursors */
		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
			struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (amdgpu_crtc->cursor_bo) {
				struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
				r = amdgpu_bo_reserve(aobj, true);
				if (r == 0) {
					r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
					if (r != 0)
						DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
					amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
					amdgpu_bo_unreserve(aobj);
				}
2795 2796 2797
			}
		}
	}
2798 2799 2800
	r = amdgpu_amdkfd_resume(adev);
	if (r)
		return r;
2801

2802 2803 2804
	/* Make sure IB tests flushed */
	flush_delayed_work(&adev->late_init_work);

A
Alex Deucher 已提交
2805 2806
	/* blat the mode back in */
	if (fbcon) {
2807 2808 2809 2810 2811 2812 2813 2814 2815 2816
		if (!amdgpu_device_has_dc_support(adev)) {
			/* pre DCE11 */
			drm_helper_resume_force_mode(dev);

			/* turn on display hw */
			drm_modeset_lock_all(dev);
			list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
			}
			drm_modeset_unlock_all(dev);
A
Alex Deucher 已提交
2817
		}
2818
		amdgpu_fbdev_set_suspend(adev, 0);
A
Alex Deucher 已提交
2819 2820 2821
	}

	drm_kms_helper_poll_enable(dev);
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834

	/*
	 * Most of the connector probing functions try to acquire runtime pm
	 * refs to ensure that the GPU is powered on when connector polling is
	 * performed. Since we're calling this from a runtime PM callback,
	 * trying to acquire rpm refs will cause us to deadlock.
	 *
	 * Since we're guaranteed to be holding the rpm lock, it's safe to
	 * temporarily disable the rpm helpers so this doesn't deadlock us.
	 */
#ifdef CONFIG_PM
	dev->dev->power.disable_depth++;
#endif
2835 2836 2837 2838
	if (!amdgpu_device_has_dc_support(adev))
		drm_helper_hpd_irq_event(dev);
	else
		drm_kms_helper_hotplug_event(dev);
2839 2840 2841
#ifdef CONFIG_PM
	dev->dev->power.disable_depth--;
#endif
2842 2843
	adev->in_suspend = false;

2844
	return 0;
A
Alex Deucher 已提交
2845 2846
}

2847 2848 2849 2850 2851 2852 2853 2854 2855 2856
/**
 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
 *
 * @adev: amdgpu_device pointer
 *
 * The list of all the hardware IPs that make up the asic is walked and
 * the check_soft_reset callbacks are run.  check_soft_reset determines
 * if the asic is still hung or not.
 * Returns true if any of the IPs are still in a hung state, false if not.
 */
2857
static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2858 2859 2860 2861
{
	int i;
	bool asic_hang = false;

2862 2863 2864
	if (amdgpu_sriov_vf(adev))
		return true;

2865 2866 2867
	if (amdgpu_asic_need_full_reset(adev))
		return true;

2868
	for (i = 0; i < adev->num_ip_blocks; i++) {
2869
		if (!adev->ip_blocks[i].status.valid)
2870
			continue;
2871 2872 2873 2874 2875
		if (adev->ip_blocks[i].version->funcs->check_soft_reset)
			adev->ip_blocks[i].status.hang =
				adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
		if (adev->ip_blocks[i].status.hang) {
			DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2876 2877 2878 2879 2880 2881
			asic_hang = true;
		}
	}
	return asic_hang;
}

2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892
/**
 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
 *
 * @adev: amdgpu_device pointer
 *
 * The list of all the hardware IPs that make up the asic is walked and the
 * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
 * handles any IP specific hardware or software state changes that are
 * necessary for a soft reset to succeed.
 * Returns 0 on success, negative error code on failure.
 */
2893
static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2894 2895 2896 2897
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2898
		if (!adev->ip_blocks[i].status.valid)
2899
			continue;
2900 2901 2902
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->pre_soft_reset) {
			r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2903 2904 2905 2906 2907 2908 2909 2910
			if (r)
				return r;
		}
	}

	return 0;
}

2911 2912 2913 2914 2915 2916 2917 2918 2919
/**
 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
 *
 * @adev: amdgpu_device pointer
 *
 * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
 * reset is necessary to recover.
 * Returns true if a full asic reset is required, false if not.
 */
2920
static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2921
{
2922 2923
	int i;

2924 2925 2926
	if (amdgpu_asic_need_full_reset(adev))
		return true;

2927
	for (i = 0; i < adev->num_ip_blocks; i++) {
2928
		if (!adev->ip_blocks[i].status.valid)
2929
			continue;
2930 2931 2932
		if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2933 2934
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2935
			if (adev->ip_blocks[i].status.hang) {
2936 2937 2938 2939
				DRM_INFO("Some block need full reset!\n");
				return true;
			}
		}
2940 2941 2942 2943
	}
	return false;
}

2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954
/**
 * amdgpu_device_ip_soft_reset - do a soft reset
 *
 * @adev: amdgpu_device pointer
 *
 * The list of all the hardware IPs that make up the asic is walked and the
 * soft_reset callbacks are run if the block is hung.  soft_reset handles any
 * IP specific hardware or software state changes that are necessary to soft
 * reset the IP.
 * Returns 0 on success, negative error code on failure.
 */
2955
static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2956 2957 2958 2959
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2960
		if (!adev->ip_blocks[i].status.valid)
2961
			continue;
2962 2963 2964
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->soft_reset) {
			r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2965 2966 2967 2968 2969 2970 2971 2972
			if (r)
				return r;
		}
	}

	return 0;
}

2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983
/**
 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
 *
 * @adev: amdgpu_device pointer
 *
 * The list of all the hardware IPs that make up the asic is walked and the
 * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
 * handles any IP specific hardware or software state changes that are
 * necessary after the IP has been soft reset.
 * Returns 0 on success, negative error code on failure.
 */
2984
static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
2985 2986 2987 2988
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2989
		if (!adev->ip_blocks[i].status.valid)
2990
			continue;
2991 2992 2993
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->post_soft_reset)
			r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2994 2995 2996 2997 2998 2999 3000
		if (r)
			return r;
	}

	return 0;
}

3001
/**
3002
 * amdgpu_device_recover_vram - Recover some VRAM contents
3003 3004 3005 3006 3007 3008
 *
 * @adev: amdgpu_device pointer
 *
 * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
 * restore things like GPUVM page tables after a GPU reset where
 * the contents of VRAM might be lost.
3009 3010 3011
 *
 * Returns:
 * 0 on success, negative error code on failure.
3012
 */
3013
static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3014 3015
{
	struct dma_fence *fence = NULL, *next = NULL;
3016 3017
	struct amdgpu_bo *shadow;
	long r = 1, tmo;
3018 3019

	if (amdgpu_sriov_runtime(adev))
3020
		tmo = msecs_to_jiffies(8000);
3021 3022 3023 3024 3025
	else
		tmo = msecs_to_jiffies(100);

	DRM_INFO("recover vram bo from shadow start\n");
	mutex_lock(&adev->shadow_list_lock);
3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036
	list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {

		/* No need to recover an evicted BO */
		if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
		    shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
			continue;

		r = amdgpu_bo_restore_shadow(shadow, &next);
		if (r)
			break;

3037 3038
		if (fence) {
			r = dma_fence_wait_timeout(fence, false, tmo);
3039 3040 3041
			dma_fence_put(fence);
			fence = next;
			if (r <= 0)
3042
				break;
3043 3044
		} else {
			fence = next;
3045 3046 3047 3048
		}
	}
	mutex_unlock(&adev->shadow_list_lock);

3049 3050
	if (fence)
		tmo = dma_fence_wait_timeout(fence, false, tmo);
3051 3052
	dma_fence_put(fence);

3053
	if (r <= 0 || tmo <= 0) {
3054
		DRM_ERROR("recover vram bo from shadow failed\n");
3055 3056
		return -EIO;
	}
3057

3058 3059
	DRM_INFO("recover vram bo from shadow done\n");
	return 0;
3060 3061
}

3062
/**
3063
 * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
3064 3065 3066
 *
 * @adev: amdgpu device pointer
 *
3067
 * attempt to do soft-reset or full-reset and reinitialize Asic
3068
 * return 0 means succeeded otherwise failed
3069
 */
3070
static int amdgpu_device_reset(struct amdgpu_device *adev)
3071
{
3072 3073
	bool need_full_reset, vram_lost = 0;
	int r;
3074

3075
	need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3076

3077
	if (!need_full_reset) {
3078 3079 3080 3081
		amdgpu_device_ip_pre_soft_reset(adev);
		r = amdgpu_device_ip_soft_reset(adev);
		amdgpu_device_ip_post_soft_reset(adev);
		if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3082 3083 3084 3085
			DRM_INFO("soft reset failed, will fallback to full reset!\n");
			need_full_reset = true;
		}
	}
3086

3087
	if (need_full_reset) {
3088
		r = amdgpu_device_ip_suspend(adev);
3089

3090 3091 3092 3093
retry:
		r = amdgpu_asic_reset(adev);
		/* post card */
		amdgpu_atom_asic_init(adev->mode_info.atom_context);
3094

3095 3096
		if (!r) {
			dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
3097
			r = amdgpu_device_ip_resume_phase1(adev);
3098 3099
			if (r)
				goto out;
3100

3101
			vram_lost = amdgpu_device_check_vram_lost(adev);
3102 3103 3104 3105 3106
			if (vram_lost) {
				DRM_ERROR("VRAM is lost!\n");
				atomic_inc(&adev->vram_lost_counter);
			}

3107 3108
			r = amdgpu_gtt_mgr_recover(
				&adev->mman.bdev.man[TTM_PL_TT]);
3109 3110 3111
			if (r)
				goto out;

3112
			r = amdgpu_device_ip_resume_phase2(adev);
3113 3114 3115 3116
			if (r)
				goto out;

			if (vram_lost)
3117
				amdgpu_device_fill_reset_magic(adev);
3118
		}
3119
	}
3120

3121 3122 3123 3124 3125 3126
out:
	if (!r) {
		amdgpu_irq_gpu_reset_resume_helper(adev);
		r = amdgpu_ib_ring_tests(adev);
		if (r) {
			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
3127
			r = amdgpu_device_ip_suspend(adev);
3128 3129 3130 3131
			need_full_reset = true;
			goto retry;
		}
	}
3132

3133 3134
	if (!r)
		r = amdgpu_device_recover_vram(adev);
3135

3136 3137
	return r;
}
3138

3139
/**
3140
 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3141 3142
 *
 * @adev: amdgpu device pointer
3143
 * @from_hypervisor: request from hypervisor
3144 3145
 *
 * do VF FLR and reinitialize Asic
3146
 * return 0 means succeeded otherwise failed
3147 3148 3149
 */
static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
				     bool from_hypervisor)
3150 3151 3152 3153 3154 3155 3156 3157 3158
{
	int r;

	if (from_hypervisor)
		r = amdgpu_virt_request_full_gpu(adev, true);
	else
		r = amdgpu_virt_reset_gpu(adev);
	if (r)
		return r;
3159 3160

	/* Resume IP prior to SMC */
3161
	r = amdgpu_device_ip_reinit_early_sriov(adev);
3162 3163
	if (r)
		goto error;
3164 3165

	/* we need recover gart prior to run SMC/CP/SDMA resume */
3166
	amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3167 3168

	/* now we are okay to resume SMC/CP/SDMA */
3169
	r = amdgpu_device_ip_reinit_late_sriov(adev);
3170 3171
	if (r)
		goto error;
3172 3173

	amdgpu_irq_gpu_reset_resume_helper(adev);
3174
	r = amdgpu_ib_ring_tests(adev);
3175

3176 3177
error:
	amdgpu_virt_release_full_gpu(adev, true);
3178 3179
	if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
		atomic_inc(&adev->vram_lost_counter);
3180
		r = amdgpu_device_recover_vram(adev);
3181 3182 3183 3184 3185
	}

	return r;
}

3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209
/**
 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
 *
 * @adev: amdgpu device pointer
 *
 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
 * a hung GPU.
 */
bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
{
	if (!amdgpu_device_ip_check_soft_reset(adev)) {
		DRM_INFO("Timeout, but no hardware hang detected.\n");
		return false;
	}

	if (amdgpu_gpu_recovery == 0 || (amdgpu_gpu_recovery == -1  &&
					 !amdgpu_sriov_vf(adev))) {
		DRM_INFO("GPU recovery disabled.\n");
		return false;
	}

	return true;
}

A
Alex Deucher 已提交
3210
/**
3211
 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
A
Alex Deucher 已提交
3212 3213
 *
 * @adev: amdgpu device pointer
3214
 * @job: which job trigger hang
A
Alex Deucher 已提交
3215
 *
3216
 * Attempt to reset the GPU if it has hung (all asics).
A
Alex Deucher 已提交
3217 3218
 * Returns 0 for success or an error on failure.
 */
3219
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3220
			      struct amdgpu_job *job)
A
Alex Deucher 已提交
3221
{
3222
	int i, r, resched;
3223

3224 3225
	dev_info(adev->dev, "GPU reset begin!\n");

3226
	mutex_lock(&adev->lock_reset);
3227
	atomic_inc(&adev->gpu_reset_counter);
3228
	adev->in_gpu_reset = 1;
A
Alex Deucher 已提交
3229

3230 3231 3232
	/* Block kfd */
	amdgpu_amdkfd_pre_reset(adev);

3233 3234
	/* block TTM */
	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3235 3236

	/* block all schedulers and reset given job's ring */
3237 3238 3239
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_ring *ring = adev->rings[i];

C
Chunming Zhou 已提交
3240
		if (!ring || !ring->sched.thread)
3241
			continue;
3242

3243 3244
		kthread_park(ring->sched.thread);

C
Christian König 已提交
3245
		if (job && job->base.sched == &ring->sched)
3246 3247
			continue;

3248
		drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
3249

M
Monk Liu 已提交
3250 3251
		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
		amdgpu_fence_driver_force_completion(ring);
3252
	}
A
Alex Deucher 已提交
3253

3254
	if (amdgpu_sriov_vf(adev))
3255
		r = amdgpu_device_reset_sriov(adev, job ? false : true);
3256
	else
3257
		r = amdgpu_device_reset(adev);
3258

3259 3260
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_ring *ring = adev->rings[i];
3261

3262 3263
		if (!ring || !ring->sched.thread)
			continue;
3264

3265 3266 3267 3268
		/* only need recovery sched of the given job's ring
		 * or all rings (in the case @job is NULL)
		 * after above amdgpu_reset accomplished
		 */
C
Christian König 已提交
3269
		if ((!job || job->base.sched == &ring->sched) && !r)
3270
			drm_sched_job_recovery(&ring->sched);
3271

3272
		kthread_unpark(ring->sched.thread);
A
Alex Deucher 已提交
3273 3274
	}

3275
	if (!amdgpu_device_has_dc_support(adev)) {
3276
		drm_helper_resume_force_mode(adev->ddev);
3277
	}
A
Alex Deucher 已提交
3278 3279

	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3280

3281
	if (r) {
A
Alex Deucher 已提交
3282
		/* bad news, how to tell it to userspace ? */
3283 3284 3285
		dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
	} else {
3286
		dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter));
3287
	}
A
Alex Deucher 已提交
3288

3289 3290
	/*unlock kfd */
	amdgpu_amdkfd_post_reset(adev);
3291
	amdgpu_vf_error_trans_all(adev);
3292 3293
	adev->in_gpu_reset = 0;
	mutex_unlock(&adev->lock_reset);
A
Alex Deucher 已提交
3294 3295 3296
	return r;
}

3297 3298 3299 3300 3301 3302 3303 3304 3305
/**
 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
 *
 * @adev: amdgpu_device pointer
 *
 * Fetchs and stores in the driver the PCIE capabilities (gen speed
 * and lanes) of the slot the device is in. Handles APUs and
 * virtualized environments where PCIE config space may not be available.
 */
3306
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3307
{
3308 3309 3310
	struct pci_dev *pdev;
	enum pci_bus_speed speed_cap;
	enum pcie_link_width link_width;
3311

3312 3313
	if (amdgpu_pcie_gen_cap)
		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3314

3315 3316
	if (amdgpu_pcie_lane_cap)
		adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3317

3318 3319 3320 3321 3322 3323
	/* covers APUs as well */
	if (pci_is_root_bus(adev->pdev->bus)) {
		if (adev->pm.pcie_gen_mask == 0)
			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
		if (adev->pm.pcie_mlw_mask == 0)
			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3324
		return;
3325
	}
3326

3327
	if (adev->pm.pcie_gen_mask == 0) {
3328 3329 3330 3331 3332
		/* asic caps */
		pdev = adev->pdev;
		speed_cap = pcie_get_speed_cap(pdev);
		if (speed_cap == PCI_SPEED_UNKNOWN) {
			adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3333 3334 3335
						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
		} else {
3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372
			if (speed_cap == PCIE_SPEED_16_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
			else if (speed_cap == PCIE_SPEED_8_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
			else if (speed_cap == PCIE_SPEED_5_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
			else
				adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
		}
		/* platform caps */
		pdev = adev->ddev->pdev->bus->self;
		speed_cap = pcie_get_speed_cap(pdev);
		if (speed_cap == PCI_SPEED_UNKNOWN) {
			adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
						   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
		} else {
			if (speed_cap == PCIE_SPEED_16_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
			else if (speed_cap == PCIE_SPEED_8_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
			else if (speed_cap == PCIE_SPEED_5_0GT)
				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
			else
				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;

3373 3374 3375
		}
	}
	if (adev->pm.pcie_mlw_mask == 0) {
3376 3377 3378 3379 3380 3381 3382
		pdev = adev->ddev->pdev->bus->self;
		link_width = pcie_get_width_cap(pdev);
		if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
			adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
		} else {
			switch (link_width) {
			case PCIE_LNK_X32:
3383 3384 3385 3386 3387 3388 3389 3390
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3391
			case PCIE_LNK_X16:
3392 3393 3394 3395 3396 3397 3398
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3399
			case PCIE_LNK_X12:
3400 3401 3402 3403 3404 3405
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3406
			case PCIE_LNK_X8:
3407 3408 3409 3410 3411
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3412
			case PCIE_LNK_X4:
3413 3414 3415 3416
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3417
			case PCIE_LNK_X2:
3418 3419 3420
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
3421
			case PCIE_LNK_X1:
3422 3423 3424 3425 3426
				adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
				break;
			default:
				break;
			}
3427 3428 3429
		}
	}
}
A
Alex Deucher 已提交
3430