amdgpu_device.c 100.2 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
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#include <linux/kthread.h>
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#include <linux/console.h>
#include <linux/slab.h>
#include <linux/debugfs.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/amdgpu_drm.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>
#include <linux/efi.h>
#include "amdgpu.h"
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#include "amdgpu_trace.h"
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#include "amdgpu_i2c.h"
#include "atom.h"
#include "amdgpu_atombios.h"
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#include "amdgpu_atomfirmware.h"
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#include "amd_pcie.h"
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#ifdef CONFIG_DRM_AMDGPU_SI
#include "si.h"
#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
#include "cik.h"
#endif
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#include "vi.h"
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#include "soc15.h"
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#include "bif/bif_4_1_d.h"
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include "amdgpu_vf_error.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_pm.h"
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MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
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#define AMDGPU_RESUME_MS		2000

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static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
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static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
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static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
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static const char *amdgpu_asic_name[] = {
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	"TAHITI",
	"PITCAIRN",
	"VERDE",
	"OLAND",
	"HAINAN",
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	"BONAIRE",
	"KAVERI",
	"KABINI",
	"HAWAII",
	"MULLINS",
	"TOPAZ",
	"TONGA",
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	"FIJI",
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	"CARRIZO",
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	"STONEY",
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	"POLARIS10",
	"POLARIS11",
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	"POLARIS12",
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	"VEGA10",
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	"RAVEN",
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	"LAST",
};

bool amdgpu_device_is_px(struct drm_device *dev)
{
	struct amdgpu_device *adev = dev->dev_private;

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	if (adev->flags & AMD_IS_PX)
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		return true;
	return false;
}

/*
 * MMIO register access helper functions.
 */
uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
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			uint32_t acc_flags)
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{
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	uint32_t ret;

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	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
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		return amdgpu_virt_kiq_rreg(adev, reg);

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	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
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		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
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	else {
		unsigned long flags;

		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
	}
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	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
	return ret;
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}

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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		    uint32_t acc_flags)
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{
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	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
		adev->last_mm_index = v;
	}

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	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
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		return amdgpu_virt_kiq_wreg(adev, reg, v);

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	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
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		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
	else {
		unsigned long flags;

		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
	}
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
		udelay(500);
	}
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}

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
{
	if ((reg * 4) < adev->rio_mem_size)
		return ioread32(adev->rio_mem + (reg * 4));
	else {
		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
		return ioread32(adev->rio_mem + (mmMM_DATA * 4));
	}
}

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
		adev->last_mm_index = v;
	}
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	if ((reg * 4) < adev->rio_mem_size)
		iowrite32(v, adev->rio_mem + (reg * 4));
	else {
		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
		iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
	}
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	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
		udelay(500);
	}
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}

/**
 * amdgpu_mm_rdoorbell - read a doorbell dword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 *
 * Returns the value in the doorbell aperture at the
 * requested doorbell index (CIK).
 */
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
{
	if (index < adev->doorbell.num_doorbells) {
		return readl(adev->doorbell.ptr + index);
	} else {
		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
		return 0;
	}
}

/**
 * amdgpu_mm_wdoorbell - write a doorbell dword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 * @v: value to write
 *
 * Writes @v to the doorbell aperture at the
 * requested doorbell index (CIK).
 */
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
{
	if (index < adev->doorbell.num_doorbells) {
		writel(v, adev->doorbell.ptr + index);
	} else {
		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
	}
}

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/**
 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 *
 * Returns the value in the doorbell aperture at the
 * requested doorbell index (VEGA10+).
 */
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
{
	if (index < adev->doorbell.num_doorbells) {
		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
	} else {
		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
		return 0;
	}
}

/**
 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 *
 * @adev: amdgpu_device pointer
 * @index: doorbell index
 * @v: value to write
 *
 * Writes @v to the doorbell aperture at the
 * requested doorbell index (VEGA10+).
 */
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
{
	if (index < adev->doorbell.num_doorbells) {
		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
	} else {
		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
	}
}

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/**
 * amdgpu_invalid_rreg - dummy reg read function
 *
 * @adev: amdgpu device pointer
 * @reg: offset of register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 * Returns the value in the register.
 */
static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
{
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
	BUG();
	return 0;
}

/**
 * amdgpu_invalid_wreg - dummy reg write function
 *
 * @adev: amdgpu device pointer
 * @reg: offset of register
 * @v: value to write to the register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 */
static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
{
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		  reg, v);
	BUG();
}

/**
 * amdgpu_block_invalid_rreg - dummy reg read function
 *
 * @adev: amdgpu device pointer
 * @block: offset of instance
 * @reg: offset of register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 * Returns the value in the register.
 */
static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
					  uint32_t block, uint32_t reg)
{
	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
		  reg, block);
	BUG();
	return 0;
}

/**
 * amdgpu_block_invalid_wreg - dummy reg write function
 *
 * @adev: amdgpu device pointer
 * @block: offset of instance
 * @reg: offset of register
 * @v: value to write to the register
 *
 * Dummy register read function.  Used for register blocks
 * that certain asics don't have (all asics).
 */
static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
				      uint32_t block,
				      uint32_t reg, uint32_t v)
{
	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
		  reg, block, v);
	BUG();
}

static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
{
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	return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
				       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
				       &adev->vram_scratch.robj,
				       &adev->vram_scratch.gpu_addr,
				       (void **)&adev->vram_scratch.ptr);
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}

static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
{
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	amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
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}

/**
 * amdgpu_program_register_sequence - program an array of registers.
 *
 * @adev: amdgpu_device pointer
 * @registers: pointer to the register array
 * @array_size: size of the register array
 *
 * Programs an array or registers with and and or masks.
 * This is a helper for setting golden registers.
 */
void amdgpu_program_register_sequence(struct amdgpu_device *adev,
				      const u32 *registers,
				      const u32 array_size)
{
	u32 tmp, reg, and_mask, or_mask;
	int i;

	if (array_size % 3)
		return;

	for (i = 0; i < array_size; i +=3) {
		reg = registers[i + 0];
		and_mask = registers[i + 1];
		or_mask = registers[i + 2];

		if (and_mask == 0xffffffff) {
			tmp = or_mask;
		} else {
			tmp = RREG32(reg);
			tmp &= ~and_mask;
			tmp |= or_mask;
		}
		WREG32(reg, tmp);
	}
}

void amdgpu_pci_config_reset(struct amdgpu_device *adev)
{
	pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
}

/*
 * GPU doorbell aperture helpers function.
 */
/**
 * amdgpu_doorbell_init - Init doorbell driver information.
 *
 * @adev: amdgpu_device pointer
 *
 * Init doorbell driver information (CIK)
 * Returns 0 on success, error on failure.
 */
static int amdgpu_doorbell_init(struct amdgpu_device *adev)
{
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	/* No doorbell on SI hardware generation */
	if (adev->asic_type < CHIP_BONAIRE) {
		adev->doorbell.base = 0;
		adev->doorbell.size = 0;
		adev->doorbell.num_doorbells = 0;
		adev->doorbell.ptr = NULL;
		return 0;
	}

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	/* doorbell bar mapping */
	adev->doorbell.base = pci_resource_start(adev->pdev, 2);
	adev->doorbell.size = pci_resource_len(adev->pdev, 2);

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	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
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					     AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
	if (adev->doorbell.num_doorbells == 0)
		return -EINVAL;

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	adev->doorbell.ptr = ioremap(adev->doorbell.base,
				     adev->doorbell.num_doorbells *
				     sizeof(u32));
	if (adev->doorbell.ptr == NULL)
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		return -ENOMEM;

	return 0;
}

/**
 * amdgpu_doorbell_fini - Tear down doorbell driver information.
 *
 * @adev: amdgpu_device pointer
 *
 * Tear down doorbell driver information (CIK)
 */
static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
{
	iounmap(adev->doorbell.ptr);
	adev->doorbell.ptr = NULL;
}

/**
 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 *                                setup amdkfd
 *
 * @adev: amdgpu_device pointer
 * @aperture_base: output returning doorbell aperture base physical address
 * @aperture_size: output returning doorbell aperture size in bytes
 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 *
 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 * takes doorbells required for its own rings and reports the setup to amdkfd.
 * amdgpu reserved doorbells are at the start of the doorbell aperture.
 */
void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
				phys_addr_t *aperture_base,
				size_t *aperture_size,
				size_t *start_offset)
{
	/*
	 * The first num_doorbells are used by amdgpu.
	 * amdkfd takes whatever's left in the aperture.
	 */
	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
		*aperture_base = adev->doorbell.base;
		*aperture_size = adev->doorbell.size;
		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
	} else {
		*aperture_base = 0;
		*aperture_size = 0;
		*start_offset = 0;
	}
}

/*
 * amdgpu_wb_*()
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 * Writeback is the method by which the GPU updates special pages in memory
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 * with the status of certain GPU events (fences, ring pointers,etc.).
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 */

/**
 * amdgpu_wb_fini - Disable Writeback and free memory
 *
 * @adev: amdgpu_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
static void amdgpu_wb_fini(struct amdgpu_device *adev)
{
	if (adev->wb.wb_obj) {
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		amdgpu_bo_free_kernel(&adev->wb.wb_obj,
				      &adev->wb.gpu_addr,
				      (void **)&adev->wb.wb);
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		adev->wb.wb_obj = NULL;
	}
}

/**
 * amdgpu_wb_init- Init Writeback driver info and allocate memory
 *
 * @adev: amdgpu_device pointer
 *
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 * Initializes writeback and allocates writeback memory (all asics).
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 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
static int amdgpu_wb_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->wb.wb_obj == NULL) {
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		/* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
		r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
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					    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
					    &adev->wb.wb_obj, &adev->wb.gpu_addr,
					    (void **)&adev->wb.wb);
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		if (r) {
			dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}

		adev->wb.num_wb = AMDGPU_MAX_WB;
		memset(&adev->wb.used, 0, sizeof(adev->wb.used));

		/* clear wb memory */
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		memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
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	}

	return 0;
}

/**
 * amdgpu_wb_get - Allocate a wb entry
 *
 * @adev: amdgpu_device pointer
 * @wb: wb index
 *
 * Allocate a wb slot for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
{
	unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);

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	if (offset < adev->wb.num_wb) {
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		__set_bit(offset, adev->wb.used);
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		*wb = offset << 3; /* convert to dw offset */
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		return 0;
	} else {
		return -EINVAL;
	}
}

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/**
 * amdgpu_wb_free - Free a wb entry
 *
 * @adev: amdgpu_device pointer
 * @wb: wb index
 *
 * Free a wb slot allocated for use by the driver (all asics)
 */
void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
{
	if (wb < adev->wb.num_wb)
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		__clear_bit(wb >> 3, adev->wb.used);
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}

/**
 * amdgpu_vram_location - try to find VRAM location
 * @adev: amdgpu device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 * @base: base address at which to put VRAM
 *
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 * Function will try to place VRAM at base address provided
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 * as parameter (which is so far either PCI aperture address or
 * for IGP TOM base address).
 *
 * If there is not enough space to fit the unvisible VRAM in the 32bits
 * address space then we limit the VRAM size to the aperture.
 *
 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 * not IGP.
 *
 * Note: we use mc_vram_size as on some board we need to program the mc to
 * cover the whole aperture even if VRAM size is inferior to aperture size
 * Novell bug 204882 + along with lots of ubuntu ones
 *
 * Note: when limiting vram it's safe to overwritte real_vram_size because
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 * ones)
 *
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
599
 * explicitly check for that though.
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 *
 * FIXME: when reducing VRAM size align new size on power of 2.
 */
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
{
	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;

	mc->vram_start = base;
	if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
		dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
	if (limit && limit < mc->real_vram_size)
		mc->real_vram_size = limit;
	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
			mc->mc_vram_size >> 20, mc->vram_start,
			mc->vram_end, mc->real_vram_size >> 20);
}

/**
622
 * amdgpu_gart_location - try to find GTT location
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 * @adev: amdgpu device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 *
 * Function will place try to place GTT before or after VRAM.
 *
 * If GTT size is bigger than space left then we ajust GTT size.
 * Thus function will never fails.
 *
 * FIXME: when reducing GTT size align new size on power of 2.
 */
633
void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
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Alex Deucher 已提交
634 635 636
{
	u64 size_af, size_bf;

637 638
	size_af = adev->mc.mc_mask - mc->vram_end;
	size_bf = mc->vram_start;
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Alex Deucher 已提交
639
	if (size_bf > size_af) {
640
		if (mc->gart_size > size_bf) {
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641
			dev_warn(adev->dev, "limiting GTT\n");
642
			mc->gart_size = size_bf;
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Alex Deucher 已提交
643
		}
644
		mc->gart_start = 0;
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645
	} else {
646
		if (mc->gart_size > size_af) {
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647
			dev_warn(adev->dev, "limiting GTT\n");
648
			mc->gart_size = size_af;
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649
		}
650
		mc->gart_start = mc->vram_end + 1;
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	}
652
	mc->gart_end = mc->gart_start + mc->gart_size - 1;
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	dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
654
			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}

657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731
/*
 * Firmware Reservation functions
 */
/**
 * amdgpu_fw_reserve_vram_fini - free fw reserved vram
 *
 * @adev: amdgpu_device pointer
 *
 * free fw reserved vram if it has been reserved.
 */
void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
{
	amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
		NULL, &adev->fw_vram_usage.va);
}

/**
 * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
 *
 * @adev: amdgpu_device pointer
 *
 * create bo vram reservation from fw.
 */
int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
{
	int r = 0;
	u64 gpu_addr;
	u64 vram_size = adev->mc.visible_vram_size;

	adev->fw_vram_usage.va = NULL;
	adev->fw_vram_usage.reserved_bo = NULL;

	if (adev->fw_vram_usage.size > 0 &&
		adev->fw_vram_usage.size <= vram_size) {

		r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
			PAGE_SIZE, true, 0,
			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
			&adev->fw_vram_usage.reserved_bo);
		if (r)
			goto error_create;

		r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
		if (r)
			goto error_reserve;
		r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
			AMDGPU_GEM_DOMAIN_VRAM,
			adev->fw_vram_usage.start_offset,
			(adev->fw_vram_usage.start_offset +
			adev->fw_vram_usage.size), &gpu_addr);
		if (r)
			goto error_pin;
		r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
			&adev->fw_vram_usage.va);
		if (r)
			goto error_kmap;

		amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
	}
	return r;

error_kmap:
	amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
error_pin:
	amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
error_reserve:
	amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
error_create:
	adev->fw_vram_usage.va = NULL;
	adev->fw_vram_usage.reserved_bo = NULL;
	return r;
}


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Alex Deucher 已提交
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/*
 * GPU helpers function.
 */
/**
736
 * amdgpu_need_post - check if the hw need post or not
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Alex Deucher 已提交
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 *
 * @adev: amdgpu_device pointer
 *
740 741 742
 * Check if the asic has been initialized (all asics) at driver startup
 * or post is needed if  hw reset is performed.
 * Returns true if need or false if not.
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Alex Deucher 已提交
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 */
744
bool amdgpu_need_post(struct amdgpu_device *adev)
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Alex Deucher 已提交
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{
	uint32_t reg;

748 749 750 751
	if (amdgpu_sriov_vf(adev))
		return false;

	if (amdgpu_passthrough(adev)) {
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		/* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
		 * some old smc fw still need driver do vPost otherwise gpu hang, while
		 * those smc fw version above 22.15 doesn't have this flaw, so we force
		 * vpost executed for smc version below 22.15
756 757 758 759 760 761 762 763 764 765
		 */
		if (adev->asic_type == CHIP_FIJI) {
			int err;
			uint32_t fw_ver;
			err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
			/* force vPost if error occured */
			if (err)
				return true;

			fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
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			if (fw_ver < 0x00160e00)
				return true;
768 769
		}
	}
770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786

	if (adev->has_hw_reset) {
		adev->has_hw_reset = false;
		return true;
	}

	/* bios scratch used on CIK+ */
	if (adev->asic_type >= CHIP_BONAIRE)
		return amdgpu_atombios_scratch_need_asic_init(adev);

	/* check MEM_SIZE for older asics */
	reg = amdgpu_asic_get_config_memsize(adev);

	if ((reg != 0) && (reg != 0xffffffff))
		return false;

	return true;
787 788
}

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/**
 * amdgpu_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
int amdgpu_dummy_page_init(struct amdgpu_device *adev)
{
	if (adev->dummy_page.page)
		return 0;
	adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
	if (adev->dummy_page.page == NULL)
		return -ENOMEM;
	adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		__free_page(adev->dummy_page.page);
		adev->dummy_page.page = NULL;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
{
	if (adev->dummy_page.page == NULL)
		return;
	pci_unmap_page(adev->pdev, adev->dummy_page.addr,
			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	__free_page(adev->dummy_page.page);
	adev->dummy_page.page = NULL;
}


/* ATOM accessor methods */
/*
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 * driver registers callbacks to access registers and the interpreter
 * in the driver parses the tables and executes then to program specific
 * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 * atombios.h, and atom.c
 */

/**
 * cail_pll_read - read PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 * Returns the value of the PLL register.
 */
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
	return 0;
}

/**
 * cail_pll_write - write PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 * @val: value to write to the pll register
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 */
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{

}

/**
 * cail_mc_read - read MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 *
 * Provides an MC register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MC register.
 */
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
	return 0;
}

/**
 * cail_mc_write - write MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 * @val: value to write to the pll register
 *
 * Provides a MC register accessor for the atom interpreter (r4xx+).
 */
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{

}

/**
 * cail_reg_write - write MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 * @val: value to write to the pll register
 *
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 */
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct amdgpu_device *adev = info->dev->dev_private;

	WREG32(reg, val);
}

/**
 * cail_reg_read - read MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 *
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MMIO register.
 */
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
	struct amdgpu_device *adev = info->dev->dev_private;
	uint32_t r;

	r = RREG32(reg);
	return r;
}

/**
 * cail_ioreg_write - write IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 * @val: value to write to the pll register
 *
 * Provides a IO register accessor for the atom interpreter (r4xx+).
 */
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct amdgpu_device *adev = info->dev->dev_private;

	WREG32_IO(reg, val);
}

/**
 * cail_ioreg_read - read IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 *
 * Provides an IO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the IO register.
 */
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
{
	struct amdgpu_device *adev = info->dev->dev_private;
	uint32_t r;

	r = RREG32_IO(reg);
	return r;
}

968 969 970 971 972 973 974 975 976 977 978 979 980 981
static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
						 struct device_attribute *attr,
						 char *buf)
{
	struct drm_device *ddev = dev_get_drvdata(dev);
	struct amdgpu_device *adev = ddev->dev_private;
	struct atom_context *ctx = adev->mode_info.atom_context;

	return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
}

static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
		   NULL);

A
Alex Deucher 已提交
982 983 984 985 986 987 988 989 990 991 992
/**
 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the driver info and register access callbacks for the ATOM
 * interpreter (r4xx+).
 * Called at driver shutdown.
 */
static void amdgpu_atombios_fini(struct amdgpu_device *adev)
{
M
Monk Liu 已提交
993
	if (adev->mode_info.atom_context) {
A
Alex Deucher 已提交
994
		kfree(adev->mode_info.atom_context->scratch);
M
Monk Liu 已提交
995 996
		kfree(adev->mode_info.atom_context->iio);
	}
A
Alex Deucher 已提交
997 998 999 1000
	kfree(adev->mode_info.atom_context);
	adev->mode_info.atom_context = NULL;
	kfree(adev->mode_info.atom_card_info);
	adev->mode_info.atom_card_info = NULL;
1001
	device_remove_file(adev->dev, &dev_attr_vbios_version);
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Alex Deucher 已提交
1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017
}

/**
 * amdgpu_atombios_init - init the driver info and callbacks for atombios
 *
 * @adev: amdgpu_device pointer
 *
 * Initializes the driver info and register access callbacks for the
 * ATOM interpreter (r4xx+).
 * Returns 0 on sucess, -ENOMEM on failure.
 * Called at driver startup.
 */
static int amdgpu_atombios_init(struct amdgpu_device *adev)
{
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
1018
	int ret;
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Alex Deucher 已提交
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031

	if (!atom_card_info)
		return -ENOMEM;

	adev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = adev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
	/* needed for iio ops */
	if (adev->rio_mem) {
		atom_card_info->ioreg_read = cail_ioreg_read;
		atom_card_info->ioreg_write = cail_ioreg_write;
	} else {
1032
		DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
A
Alex Deucher 已提交
1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047
		atom_card_info->ioreg_read = cail_reg_read;
		atom_card_info->ioreg_write = cail_reg_write;
	}
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;

	adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
	if (!adev->mode_info.atom_context) {
		amdgpu_atombios_fini(adev);
		return -ENOMEM;
	}

	mutex_init(&adev->mode_info.atom_context->mutex);
1048 1049 1050 1051 1052 1053 1054
	if (adev->is_atom_fw) {
		amdgpu_atomfirmware_scratch_regs_init(adev);
		amdgpu_atomfirmware_allocate_fb_scratch(adev);
	} else {
		amdgpu_atombios_scratch_regs_init(adev);
		amdgpu_atombios_allocate_fb_scratch(adev);
	}
1055 1056 1057 1058 1059 1060 1061

	ret = device_create_file(adev->dev, &dev_attr_vbios_version);
	if (ret) {
		DRM_ERROR("Failed to create device file for VBIOS version\n");
		return ret;
	}

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Alex Deucher 已提交
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	return 0;
}

/* if we get transitioned to only one device, take VGA back */
/**
 * amdgpu_vga_set_decode - enable/disable vga decode
 *
 * @cookie: amdgpu_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
{
	struct amdgpu_device *adev = cookie;
	amdgpu_asic_set_vga_state(adev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

1086
static void amdgpu_check_block_size(struct amdgpu_device *adev)
1087 1088 1089 1090
{
	/* defines number of bits in page table versus page directory,
	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
	 * page table and the remaining bits are in the page directory */
1091 1092
	if (amdgpu_vm_block_size == -1)
		return;
1093

1094
	if (amdgpu_vm_block_size < 9) {
1095 1096
		dev_warn(adev->dev, "VM page table size (%d) too small\n",
			 amdgpu_vm_block_size);
1097
		goto def_value;
1098 1099 1100 1101 1102 1103
	}

	if (amdgpu_vm_block_size > 24 ||
	    (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
		dev_warn(adev->dev, "VM page table size (%d) too large\n",
			 amdgpu_vm_block_size);
1104
		goto def_value;
1105
	}
1106 1107 1108 1109 1110

	return;

def_value:
	amdgpu_vm_block_size = -1;
1111 1112
}

1113 1114
static void amdgpu_check_vm_size(struct amdgpu_device *adev)
{
1115 1116 1117 1118
	/* no need to check the default value */
	if (amdgpu_vm_size == -1)
		return;

1119
	if (!is_power_of_2(amdgpu_vm_size)) {
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
		dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
			 amdgpu_vm_size);
		goto def_value;
	}

	if (amdgpu_vm_size < 1) {
		dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
			 amdgpu_vm_size);
		goto def_value;
	}

	/*
	 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
	 */
	if (amdgpu_vm_size > 1024) {
		dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
			 amdgpu_vm_size);
		goto def_value;
	}

	return;

def_value:
1143
	amdgpu_vm_size = -1;
1144 1145
}

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Alex Deucher 已提交
1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
/**
 * amdgpu_check_arguments - validate module params
 *
 * @adev: amdgpu_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
static void amdgpu_check_arguments(struct amdgpu_device *adev)
{
1156 1157 1158 1159
	if (amdgpu_sched_jobs < 4) {
		dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
			 amdgpu_sched_jobs);
		amdgpu_sched_jobs = 4;
1160
	} else if (!is_power_of_2(amdgpu_sched_jobs)){
1161 1162 1163 1164
		dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
			 amdgpu_sched_jobs);
		amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
	}
A
Alex Deucher 已提交
1165

1166
	if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1167 1168 1169
		/* gart size must be greater or equal to 32M */
		dev_warn(adev->dev, "gart size (%d) too small\n",
			 amdgpu_gart_size);
1170
		amdgpu_gart_size = -1;
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Alex Deucher 已提交
1171 1172
	}

1173
	if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1174
		/* gtt size must be greater or equal to 32M */
1175 1176 1177
		dev_warn(adev->dev, "gtt size (%d) too small\n",
				 amdgpu_gtt_size);
		amdgpu_gtt_size = -1;
A
Alex Deucher 已提交
1178 1179
	}

1180 1181 1182 1183 1184 1185 1186
	/* valid range is between 4 and 9 inclusive */
	if (amdgpu_vm_fragment_size != -1 &&
	    (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
		dev_warn(adev->dev, "valid range is between 4 and 9\n");
		amdgpu_vm_fragment_size = -1;
	}

1187
	amdgpu_check_vm_size(adev);
A
Alex Deucher 已提交
1188

1189
	amdgpu_check_block_size(adev);
C
Christian König 已提交
1190

1191
	if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1192
	    !is_power_of_2(amdgpu_vram_page_split))) {
C
Christian König 已提交
1193 1194 1195 1196
		dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
			 amdgpu_vram_page_split);
		amdgpu_vram_page_split = 1024;
	}
A
Alex Deucher 已提交
1197 1198 1199 1200 1201 1202
}

/**
 * amdgpu_switcheroo_set_state - set switcheroo state
 *
 * @pdev: pci dev pointer
1203
 * @state: vga_switcheroo state
A
Alex Deucher 已提交
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215
 *
 * Callback for the switcheroo driver.  Suspends or resumes the
 * the asics before or after it is powered up using ACPI methods.
 */
static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
		return;

	if (state == VGA_SWITCHEROO_ON) {
1216
		pr_info("amdgpu: switched on\n");
A
Alex Deucher 已提交
1217 1218 1219
		/* don't suspend or resume card normally */
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

1220
		amdgpu_device_resume(dev, true, true);
A
Alex Deucher 已提交
1221 1222 1223 1224

		dev->switch_power_state = DRM_SWITCH_POWER_ON;
		drm_kms_helper_poll_enable(dev);
	} else {
1225
		pr_info("amdgpu: switched off\n");
A
Alex Deucher 已提交
1226 1227
		drm_kms_helper_poll_disable(dev);
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1228
		amdgpu_device_suspend(dev, true, true);
A
Alex Deucher 已提交
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
	}
}

/**
 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
 *
 * @pdev: pci dev pointer
 *
 * Callback for the switcheroo driver.  Check of the switcheroo
 * state can be changed.
 * Returns true if the state can be changed, false if not.
 */
static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	/*
	* FIXME: open_count is protected by drm_global_mutex but that would lead to
	* locking inversion with the driver load path. And the access here is
	* completely racy anyway. So don't bother with locking for now.
	*/
	return dev->open_count == 0;
}

static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
	.set_gpu_state = amdgpu_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = amdgpu_switcheroo_can_switch,
};

int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1261 1262
				  enum amd_ip_block_type block_type,
				  enum amd_clockgating_state state)
A
Alex Deucher 已提交
1263 1264 1265 1266
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1267
		if (!adev->ip_blocks[i].status.valid)
1268
			continue;
1269 1270 1271 1272 1273 1274 1275 1276 1277
		if (adev->ip_blocks[i].version->type != block_type)
			continue;
		if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
			continue;
		r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
			(void *)adev, state);
		if (r)
			DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1278 1279 1280 1281 1282
	}
	return r;
}

int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1283 1284
				  enum amd_ip_block_type block_type,
				  enum amd_powergating_state state)
A
Alex Deucher 已提交
1285 1286 1287 1288
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1289
		if (!adev->ip_blocks[i].status.valid)
1290
			continue;
1291 1292 1293 1294 1295 1296 1297 1298 1299
		if (adev->ip_blocks[i].version->type != block_type)
			continue;
		if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
			continue;
		r = adev->ip_blocks[i].version->funcs->set_powergating_state(
			(void *)adev, state);
		if (r)
			DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1300 1301 1302 1303
	}
	return r;
}

1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315
void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
			adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
	}
}

1316 1317 1318 1319 1320 1321
int amdgpu_wait_for_idle(struct amdgpu_device *adev,
			 enum amd_ip_block_type block_type)
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1322
		if (!adev->ip_blocks[i].status.valid)
1323
			continue;
1324 1325
		if (adev->ip_blocks[i].version->type == block_type) {
			r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340
			if (r)
				return r;
			break;
		}
	}
	return 0;

}

bool amdgpu_is_idle(struct amdgpu_device *adev,
		    enum amd_ip_block_type block_type)
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1341
		if (!adev->ip_blocks[i].status.valid)
1342
			continue;
1343 1344
		if (adev->ip_blocks[i].version->type == block_type)
			return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1345 1346 1347 1348 1349
	}
	return true;

}

1350 1351
struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
					     enum amd_ip_block_type type)
A
Alex Deucher 已提交
1352 1353 1354 1355
{
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++)
1356
		if (adev->ip_blocks[i].version->type == type)
A
Alex Deucher 已提交
1357 1358 1359 1360 1361 1362 1363 1364 1365
			return &adev->ip_blocks[i];

	return NULL;
}

/**
 * amdgpu_ip_block_version_cmp
 *
 * @adev: amdgpu_device pointer
1366
 * @type: enum amd_ip_block_type
A
Alex Deucher 已提交
1367 1368 1369 1370 1371 1372 1373
 * @major: major version
 * @minor: minor version
 *
 * return 0 if equal or greater
 * return 1 if smaller or the ip_block doesn't exist
 */
int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1374
				enum amd_ip_block_type type,
A
Alex Deucher 已提交
1375 1376
				u32 major, u32 minor)
{
1377
	struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
A
Alex Deucher 已提交
1378

1379 1380 1381
	if (ip_block && ((ip_block->version->major > major) ||
			((ip_block->version->major == major) &&
			(ip_block->version->minor >= minor))))
A
Alex Deucher 已提交
1382 1383 1384 1385 1386
		return 0;

	return 1;
}

1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
/**
 * amdgpu_ip_block_add
 *
 * @adev: amdgpu_device pointer
 * @ip_block_version: pointer to the IP to add
 *
 * Adds the IP block driver information to the collection of IPs
 * on the asic.
 */
int amdgpu_ip_block_add(struct amdgpu_device *adev,
			const struct amdgpu_ip_block_version *ip_block_version)
{
	if (!ip_block_version)
		return -EINVAL;

1402 1403 1404
	DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
		  ip_block_version->funcs->name);

1405 1406 1407 1408 1409
	adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;

	return 0;
}

1410
static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1411 1412 1413 1414 1415 1416
{
	adev->enable_virtual_display = false;

	if (amdgpu_virtual_display) {
		struct drm_device *ddev = adev->ddev;
		const char *pci_address_name = pci_name(ddev->pdev);
1417
		char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1418 1419 1420

		pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
		pciaddstr_tmp = pciaddstr;
1421 1422
		while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
			pciaddname = strsep(&pciaddname_tmp, ",");
1423 1424
			if (!strcmp("all", pciaddname)
			    || !strcmp(pci_address_name, pciaddname)) {
1425 1426 1427
				long num_crtc;
				int res = -1;

1428
				adev->enable_virtual_display = true;
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442

				if (pciaddname_tmp)
					res = kstrtol(pciaddname_tmp, 10,
						      &num_crtc);

				if (!res) {
					if (num_crtc < 1)
						num_crtc = 1;
					if (num_crtc > 6)
						num_crtc = 6;
					adev->mode_info.num_crtc = num_crtc;
				} else {
					adev->mode_info.num_crtc = 1;
				}
1443 1444 1445 1446
				break;
			}
		}

1447 1448 1449
		DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
			 amdgpu_virtual_display, pci_address_name,
			 adev->enable_virtual_display, adev->mode_info.num_crtc);
1450 1451 1452 1453 1454

		kfree(pciaddstr);
	}
}

1455 1456 1457 1458 1459 1460 1461
static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
{
	const char *chip_name;
	char fw_name[30];
	int err;
	const struct gpu_info_firmware_header_v1_0 *hdr;

1462 1463
	adev->firmware.gpu_info_fw = NULL;

1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
	switch (adev->asic_type) {
	case CHIP_TOPAZ:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
	case CHIP_POLARIS12:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
#ifdef CONFIG_DRM_AMDGPU_SI
	case CHIP_VERDE:
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_OLAND:
	case CHIP_HAINAN:
#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
#endif
	default:
		return 0;
	case CHIP_VEGA10:
		chip_name = "vega10";
		break;
1492 1493 1494
	case CHIP_RAVEN:
		chip_name = "raven";
		break;
1495 1496 1497
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1498
	err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1499 1500 1501 1502 1503 1504
	if (err) {
		dev_err(adev->dev,
			"Failed to load gpu_info firmware \"%s\"\n",
			fw_name);
		goto out;
	}
1505
	err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1506 1507 1508 1509 1510 1511 1512
	if (err) {
		dev_err(adev->dev,
			"Failed to validate gpu_info firmware \"%s\"\n",
			fw_name);
		goto out;
	}

1513
	hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1514 1515 1516 1517 1518 1519
	amdgpu_ucode_print_gpu_info_hdr(&hdr->header);

	switch (hdr->version_major) {
	case 1:
	{
		const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1520
			(const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1521 1522
								le32_to_cpu(hdr->header.ucode_array_offset_bytes));

1523 1524 1525 1526
		adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
		adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
		adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
		adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1527
		adev->gfx.config.max_texture_channel_caches =
1528 1529 1530 1531 1532
			le32_to_cpu(gpu_info_fw->gc_num_tccs);
		adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
		adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
		adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
		adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1533
		adev->gfx.config.double_offchip_lds_buf =
1534 1535
			le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
		adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1536 1537 1538 1539 1540
		adev->gfx.cu_info.max_waves_per_simd =
			le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
		adev->gfx.cu_info.max_scratch_slots_per_cu =
			le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
		adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552
		break;
	}
	default:
		dev_err(adev->dev,
			"Unsupported gpu_info table %d\n", hdr->header.ucode_version);
		err = -EINVAL;
		goto out;
	}
out:
	return err;
}

A
Alex Deucher 已提交
1553 1554
static int amdgpu_early_init(struct amdgpu_device *adev)
{
1555
	int i, r;
A
Alex Deucher 已提交
1556

1557
	amdgpu_device_enable_virtual_display(adev);
1558

A
Alex Deucher 已提交
1559
	switch (adev->asic_type) {
1560 1561
	case CHIP_TOPAZ:
	case CHIP_TONGA:
1562
	case CHIP_FIJI:
1563 1564
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
1565
	case CHIP_POLARIS12:
1566
	case CHIP_CARRIZO:
1567 1568
	case CHIP_STONEY:
		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1569 1570 1571 1572 1573 1574 1575 1576
			adev->family = AMDGPU_FAMILY_CZ;
		else
			adev->family = AMDGPU_FAMILY_VI;

		r = vi_set_ip_blocks(adev);
		if (r)
			return r;
		break;
K
Ken Wang 已提交
1577 1578 1579 1580 1581 1582
#ifdef CONFIG_DRM_AMDGPU_SI
	case CHIP_VERDE:
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_OLAND:
	case CHIP_HAINAN:
K
Ken Wang 已提交
1583
		adev->family = AMDGPU_FAMILY_SI;
K
Ken Wang 已提交
1584 1585 1586 1587 1588
		r = si_set_ip_blocks(adev);
		if (r)
			return r;
		break;
#endif
1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
		if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
			adev->family = AMDGPU_FAMILY_CI;
		else
			adev->family = AMDGPU_FAMILY_KV;

		r = cik_set_ip_blocks(adev);
		if (r)
			return r;
		break;
#endif
1605 1606 1607 1608 1609 1610
	case  CHIP_VEGA10:
	case  CHIP_RAVEN:
		if (adev->asic_type == CHIP_RAVEN)
			adev->family = AMDGPU_FAMILY_RV;
		else
			adev->family = AMDGPU_FAMILY_AI;
1611 1612 1613 1614 1615

		r = soc15_set_ip_blocks(adev);
		if (r)
			return r;
		break;
A
Alex Deucher 已提交
1616 1617 1618 1619 1620
	default:
		/* FIXME: not supported yet */
		return -EINVAL;
	}

1621 1622 1623 1624
	r = amdgpu_device_parse_gpu_info_fw(adev);
	if (r)
		return r;

1625 1626 1627 1628 1629 1630
	if (amdgpu_sriov_vf(adev)) {
		r = amdgpu_virt_request_full_gpu(adev, true);
		if (r)
			return r;
	}

A
Alex Deucher 已提交
1631 1632
	for (i = 0; i < adev->num_ip_blocks; i++) {
		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1633 1634
			DRM_ERROR("disabled ip block: %d <%s>\n",
				  i, adev->ip_blocks[i].version->funcs->name);
1635
			adev->ip_blocks[i].status.valid = false;
A
Alex Deucher 已提交
1636
		} else {
1637 1638
			if (adev->ip_blocks[i].version->funcs->early_init) {
				r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1639
				if (r == -ENOENT) {
1640
					adev->ip_blocks[i].status.valid = false;
1641
				} else if (r) {
1642 1643
					DRM_ERROR("early_init of IP block <%s> failed %d\n",
						  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1644
					return r;
1645
				} else {
1646
					adev->ip_blocks[i].status.valid = true;
1647
				}
1648
			} else {
1649
				adev->ip_blocks[i].status.valid = true;
A
Alex Deucher 已提交
1650 1651 1652 1653
			}
		}
	}

1654 1655 1656
	adev->cg_flags &= amdgpu_cg_mask;
	adev->pg_flags &= amdgpu_pg_mask;

A
Alex Deucher 已提交
1657 1658 1659 1660 1661 1662 1663 1664
	return 0;
}

static int amdgpu_init(struct amdgpu_device *adev)
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1665
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
1666
			continue;
1667
		r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1668
		if (r) {
1669 1670
			DRM_ERROR("sw_init of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1671
			return r;
1672
		}
1673
		adev->ip_blocks[i].status.sw = true;
A
Alex Deucher 已提交
1674
		/* need to do gmc hw init early so we can allocate gpu mem */
1675
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
A
Alex Deucher 已提交
1676
			r = amdgpu_vram_scratch_init(adev);
1677 1678
			if (r) {
				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
A
Alex Deucher 已提交
1679
				return r;
1680
			}
1681
			r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1682 1683
			if (r) {
				DRM_ERROR("hw_init %d failed %d\n", i, r);
A
Alex Deucher 已提交
1684
				return r;
1685
			}
A
Alex Deucher 已提交
1686
			r = amdgpu_wb_init(adev);
1687 1688
			if (r) {
				DRM_ERROR("amdgpu_wb_init failed %d\n", r);
A
Alex Deucher 已提交
1689
				return r;
1690
			}
1691
			adev->ip_blocks[i].status.hw = true;
M
Monk Liu 已提交
1692 1693 1694 1695 1696 1697 1698 1699 1700

			/* right after GMC hw init, we create CSA */
			if (amdgpu_sriov_vf(adev)) {
				r = amdgpu_allocate_static_csa(adev);
				if (r) {
					DRM_ERROR("allocate CSA failed %d\n", r);
					return r;
				}
			}
A
Alex Deucher 已提交
1701 1702 1703 1704
		}
	}

	for (i = 0; i < adev->num_ip_blocks; i++) {
1705
		if (!adev->ip_blocks[i].status.sw)
A
Alex Deucher 已提交
1706 1707
			continue;
		/* gmc hw init is done early */
1708
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
A
Alex Deucher 已提交
1709
			continue;
1710
		r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1711
		if (r) {
1712 1713
			DRM_ERROR("hw_init of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
1714
			return r;
1715
		}
1716
		adev->ip_blocks[i].status.hw = true;
A
Alex Deucher 已提交
1717 1718 1719 1720 1721
	}

	return 0;
}

1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732
static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
{
	memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
}

static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
{
	return !!memcmp(adev->gart.ptr, adev->reset_magic,
			AMDGPU_RESET_MAGIC_NUM);
}

1733
static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1734 1735 1736 1737
{
	int i = 0, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
1738
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
1739
			continue;
1740
		/* skip CG for VCE/UVD, it's handled specially */
1741 1742
		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1743
			/* enable clockgating to save power */
1744 1745
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
										     AMD_CG_STATE_GATE);
1746 1747
			if (r) {
				DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1748
					  adev->ip_blocks[i].version->funcs->name, r);
1749 1750
				return r;
			}
1751
		}
A
Alex Deucher 已提交
1752
	}
1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775
	return 0;
}

static int amdgpu_late_init(struct amdgpu_device *adev)
{
	int i = 0, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		if (adev->ip_blocks[i].version->funcs->late_init) {
			r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
			if (r) {
				DRM_ERROR("late_init of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
			adev->ip_blocks[i].status.late_initialized = true;
		}
	}

	mod_delayed_work(system_wq, &adev->late_init_work,
			msecs_to_jiffies(AMDGPU_RESUME_MS));
A
Alex Deucher 已提交
1776

1777
	amdgpu_fill_reset_magic(adev);
A
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1778 1779 1780 1781 1782 1783 1784 1785

	return 0;
}

static int amdgpu_fini(struct amdgpu_device *adev)
{
	int i, r;

1786 1787
	/* need to disable SMC first */
	for (i = 0; i < adev->num_ip_blocks; i++) {
1788
		if (!adev->ip_blocks[i].status.hw)
1789
			continue;
1790
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1791
			/* ungate blocks before hw fini so that we can shutdown the blocks safely */
1792 1793
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
										     AMD_CG_STATE_UNGATE);
1794 1795
			if (r) {
				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1796
					  adev->ip_blocks[i].version->funcs->name, r);
1797 1798
				return r;
			}
1799
			r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1800 1801 1802
			/* XXX handle errors */
			if (r) {
				DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1803
					  adev->ip_blocks[i].version->funcs->name, r);
1804
			}
1805
			adev->ip_blocks[i].status.hw = false;
1806 1807 1808 1809
			break;
		}
	}

A
Alex Deucher 已提交
1810
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1811
		if (!adev->ip_blocks[i].status.hw)
A
Alex Deucher 已提交
1812
			continue;
1813
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
A
Alex Deucher 已提交
1814 1815 1816
			amdgpu_wb_fini(adev);
			amdgpu_vram_scratch_fini(adev);
		}
1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827

		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
			adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
			/* ungate blocks before hw fini so that we can shutdown the blocks safely */
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
										     AMD_CG_STATE_UNGATE);
			if (r) {
				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
1828
		}
1829

1830
		r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
A
Alex Deucher 已提交
1831
		/* XXX handle errors */
1832
		if (r) {
1833 1834
			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1835
		}
1836

1837
		adev->ip_blocks[i].status.hw = false;
A
Alex Deucher 已提交
1838 1839 1840
	}

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1841
		if (!adev->ip_blocks[i].status.sw)
A
Alex Deucher 已提交
1842
			continue;
1843
		r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
A
Alex Deucher 已提交
1844
		/* XXX handle errors */
1845
		if (r) {
1846 1847
			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1848
		}
1849 1850
		adev->ip_blocks[i].status.sw = false;
		adev->ip_blocks[i].status.valid = false;
A
Alex Deucher 已提交
1851 1852
	}

M
Monk Liu 已提交
1853
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1854
		if (!adev->ip_blocks[i].status.late_initialized)
1855
			continue;
1856 1857 1858
		if (adev->ip_blocks[i].version->funcs->late_fini)
			adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
		adev->ip_blocks[i].status.late_initialized = false;
M
Monk Liu 已提交
1859 1860
	}

1861
	if (amdgpu_sriov_vf(adev))
1862
		amdgpu_virt_release_full_gpu(adev, false);
M
Monk Liu 已提交
1863

A
Alex Deucher 已提交
1864 1865 1866
	return 0;
}

1867 1868 1869 1870 1871 1872 1873
static void amdgpu_late_init_func_handler(struct work_struct *work)
{
	struct amdgpu_device *adev =
		container_of(work, struct amdgpu_device, late_init_work.work);
	amdgpu_late_set_cg_state(adev);
}

1874
int amdgpu_suspend(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1875 1876 1877
{
	int i, r;

1878 1879 1880
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_request_full_gpu(adev, false);

1881 1882 1883 1884 1885 1886 1887
	/* ungate SMC block first */
	r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
					 AMD_CG_STATE_UNGATE);
	if (r) {
		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
	}

A
Alex Deucher 已提交
1888
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1889
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
1890 1891
			continue;
		/* ungate blocks so that suspend can properly shut them down */
1892
		if (i != AMD_IP_BLOCK_TYPE_SMC) {
1893 1894
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
										     AMD_CG_STATE_UNGATE);
1895
			if (r) {
1896 1897
				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
1898
			}
1899
		}
A
Alex Deucher 已提交
1900
		/* XXX handle errors */
1901
		r = adev->ip_blocks[i].version->funcs->suspend(adev);
A
Alex Deucher 已提交
1902
		/* XXX handle errors */
1903
		if (r) {
1904 1905
			DRM_ERROR("suspend of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
1906
		}
A
Alex Deucher 已提交
1907 1908
	}

1909 1910 1911
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_release_full_gpu(adev, false);

A
Alex Deucher 已提交
1912 1913 1914
	return 0;
}

1915
static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1916 1917 1918
{
	int i, r;

1919 1920 1921 1922 1923
	static enum amd_ip_block_type ip_order[] = {
		AMD_IP_BLOCK_TYPE_GMC,
		AMD_IP_BLOCK_TYPE_COMMON,
		AMD_IP_BLOCK_TYPE_IH,
	};
1924

1925 1926 1927
	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
		int j;
		struct amdgpu_ip_block *block;
1928

1929 1930 1931 1932 1933 1934 1935 1936 1937
		for (j = 0; j < adev->num_ip_blocks; j++) {
			block = &adev->ip_blocks[j];

			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				continue;

			r = block->version->funcs->hw_init(adev);
			DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1938 1939 1940 1941 1942 1943
		}
	}

	return 0;
}

1944
static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1945 1946 1947
{
	int i, r;

1948 1949
	static enum amd_ip_block_type ip_order[] = {
		AMD_IP_BLOCK_TYPE_SMC,
M
Monk Liu 已提交
1950
		AMD_IP_BLOCK_TYPE_PSP,
1951 1952 1953
		AMD_IP_BLOCK_TYPE_DCE,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_IP_BLOCK_TYPE_SDMA,
1954 1955
		AMD_IP_BLOCK_TYPE_UVD,
		AMD_IP_BLOCK_TYPE_VCE
1956
	};
1957

1958 1959 1960
	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
		int j;
		struct amdgpu_ip_block *block;
1961

1962 1963 1964 1965 1966 1967 1968 1969 1970
		for (j = 0; j < adev->num_ip_blocks; j++) {
			block = &adev->ip_blocks[j];

			if (block->version->type != ip_order[i] ||
				!block->status.valid)
				continue;

			r = block->version->funcs->hw_init(adev);
			DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1971 1972 1973 1974 1975 1976
		}
	}

	return 0;
}

1977
static int amdgpu_resume_phase1(struct amdgpu_device *adev)
A
Alex Deucher 已提交
1978 1979 1980
{
	int i, r;

1981 1982 1983 1984 1985
	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1986 1987 1988 1989 1990 1991 1992 1993
				adev->ip_blocks[i].version->type ==
				AMD_IP_BLOCK_TYPE_IH) {
			r = adev->ip_blocks[i].version->funcs->resume(adev);
			if (r) {
				DRM_ERROR("resume of IP block <%s> failed %d\n",
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
1994 1995 1996 1997 1998 1999
		}
	}

	return 0;
}

2000
static int amdgpu_resume_phase2(struct amdgpu_device *adev)
A
Alex Deucher 已提交
2001 2002 2003 2004
{
	int i, r;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2005
		if (!adev->ip_blocks[i].status.valid)
A
Alex Deucher 已提交
2006
			continue;
2007 2008 2009 2010
		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
			continue;
2011
		r = adev->ip_blocks[i].version->funcs->resume(adev);
2012
		if (r) {
2013 2014
			DRM_ERROR("resume of IP block <%s> failed %d\n",
				  adev->ip_blocks[i].version->funcs->name, r);
A
Alex Deucher 已提交
2015
			return r;
2016
		}
A
Alex Deucher 已提交
2017 2018 2019 2020 2021
	}

	return 0;
}

2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033
static int amdgpu_resume(struct amdgpu_device *adev)
{
	int r;

	r = amdgpu_resume_phase1(adev);
	if (r)
		return r;
	r = amdgpu_resume_phase2(adev);

	return r;
}

2034
static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2035
{
M
Monk Liu 已提交
2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046
	if (amdgpu_sriov_vf(adev)) {
		if (adev->is_atom_fw) {
			if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
		} else {
			if (amdgpu_atombios_has_gpu_virtualization_table(adev))
				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
		}

		if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2047
	}
2048 2049
}

2050 2051 2052 2053 2054 2055
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
{
	switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
2056
	case CHIP_KAVERI:
2057 2058 2059 2060
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
2061
	case CHIP_POLARIS12:
2062 2063 2064 2065 2066
	case CHIP_TONGA:
	case CHIP_FIJI:
#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
		return amdgpu_dc != 0;
#endif
2067 2068 2069
	case CHIP_KABINI:
	case CHIP_MULLINS:
		return amdgpu_dc > 0;
2070 2071
	case CHIP_VEGA10:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2072
	case CHIP_RAVEN:
2073
#endif
2074
		return amdgpu_dc != 0;
2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
#endif
	default:
		return false;
	}
}

/**
 * amdgpu_device_has_dc_support - check if dc is supported
 *
 * @adev: amdgpu_device_pointer
 *
 * Returns true for supported, false for not supported
 */
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
{
X
Xiangliang Yu 已提交
2090 2091 2092
	if (amdgpu_sriov_vf(adev))
		return false;

2093 2094 2095
	return amdgpu_device_asic_has_dc_support(adev->asic_type);
}

A
Alex Deucher 已提交
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114
/**
 * amdgpu_device_init - initialize the driver
 *
 * @adev: amdgpu_device pointer
 * @pdev: drm dev pointer
 * @pdev: pci dev pointer
 * @flags: driver flags
 *
 * Initializes the driver info and hw (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver startup.
 */
int amdgpu_device_init(struct amdgpu_device *adev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags)
{
	int r, i;
	bool runtime = false;
2115
	u32 max_MBps;
A
Alex Deucher 已提交
2116 2117 2118 2119 2120 2121

	adev->shutdown = false;
	adev->dev = &pdev->dev;
	adev->ddev = ddev;
	adev->pdev = pdev;
	adev->flags = flags;
2122
	adev->asic_type = flags & AMD_ASIC_MASK;
A
Alex Deucher 已提交
2123
	adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2124
	adev->mc.gart_size = 512 * 1024 * 1024;
A
Alex Deucher 已提交
2125 2126 2127 2128 2129
	adev->accel_working = false;
	adev->num_rings = 0;
	adev->mman.buffer_funcs = NULL;
	adev->mman.buffer_funcs_ring = NULL;
	adev->vm_manager.vm_pte_funcs = NULL;
2130
	adev->vm_manager.vm_pte_num_rings = 0;
A
Alex Deucher 已提交
2131
	adev->gart.gart_funcs = NULL;
2132
	adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2133
	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
A
Alex Deucher 已提交
2134 2135 2136 2137 2138

	adev->smc_rreg = &amdgpu_invalid_rreg;
	adev->smc_wreg = &amdgpu_invalid_wreg;
	adev->pcie_rreg = &amdgpu_invalid_rreg;
	adev->pcie_wreg = &amdgpu_invalid_wreg;
2139 2140
	adev->pciep_rreg = &amdgpu_invalid_rreg;
	adev->pciep_wreg = &amdgpu_invalid_wreg;
A
Alex Deucher 已提交
2141 2142 2143 2144
	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
	adev->didt_rreg = &amdgpu_invalid_rreg;
	adev->didt_wreg = &amdgpu_invalid_wreg;
2145 2146
	adev->gc_cac_rreg = &amdgpu_invalid_rreg;
	adev->gc_cac_wreg = &amdgpu_invalid_wreg;
A
Alex Deucher 已提交
2147 2148 2149
	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;

2150 2151 2152
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
		 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
A
Alex Deucher 已提交
2153 2154 2155 2156

	/* mutex initialization are all done here so we
	 * can recall function without having locking issues */
	atomic_set(&adev->irq.ih.lock, 0);
2157
	mutex_init(&adev->firmware.mutex);
A
Alex Deucher 已提交
2158 2159 2160
	mutex_init(&adev->pm.mutex);
	mutex_init(&adev->gfx.gpu_clock_mutex);
	mutex_init(&adev->srbm_mutex);
2161
	mutex_init(&adev->gfx.pipe_reserve_mutex);
A
Alex Deucher 已提交
2162 2163
	mutex_init(&adev->grbm_idx_mutex);
	mutex_init(&adev->mn_lock);
A
Alex Deucher 已提交
2164
	mutex_init(&adev->virt.vf_errors.lock);
A
Alex Deucher 已提交
2165
	hash_init(adev->mn_hash);
2166
	mutex_init(&adev->lock_reset);
A
Alex Deucher 已提交
2167 2168 2169 2170 2171 2172 2173 2174

	amdgpu_check_arguments(adev);

	spin_lock_init(&adev->mmio_idx_lock);
	spin_lock_init(&adev->smc_idx_lock);
	spin_lock_init(&adev->pcie_idx_lock);
	spin_lock_init(&adev->uvd_ctx_idx_lock);
	spin_lock_init(&adev->didt_idx_lock);
2175
	spin_lock_init(&adev->gc_cac_idx_lock);
2176
	spin_lock_init(&adev->se_cac_idx_lock);
A
Alex Deucher 已提交
2177
	spin_lock_init(&adev->audio_endpt_idx_lock);
2178
	spin_lock_init(&adev->mm_stats.lock);
A
Alex Deucher 已提交
2179

2180 2181 2182
	INIT_LIST_HEAD(&adev->shadow_list);
	mutex_init(&adev->shadow_list_lock);

2183 2184 2185
	INIT_LIST_HEAD(&adev->gtt_list);
	spin_lock_init(&adev->gtt_list_lock);

2186 2187 2188
	INIT_LIST_HEAD(&adev->ring_lru_list);
	spin_lock_init(&adev->ring_lru_list_lock);

2189 2190
	INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);

2191 2192
	/* Registers mapping */
	/* TODO: block userspace mapping of io register */
2193 2194 2195 2196 2197 2198 2199
	if (adev->asic_type >= CHIP_BONAIRE) {
		adev->rmmio_base = pci_resource_start(adev->pdev, 5);
		adev->rmmio_size = pci_resource_len(adev->pdev, 5);
	} else {
		adev->rmmio_base = pci_resource_start(adev->pdev, 2);
		adev->rmmio_size = pci_resource_len(adev->pdev, 2);
	}
A
Alex Deucher 已提交
2200 2201 2202 2203 2204 2205 2206 2207

	adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
	if (adev->rmmio == NULL) {
		return -ENOMEM;
	}
	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
	DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);

2208 2209
	/* doorbell bar mapping */
	amdgpu_doorbell_init(adev);
A
Alex Deucher 已提交
2210 2211 2212 2213 2214 2215 2216 2217 2218 2219

	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
			adev->rio_mem_size = pci_resource_len(adev->pdev, i);
			adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
			break;
		}
	}
	if (adev->rio_mem == NULL)
2220
		DRM_INFO("PCI I/O BAR is not found.\n");
A
Alex Deucher 已提交
2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233

	/* early init functions */
	r = amdgpu_early_init(adev);
	if (r)
		return r;

	/* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
	/* this will fail for cards that aren't VGA class devices, just
	 * ignore it */
	vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);

	if (amdgpu_runtime_pm == 1)
		runtime = true;
2234
	if (amdgpu_device_is_px(ddev))
A
Alex Deucher 已提交
2235
		runtime = true;
2236 2237 2238
	if (!pci_is_thunderbolt_attached(adev->pdev))
		vga_switcheroo_register_client(adev->pdev,
					       &amdgpu_switcheroo_ops, runtime);
A
Alex Deucher 已提交
2239 2240 2241 2242
	if (runtime)
		vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);

	/* Read BIOS */
2243 2244 2245 2246
	if (!amdgpu_get_bios(adev)) {
		r = -EINVAL;
		goto failed;
	}
2247

A
Alex Deucher 已提交
2248
	r = amdgpu_atombios_init(adev);
2249 2250
	if (r) {
		dev_err(adev->dev, "amdgpu_atombios_init failed\n");
A
Alex Deucher 已提交
2251
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2252
		goto failed;
2253
	}
A
Alex Deucher 已提交
2254

2255 2256
	/* detect if we are with an SRIOV vbios */
	amdgpu_device_detect_sriov_bios(adev);
2257

A
Alex Deucher 已提交
2258
	/* Post card if necessary */
2259
	if (amdgpu_need_post(adev)) {
A
Alex Deucher 已提交
2260
		if (!adev->bios) {
2261
			dev_err(adev->dev, "no vBIOS found\n");
2262 2263
			r = -EINVAL;
			goto failed;
A
Alex Deucher 已提交
2264
		}
2265
		DRM_INFO("GPU posting now...\n");
2266 2267 2268 2269 2270
		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
		if (r) {
			dev_err(adev->dev, "gpu post error!\n");
			goto failed;
		}
A
Alex Deucher 已提交
2271 2272
	}

2273 2274 2275 2276 2277
	if (adev->is_atom_fw) {
		/* Initialize clocks */
		r = amdgpu_atomfirmware_get_clock_info(adev);
		if (r) {
			dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
A
Alex Deucher 已提交
2278
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2279 2280 2281
			goto failed;
		}
	} else {
2282 2283 2284 2285
		/* Initialize clocks */
		r = amdgpu_atombios_get_clock_info(adev);
		if (r) {
			dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
A
Alex Deucher 已提交
2286
			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2287
			goto failed;
2288 2289
		}
		/* init i2c buses */
2290 2291
		if (!amdgpu_device_has_dc_support(adev))
			amdgpu_atombios_i2c_init(adev);
2292
	}
A
Alex Deucher 已提交
2293 2294 2295

	/* Fence driver */
	r = amdgpu_fence_driver_init(adev);
2296 2297
	if (r) {
		dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
A
Alex Deucher 已提交
2298
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2299
		goto failed;
2300
	}
A
Alex Deucher 已提交
2301 2302 2303 2304 2305 2306

	/* init the mode config */
	drm_mode_config_init(adev->ddev);

	r = amdgpu_init(adev);
	if (r) {
2307 2308 2309 2310 2311 2312 2313 2314 2315
		/* failed in exclusive mode due to timeout */
		if (amdgpu_sriov_vf(adev) &&
		    !amdgpu_sriov_runtime(adev) &&
		    amdgpu_virt_mmio_blocked(adev) &&
		    !amdgpu_virt_wait_reset(adev)) {
			dev_err(adev->dev, "VF exclusive mode timeout\n");
			r = -EAGAIN;
			goto failed;
		}
2316
		dev_err(adev->dev, "amdgpu_init failed\n");
A
Alex Deucher 已提交
2317
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
A
Alex Deucher 已提交
2318
		amdgpu_fini(adev);
2319
		goto failed;
A
Alex Deucher 已提交
2320 2321 2322 2323
	}

	adev->accel_working = true;

2324 2325
	amdgpu_vm_check_compute_bug(adev);

2326 2327 2328 2329 2330 2331 2332 2333
	/* Initialize the buffer migration limit. */
	if (amdgpu_moverate >= 0)
		max_MBps = amdgpu_moverate;
	else
		max_MBps = 8; /* Allow 8 MB/s. */
	/* Get a log2 for easy divisions. */
	adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));

A
Alex Deucher 已提交
2334 2335 2336
	r = amdgpu_ib_pool_init(adev);
	if (r) {
		dev_err(adev->dev, "IB initialization failed (%d).\n", r);
A
Alex Deucher 已提交
2337
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2338
		goto failed;
A
Alex Deucher 已提交
2339 2340 2341 2342 2343 2344
	}

	r = amdgpu_ib_ring_tests(adev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);

2345 2346 2347
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_init_data_exchange(adev);

2348 2349
	amdgpu_fbdev_init(adev);

2350 2351 2352 2353
	r = amdgpu_pm_sysfs_init(adev);
	if (r)
		DRM_ERROR("registering pm debugfs failed (%d).\n", r);

A
Alex Deucher 已提交
2354
	r = amdgpu_gem_debugfs_init(adev);
M
Monk Liu 已提交
2355
	if (r)
A
Alex Deucher 已提交
2356 2357 2358
		DRM_ERROR("registering gem debugfs failed (%d).\n", r);

	r = amdgpu_debugfs_regs_init(adev);
M
Monk Liu 已提交
2359
	if (r)
A
Alex Deucher 已提交
2360 2361
		DRM_ERROR("registering register debugfs failed (%d).\n", r);

2362 2363 2364 2365
	r = amdgpu_debugfs_test_ib_ring_init(adev);
	if (r)
		DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);

2366
	r = amdgpu_debugfs_firmware_init(adev);
M
Monk Liu 已提交
2367
	if (r)
2368 2369
		DRM_ERROR("registering firmware debugfs failed (%d).\n", r);

2370 2371 2372 2373
	r = amdgpu_debugfs_vbios_dump_init(adev);
	if (r)
		DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);

A
Alex Deucher 已提交
2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
	if ((amdgpu_testing & 1)) {
		if (adev->accel_working)
			amdgpu_test_moves(adev);
		else
			DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
	}
	if (amdgpu_benchmarking) {
		if (adev->accel_working)
			amdgpu_benchmark(adev, amdgpu_benchmarking);
		else
			DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
	}

	/* enable clockgating, etc. after ib tests, etc. since some blocks require
	 * explicit gating rather than handling it automatically.
	 */
	r = amdgpu_late_init(adev);
2391 2392
	if (r) {
		dev_err(adev->dev, "amdgpu_late_init failed\n");
A
Alex Deucher 已提交
2393
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2394
		goto failed;
2395
	}
A
Alex Deucher 已提交
2396 2397

	return 0;
2398 2399

failed:
2400
	amdgpu_vf_error_trans_all(adev);
2401 2402
	if (runtime)
		vga_switcheroo_fini_domain_pm_ops(adev->dev);
2403

2404
	return r;
A
Alex Deucher 已提交
2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420
}

/**
 * amdgpu_device_fini - tear down the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Tear down the driver info (all asics).
 * Called at driver shutdown.
 */
void amdgpu_device_fini(struct amdgpu_device *adev)
{
	int r;

	DRM_INFO("amdgpu: finishing device.\n");
	adev->shutdown = true;
2421 2422
	if (adev->mode_info.mode_config_initialized)
		drm_crtc_force_disable_all(adev->ddev);
A
Alex Deucher 已提交
2423 2424 2425
	/* evict vram memory */
	amdgpu_bo_evict_vram(adev);
	amdgpu_ib_pool_fini(adev);
2426
	amdgpu_fw_reserve_vram_fini(adev);
A
Alex Deucher 已提交
2427 2428 2429
	amdgpu_fence_driver_fini(adev);
	amdgpu_fbdev_fini(adev);
	r = amdgpu_fini(adev);
2430 2431 2432 2433
	if (adev->firmware.gpu_info_fw) {
		release_firmware(adev->firmware.gpu_info_fw);
		adev->firmware.gpu_info_fw = NULL;
	}
A
Alex Deucher 已提交
2434
	adev->accel_working = false;
2435
	cancel_delayed_work_sync(&adev->late_init_work);
A
Alex Deucher 已提交
2436
	/* free i2c buses */
2437 2438
	if (!amdgpu_device_has_dc_support(adev))
		amdgpu_i2c_fini(adev);
A
Alex Deucher 已提交
2439 2440 2441
	amdgpu_atombios_fini(adev);
	kfree(adev->bios);
	adev->bios = NULL;
2442 2443
	if (!pci_is_thunderbolt_attached(adev->pdev))
		vga_switcheroo_unregister_client(adev->pdev);
2444 2445
	if (adev->flags & AMD_IS_PX)
		vga_switcheroo_fini_domain_pm_ops(adev->dev);
A
Alex Deucher 已提交
2446 2447 2448 2449 2450 2451
	vga_client_register(adev->pdev, NULL, NULL, NULL);
	if (adev->rio_mem)
		pci_iounmap(adev->pdev, adev->rio_mem);
	adev->rio_mem = NULL;
	iounmap(adev->rmmio);
	adev->rmmio = NULL;
2452
	amdgpu_doorbell_fini(adev);
2453
	amdgpu_pm_sysfs_fini(adev);
A
Alex Deucher 已提交
2454 2455 2456 2457 2458 2459 2460 2461
	amdgpu_debugfs_regs_cleanup(adev);
}


/*
 * Suspend & resume.
 */
/**
2462
 * amdgpu_device_suspend - initiate device suspend
A
Alex Deucher 已提交
2463 2464 2465 2466 2467 2468 2469 2470
 *
 * @pdev: drm dev pointer
 * @state: suspend state
 *
 * Puts the hw in the suspend state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver suspend.
 */
2471
int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
A
Alex Deucher 已提交
2472 2473 2474 2475
{
	struct amdgpu_device *adev;
	struct drm_crtc *crtc;
	struct drm_connector *connector;
2476
	int r;
A
Alex Deucher 已提交
2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488

	if (dev == NULL || dev->dev_private == NULL) {
		return -ENODEV;
	}

	adev = dev->dev_private;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	drm_kms_helper_poll_disable(dev);

2489 2490 2491 2492 2493 2494 2495
	if (!amdgpu_device_has_dc_support(adev)) {
		/* turn off display hw */
		drm_modeset_lock_all(dev);
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
		}
		drm_modeset_unlock_all(dev);
A
Alex Deucher 已提交
2496 2497
	}

2498 2499
	amdgpu_amdkfd_suspend(adev);

2500
	/* unpin the front buffers and cursors */
A
Alex Deucher 已提交
2501
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2502
		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
A
Alex Deucher 已提交
2503 2504 2505
		struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
		struct amdgpu_bo *robj;

2506 2507
		if (amdgpu_crtc->cursor_bo) {
			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2508
			r = amdgpu_bo_reserve(aobj, true);
2509 2510 2511 2512 2513 2514
			if (r == 0) {
				amdgpu_bo_unpin(aobj);
				amdgpu_bo_unreserve(aobj);
			}
		}

A
Alex Deucher 已提交
2515 2516 2517 2518 2519 2520
		if (rfb == NULL || rfb->obj == NULL) {
			continue;
		}
		robj = gem_to_amdgpu_bo(rfb->obj);
		/* don't unpin kernel fb objects */
		if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2521
			r = amdgpu_bo_reserve(robj, true);
A
Alex Deucher 已提交
2522 2523 2524 2525 2526 2527 2528 2529 2530
			if (r == 0) {
				amdgpu_bo_unpin(robj);
				amdgpu_bo_unreserve(robj);
			}
		}
	}
	/* evict vram memory */
	amdgpu_bo_evict_vram(adev);

2531
	amdgpu_fence_driver_suspend(adev);
A
Alex Deucher 已提交
2532 2533 2534

	r = amdgpu_suspend(adev);

2535 2536 2537 2538
	/* evict remaining vram memory
	 * This second call to evict vram is to evict the gart page table
	 * using the CPU.
	 */
A
Alex Deucher 已提交
2539 2540
	amdgpu_bo_evict_vram(adev);

2541
	amdgpu_atombios_scratch_regs_save(adev);
A
Alex Deucher 已提交
2542 2543 2544 2545 2546
	pci_save_state(dev->pdev);
	if (suspend) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
J
jimqu 已提交
2547 2548 2549 2550
	} else {
		r = amdgpu_asic_reset(adev);
		if (r)
			DRM_ERROR("amdgpu asic reset failed\n");
A
Alex Deucher 已提交
2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561
	}

	if (fbcon) {
		console_lock();
		amdgpu_fbdev_set_suspend(adev, 1);
		console_unlock();
	}
	return 0;
}

/**
2562
 * amdgpu_device_resume - initiate device resume
A
Alex Deucher 已提交
2563 2564 2565 2566 2567 2568 2569
 *
 * @pdev: drm dev pointer
 *
 * Bring the hw back to operating state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver resume.
 */
2570
int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
A
Alex Deucher 已提交
2571 2572 2573
{
	struct drm_connector *connector;
	struct amdgpu_device *adev = dev->dev_private;
2574
	struct drm_crtc *crtc;
2575
	int r = 0;
A
Alex Deucher 已提交
2576 2577 2578 2579

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

J
jimqu 已提交
2580
	if (fbcon)
A
Alex Deucher 已提交
2581
		console_lock();
J
jimqu 已提交
2582

A
Alex Deucher 已提交
2583 2584 2585
	if (resume) {
		pci_set_power_state(dev->pdev, PCI_D0);
		pci_restore_state(dev->pdev);
J
jimqu 已提交
2586
		r = pci_enable_device(dev->pdev);
2587 2588
		if (r)
			goto unlock;
A
Alex Deucher 已提交
2589
	}
2590
	amdgpu_atombios_scratch_regs_restore(adev);
A
Alex Deucher 已提交
2591 2592

	/* post card */
2593
	if (amdgpu_need_post(adev)) {
J
jimqu 已提交
2594 2595 2596 2597
		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
		if (r)
			DRM_ERROR("amdgpu asic init failed\n");
	}
A
Alex Deucher 已提交
2598 2599

	r = amdgpu_resume(adev);
2600
	if (r) {
F
Flora Cui 已提交
2601
		DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2602
		goto unlock;
2603
	}
2604 2605
	amdgpu_fence_driver_resume(adev);

F
Flora Cui 已提交
2606 2607 2608 2609 2610
	if (resume) {
		r = amdgpu_ib_ring_tests(adev);
		if (r)
			DRM_ERROR("ib ring test failed (%d).\n", r);
	}
A
Alex Deucher 已提交
2611 2612

	r = amdgpu_late_init(adev);
2613 2614
	if (r)
		goto unlock;
A
Alex Deucher 已提交
2615

2616 2617 2618 2619 2620 2621
	/* pin cursors */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

		if (amdgpu_crtc->cursor_bo) {
			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2622
			r = amdgpu_bo_reserve(aobj, true);
2623 2624 2625 2626 2627 2628 2629 2630 2631 2632
			if (r == 0) {
				r = amdgpu_bo_pin(aobj,
						  AMDGPU_GEM_DOMAIN_VRAM,
						  &amdgpu_crtc->cursor_addr);
				if (r != 0)
					DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
				amdgpu_bo_unreserve(aobj);
			}
		}
	}
2633 2634 2635
	r = amdgpu_amdkfd_resume(adev);
	if (r)
		return r;
2636

A
Alex Deucher 已提交
2637 2638
	/* blat the mode back in */
	if (fbcon) {
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656
		if (!amdgpu_device_has_dc_support(adev)) {
			/* pre DCE11 */
			drm_helper_resume_force_mode(dev);

			/* turn on display hw */
			drm_modeset_lock_all(dev);
			list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
			}
			drm_modeset_unlock_all(dev);
		} else {
			/*
			 * There is no equivalent atomic helper to turn on
			 * display, so we defined our own function for this,
			 * once suspend resume is supported by the atomic
			 * framework this will be reworked
			 */
			amdgpu_dm_display_resume(adev);
A
Alex Deucher 已提交
2657 2658 2659 2660
		}
	}

	drm_kms_helper_poll_enable(dev);
2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673

	/*
	 * Most of the connector probing functions try to acquire runtime pm
	 * refs to ensure that the GPU is powered on when connector polling is
	 * performed. Since we're calling this from a runtime PM callback,
	 * trying to acquire rpm refs will cause us to deadlock.
	 *
	 * Since we're guaranteed to be holding the rpm lock, it's safe to
	 * temporarily disable the rpm helpers so this doesn't deadlock us.
	 */
#ifdef CONFIG_PM
	dev->dev->power.disable_depth++;
#endif
2674 2675 2676 2677
	if (!amdgpu_device_has_dc_support(adev))
		drm_helper_hpd_irq_event(dev);
	else
		drm_kms_helper_hotplug_event(dev);
2678 2679 2680
#ifdef CONFIG_PM
	dev->dev->power.disable_depth--;
#endif
A
Alex Deucher 已提交
2681

2682
	if (fbcon)
A
Alex Deucher 已提交
2683
		amdgpu_fbdev_set_suspend(adev, 0);
2684 2685 2686

unlock:
	if (fbcon)
A
Alex Deucher 已提交
2687 2688
		console_unlock();

2689
	return r;
A
Alex Deucher 已提交
2690 2691
}

2692 2693 2694 2695 2696
static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
{
	int i;
	bool asic_hang = false;

2697 2698 2699
	if (amdgpu_sriov_vf(adev))
		return true;

2700
	for (i = 0; i < adev->num_ip_blocks; i++) {
2701
		if (!adev->ip_blocks[i].status.valid)
2702
			continue;
2703 2704 2705 2706 2707
		if (adev->ip_blocks[i].version->funcs->check_soft_reset)
			adev->ip_blocks[i].status.hang =
				adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
		if (adev->ip_blocks[i].status.hang) {
			DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2708 2709 2710 2711 2712 2713
			asic_hang = true;
		}
	}
	return asic_hang;
}

2714
static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2715 2716 2717 2718
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2719
		if (!adev->ip_blocks[i].status.valid)
2720
			continue;
2721 2722 2723
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->pre_soft_reset) {
			r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2724 2725 2726 2727 2728 2729 2730 2731
			if (r)
				return r;
		}
	}

	return 0;
}

2732 2733
static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
{
2734 2735 2736
	int i;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2737
		if (!adev->ip_blocks[i].status.valid)
2738
			continue;
2739 2740 2741
		if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2742 2743
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2744
			if (adev->ip_blocks[i].status.hang) {
2745 2746 2747 2748
				DRM_INFO("Some block need full reset!\n");
				return true;
			}
		}
2749 2750 2751 2752 2753 2754 2755 2756 2757
	}
	return false;
}

static int amdgpu_soft_reset(struct amdgpu_device *adev)
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2758
		if (!adev->ip_blocks[i].status.valid)
2759
			continue;
2760 2761 2762
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->soft_reset) {
			r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775
			if (r)
				return r;
		}
	}

	return 0;
}

static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
2776
		if (!adev->ip_blocks[i].status.valid)
2777
			continue;
2778 2779 2780
		if (adev->ip_blocks[i].status.hang &&
		    adev->ip_blocks[i].version->funcs->post_soft_reset)
			r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2781 2782 2783 2784 2785 2786 2787
		if (r)
			return r;
	}

	return 0;
}

2788 2789 2790 2791 2792 2793 2794 2795
bool amdgpu_need_backup(struct amdgpu_device *adev)
{
	if (adev->flags & AMD_IS_APU)
		return false;

	return amdgpu_lockup_timeout > 0 ? true : false;
}

2796 2797 2798
static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
					   struct amdgpu_ring *ring,
					   struct amdgpu_bo *bo,
2799
					   struct dma_fence **fence)
2800 2801 2802 2803
{
	uint32_t domain;
	int r;

R
Roger.He 已提交
2804 2805 2806
	if (!bo->shadow)
		return 0;

2807
	r = amdgpu_bo_reserve(bo, true);
R
Roger.He 已提交
2808 2809 2810 2811 2812
	if (r)
		return r;
	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
	/* if bo has been evicted, then no need to recover */
	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2813 2814 2815 2816 2817 2818
		r = amdgpu_bo_validate(bo->shadow);
		if (r) {
			DRM_ERROR("bo validate failed!\n");
			goto err;
		}

R
Roger.He 已提交
2819
		r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2820
						 NULL, fence, true);
R
Roger.He 已提交
2821 2822 2823 2824 2825
		if (r) {
			DRM_ERROR("recover page table failed!\n");
			goto err;
		}
	}
2826
err:
R
Roger.He 已提交
2827 2828
	amdgpu_bo_unreserve(bo);
	return r;
2829 2830
}

2831 2832
/*
 * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
2833 2834
 *
 * @adev: amdgpu device pointer
2835
 * @reset_flags: output param tells caller the reset result
2836
 *
2837 2838 2839 2840
 * attempt to do soft-reset or full-reset and reinitialize Asic
 * return 0 means successed otherwise failed
*/
static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
2841
{
2842 2843
	bool need_full_reset, vram_lost = 0;
	int r;
2844

2845
	need_full_reset = amdgpu_need_full_reset(adev);
2846

2847 2848 2849 2850 2851 2852 2853 2854
	if (!need_full_reset) {
		amdgpu_pre_soft_reset(adev);
		r = amdgpu_soft_reset(adev);
		amdgpu_post_soft_reset(adev);
		if (r || amdgpu_check_soft_reset(adev)) {
			DRM_INFO("soft reset failed, will fallback to full reset!\n");
			need_full_reset = true;
		}
2855

2856
	}
2857

2858 2859
	if (need_full_reset) {
		r = amdgpu_suspend(adev);
2860

2861 2862 2863 2864 2865 2866
retry:
		amdgpu_atombios_scratch_regs_save(adev);
		r = amdgpu_asic_reset(adev);
		amdgpu_atombios_scratch_regs_restore(adev);
		/* post card */
		amdgpu_atom_asic_init(adev->mode_info.atom_context);
2867

2868 2869 2870 2871 2872
		if (!r) {
			dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
			r = amdgpu_resume_phase1(adev);
			if (r)
				goto out;
2873

2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889
			vram_lost = amdgpu_check_vram_lost(adev);
			if (vram_lost) {
				DRM_ERROR("VRAM is lost!\n");
				atomic_inc(&adev->vram_lost_counter);
			}

			r = amdgpu_ttm_recover_gart(adev);
			if (r)
				goto out;

			r = amdgpu_resume_phase2(adev);
			if (r)
				goto out;

			if (vram_lost)
				amdgpu_fill_reset_magic(adev);
2890
		}
2891
	}
2892

2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903
out:
	if (!r) {
		amdgpu_irq_gpu_reset_resume_helper(adev);
		r = amdgpu_ib_ring_tests(adev);
		if (r) {
			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
			r = amdgpu_suspend(adev);
			need_full_reset = true;
			goto retry;
		}
	}
2904

2905 2906 2907
	if (reset_flags) {
		if (vram_lost)
			(*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2908

2909 2910
		if (need_full_reset)
			(*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2911
	}
2912

2913 2914
	return r;
}
2915

2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934
/*
 * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
 *
 * @adev: amdgpu device pointer
 * @reset_flags: output param tells caller the reset result
 *
 * do VF FLR and reinitialize Asic
 * return 0 means successed otherwise failed
*/
static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
{
	int r;

	if (from_hypervisor)
		r = amdgpu_virt_request_full_gpu(adev, true);
	else
		r = amdgpu_virt_reset_gpu(adev);
	if (r)
		return r;
2935 2936

	/* Resume IP prior to SMC */
2937 2938 2939
	r = amdgpu_sriov_reinit_early(adev);
	if (r)
		goto error;
2940 2941 2942 2943 2944

	/* we need recover gart prior to run SMC/CP/SDMA resume */
	amdgpu_ttm_recover_gart(adev);

	/* now we are okay to resume SMC/CP/SDMA */
2945 2946 2947
	r = amdgpu_sriov_reinit_late(adev);
	if (r)
		goto error;
2948 2949

	amdgpu_irq_gpu_reset_resume_helper(adev);
2950 2951
	r = amdgpu_ib_ring_tests(adev);
	if (r)
2952 2953
		dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);

2954
error:
2955 2956 2957
	/* release full control of GPU after ib test */
	amdgpu_virt_release_full_gpu(adev, true);

2958 2959 2960 2961 2962 2963
	if (reset_flags) {
		/* will get vram_lost from GIM in future, now all
		 * reset request considered VRAM LOST
		 */
		(*reset_flags) |= ~AMDGPU_RESET_INFO_VRAM_LOST;
		atomic_inc(&adev->vram_lost_counter);
2964

2965 2966
		/* VF FLR or hotlink reset is always full-reset */
		(*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2967 2968 2969 2970 2971
	}

	return r;
}

A
Alex Deucher 已提交
2972
/**
2973
 * amdgpu_gpu_recover - reset the asic and recover scheduler
A
Alex Deucher 已提交
2974 2975
 *
 * @adev: amdgpu device pointer
2976
 * @job: which job trigger hang
A
Alex Deucher 已提交
2977
 *
2978
 * Attempt to reset the GPU if it has hung (all asics).
A
Alex Deucher 已提交
2979 2980
 * Returns 0 for success or an error on failure.
 */
2981
int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
A
Alex Deucher 已提交
2982
{
2983
	struct drm_atomic_state *state = NULL;
2984 2985
	uint64_t reset_flags = 0;
	int i, r, resched;
2986

2987 2988 2989 2990
	if (!amdgpu_check_soft_reset(adev)) {
		DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
		return 0;
	}
A
Alex Deucher 已提交
2991

2992 2993
	dev_info(adev->dev, "GPU reset begin!\n");

2994
	mutex_lock(&adev->lock_reset);
2995
	atomic_inc(&adev->gpu_reset_counter);
2996
	adev->in_gpu_reset = 1;
A
Alex Deucher 已提交
2997

2998 2999
	/* block TTM */
	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3000 3001 3002
	/* store modesetting */
	if (amdgpu_device_has_dc_support(adev))
		state = drm_atomic_helper_suspend(adev->ddev);
3003

3004 3005 3006 3007
	/* block scheduler */
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_ring *ring = adev->rings[i];

C
Chunming Zhou 已提交
3008
		if (!ring || !ring->sched.thread)
3009
			continue;
3010 3011 3012 3013 3014

		/* only focus on the ring hit timeout if &job not NULL */
		if (job && job->ring->idx != i)
			continue;

3015
		kthread_park(ring->sched.thread);
3016 3017
		amd_sched_hw_job_reset(&ring->sched, &job->base);

M
Monk Liu 已提交
3018 3019
		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
		amdgpu_fence_driver_force_completion(ring);
3020
	}
A
Alex Deucher 已提交
3021

3022 3023 3024 3025
	if (amdgpu_sriov_vf(adev))
		r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
	else
		r = amdgpu_reset(adev, &reset_flags);
3026

A
Alex Deucher 已提交
3027
	if (!r) {
3028 3029
		if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
			(reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
3030 3031
			struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
			struct amdgpu_bo *bo, *tmp;
3032
			struct dma_fence *fence = NULL, *next = NULL;
3033 3034 3035 3036

			DRM_INFO("recover vram bo from shadow\n");
			mutex_lock(&adev->shadow_list_lock);
			list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
M
Monk Liu 已提交
3037
				next = NULL;
3038 3039
				amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
				if (fence) {
3040
					r = dma_fence_wait(fence, false);
3041
					if (r) {
M
Monk Liu 已提交
3042
						WARN(r, "recovery from shadow isn't completed\n");
3043 3044 3045
						break;
					}
				}
3046

3047
				dma_fence_put(fence);
3048 3049 3050 3051
				fence = next;
			}
			mutex_unlock(&adev->shadow_list_lock);
			if (fence) {
3052
				r = dma_fence_wait(fence, false);
3053
				if (r)
M
Monk Liu 已提交
3054
					WARN(r, "recovery from shadow isn't completed\n");
3055
			}
3056
			dma_fence_put(fence);
3057
		}
3058

A
Alex Deucher 已提交
3059 3060
		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
			struct amdgpu_ring *ring = adev->rings[i];
C
Chunming Zhou 已提交
3061 3062

			if (!ring || !ring->sched.thread)
A
Alex Deucher 已提交
3063
				continue;
3064

3065 3066 3067 3068
			/* only focus on the ring hit timeout if &job not NULL */
			if (job && job->ring->idx != i)
				continue;

3069
			amd_sched_job_recovery(&ring->sched);
3070
			kthread_unpark(ring->sched.thread);
A
Alex Deucher 已提交
3071 3072 3073
		}
	} else {
		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3074 3075 3076 3077 3078 3079 3080 3081 3082 3083
			struct amdgpu_ring *ring = adev->rings[i];

			if (!ring || !ring->sched.thread)
				continue;

			/* only focus on the ring hit timeout if &job not NULL */
			if (job && job->ring->idx != i)
				continue;

			kthread_unpark(adev->rings[i]->sched.thread);
A
Alex Deucher 已提交
3084 3085 3086
		}
	}

3087
	if (amdgpu_device_has_dc_support(adev)) {
3088 3089
		if (drm_atomic_helper_resume(adev->ddev, state))
			dev_info(adev->dev, "drm resume failed:%d\n", r);
3090
		amdgpu_dm_display_resume(adev);
3091
	} else {
3092
		drm_helper_resume_force_mode(adev->ddev);
3093
	}
A
Alex Deucher 已提交
3094 3095

	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3096

3097
	if (r) {
A
Alex Deucher 已提交
3098
		/* bad news, how to tell it to userspace ? */
3099 3100 3101 3102
		dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
	} else {
		dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
3103
	}
A
Alex Deucher 已提交
3104

3105
	amdgpu_vf_error_trans_all(adev);
3106 3107
	adev->in_gpu_reset = 0;
	mutex_unlock(&adev->lock_reset);
A
Alex Deucher 已提交
3108 3109 3110
	return r;
}

3111 3112 3113 3114 3115
void amdgpu_get_pcie_info(struct amdgpu_device *adev)
{
	u32 mask;
	int ret;

3116 3117
	if (amdgpu_pcie_gen_cap)
		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3118

3119 3120
	if (amdgpu_pcie_lane_cap)
		adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3121

3122 3123 3124 3125 3126 3127
	/* covers APUs as well */
	if (pci_is_root_bus(adev->pdev->bus)) {
		if (adev->pm.pcie_gen_mask == 0)
			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
		if (adev->pm.pcie_mlw_mask == 0)
			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3128
		return;
3129
	}
3130

3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198
	if (adev->pm.pcie_gen_mask == 0) {
		ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
		if (!ret) {
			adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);

			if (mask & DRM_PCIE_SPEED_25)
				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
			if (mask & DRM_PCIE_SPEED_50)
				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
			if (mask & DRM_PCIE_SPEED_80)
				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
		} else {
			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
		}
	}
	if (adev->pm.pcie_mlw_mask == 0) {
		ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
		if (!ret) {
			switch (mask) {
			case 32:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 16:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 12:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 8:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 4:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 2:
				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
				break;
			case 1:
				adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
				break;
			default:
				break;
			}
		} else {
			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3199 3200 3201
		}
	}
}
A
Alex Deucher 已提交
3202 3203 3204 3205 3206

/*
 * Debugfs
 */
int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3207
			     const struct drm_info_list *files,
A
Alex Deucher 已提交
3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241
			     unsigned nfiles)
{
	unsigned i;

	for (i = 0; i < adev->debugfs_count; i++) {
		if (adev->debugfs[i].files == files) {
			/* Already registered */
			return 0;
		}
	}

	i = adev->debugfs_count + 1;
	if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
		DRM_ERROR("Reached maximum number of debugfs components.\n");
		DRM_ERROR("Report so we increase "
			  "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
		return -EINVAL;
	}
	adev->debugfs[adev->debugfs_count].files = files;
	adev->debugfs[adev->debugfs_count].num_files = nfiles;
	adev->debugfs_count = i;
#if defined(CONFIG_DEBUG_FS)
	drm_debugfs_create_files(files, nfiles,
				 adev->ddev->primary->debugfs_root,
				 adev->ddev->primary);
#endif
	return 0;
}

#if defined(CONFIG_DEBUG_FS)

static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3242
	struct amdgpu_device *adev = file_inode(f)->i_private;
A
Alex Deucher 已提交
3243 3244
	ssize_t result = 0;
	int r;
3245
	bool pm_pg_lock, use_bank;
3246
	unsigned instance_bank, sh_bank, se_bank;
A
Alex Deucher 已提交
3247 3248 3249 3250

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

3251 3252 3253
	/* are we reading registers for which a PG lock is necessary? */
	pm_pg_lock = (*pos >> 23) & 1;

3254
	if (*pos & (1ULL << 62)) {
3255 3256 3257
		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3258 3259 3260 3261 3262 3263 3264

		if (se_bank == 0x3FF)
			se_bank = 0xFFFFFFFF;
		if (sh_bank == 0x3FF)
			sh_bank = 0xFFFFFFFF;
		if (instance_bank == 0x3FF)
			instance_bank = 0xFFFFFFFF;
3265 3266 3267 3268 3269
		use_bank = 1;
	} else {
		use_bank = 0;
	}

3270
	*pos &= (1UL << 22) - 1;
3271

3272
	if (use_bank) {
3273 3274
		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3275 3276 3277 3278 3279 3280
			return -EINVAL;
		mutex_lock(&adev->grbm_idx_mutex);
		amdgpu_gfx_select_se_sh(adev, se_bank,
					sh_bank, instance_bank);
	}

3281 3282 3283
	if (pm_pg_lock)
		mutex_lock(&adev->pm.mutex);

A
Alex Deucher 已提交
3284 3285 3286 3287
	while (size) {
		uint32_t value;

		if (*pos > adev->rmmio_size)
3288
			goto end;
A
Alex Deucher 已提交
3289 3290 3291

		value = RREG32(*pos >> 2);
		r = put_user(value, (uint32_t *)buf);
3292 3293 3294 3295
		if (r) {
			result = r;
			goto end;
		}
A
Alex Deucher 已提交
3296 3297 3298 3299 3300 3301 3302

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

3303 3304 3305 3306 3307 3308
end:
	if (use_bank) {
		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
		mutex_unlock(&adev->grbm_idx_mutex);
	}

3309 3310 3311
	if (pm_pg_lock)
		mutex_unlock(&adev->pm.mutex);

A
Alex Deucher 已提交
3312 3313 3314 3315 3316 3317
	return result;
}

static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
					 size_t size, loff_t *pos)
{
A
Al Viro 已提交
3318
	struct amdgpu_device *adev = file_inode(f)->i_private;
A
Alex Deucher 已提交
3319 3320
	ssize_t result = 0;
	int r;
3321 3322
	bool pm_pg_lock, use_bank;
	unsigned instance_bank, sh_bank, se_bank;
A
Alex Deucher 已提交
3323 3324 3325 3326

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

3327 3328 3329 3330
	/* are we reading registers for which a PG lock is necessary? */
	pm_pg_lock = (*pos >> 23) & 1;

	if (*pos & (1ULL << 62)) {
3331 3332 3333
		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345

		if (se_bank == 0x3FF)
			se_bank = 0xFFFFFFFF;
		if (sh_bank == 0x3FF)
			sh_bank = 0xFFFFFFFF;
		if (instance_bank == 0x3FF)
			instance_bank = 0xFFFFFFFF;
		use_bank = 1;
	} else {
		use_bank = 0;
	}

3346
	*pos &= (1UL << 22) - 1;
3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359

	if (use_bank) {
		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
			return -EINVAL;
		mutex_lock(&adev->grbm_idx_mutex);
		amdgpu_gfx_select_se_sh(adev, se_bank,
					sh_bank, instance_bank);
	}

	if (pm_pg_lock)
		mutex_lock(&adev->pm.mutex);

A
Alex Deucher 已提交
3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377
	while (size) {
		uint32_t value;

		if (*pos > adev->rmmio_size)
			return result;

		r = get_user(value, (uint32_t *)buf);
		if (r)
			return r;

		WREG32(*pos >> 2, value);

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

3378 3379 3380 3381 3382 3383 3384 3385
	if (use_bank) {
		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
		mutex_unlock(&adev->grbm_idx_mutex);
	}

	if (pm_pg_lock)
		mutex_unlock(&adev->pm.mutex);

A
Alex Deucher 已提交
3386 3387 3388
	return result;
}

3389 3390 3391
static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3392
	struct amdgpu_device *adev = file_inode(f)->i_private;
3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

		value = RREG32_PCIE(*pos >> 2);
		r = put_user(value, (uint32_t *)buf);
		if (r)
			return r;

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
					 size_t size, loff_t *pos)
{
A
Al Viro 已提交
3419
	struct amdgpu_device *adev = file_inode(f)->i_private;
3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

		r = get_user(value, (uint32_t *)buf);
		if (r)
			return r;

		WREG32_PCIE(*pos >> 2, value);

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3447
	struct amdgpu_device *adev = file_inode(f)->i_private;
3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

		value = RREG32_DIDT(*pos >> 2);
		r = put_user(value, (uint32_t *)buf);
		if (r)
			return r;

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
					 size_t size, loff_t *pos)
{
A
Al Viro 已提交
3474
	struct amdgpu_device *adev = file_inode(f)->i_private;
3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

		r = get_user(value, (uint32_t *)buf);
		if (r)
			return r;

		WREG32_DIDT(*pos >> 2, value);

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3502
	struct amdgpu_device *adev = file_inode(f)->i_private;
3503 3504 3505 3506 3507 3508 3509 3510 3511
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

3512
		value = RREG32_SMC(*pos);
3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528
		r = put_user(value, (uint32_t *)buf);
		if (r)
			return r;

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
					 size_t size, loff_t *pos)
{
A
Al Viro 已提交
3529
	struct amdgpu_device *adev = file_inode(f)->i_private;
3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

	while (size) {
		uint32_t value;

		r = get_user(value, (uint32_t *)buf);
		if (r)
			return r;

3543
		WREG32_SMC(*pos, value);
3544 3545 3546 3547 3548 3549 3550 3551 3552 3553

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

3554 3555 3556
static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3557
	struct amdgpu_device *adev = file_inode(f)->i_private;
3558 3559 3560 3561 3562 3563 3564
	ssize_t result = 0;
	int r;
	uint32_t *config, no_regs = 0;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

3565
	config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3566 3567 3568 3569
	if (!config)
		return -ENOMEM;

	/* version, increment each time something is added */
3570
	config[no_regs++] = 3;
3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594
	config[no_regs++] = adev->gfx.config.max_shader_engines;
	config[no_regs++] = adev->gfx.config.max_tile_pipes;
	config[no_regs++] = adev->gfx.config.max_cu_per_sh;
	config[no_regs++] = adev->gfx.config.max_sh_per_se;
	config[no_regs++] = adev->gfx.config.max_backends_per_se;
	config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
	config[no_regs++] = adev->gfx.config.max_gprs;
	config[no_regs++] = adev->gfx.config.max_gs_threads;
	config[no_regs++] = adev->gfx.config.max_hw_contexts;
	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
	config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
	config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
	config[no_regs++] = adev->gfx.config.num_tile_pipes;
	config[no_regs++] = adev->gfx.config.backend_enable_mask;
	config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
	config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
	config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
	config[no_regs++] = adev->gfx.config.num_gpus;
	config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
	config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
	config[no_regs++] = adev->gfx.config.gb_addr_config;
	config[no_regs++] = adev->gfx.config.num_rbs;

3595 3596 3597 3598 3599
	/* rev==1 */
	config[no_regs++] = adev->rev_id;
	config[no_regs++] = adev->pg_flags;
	config[no_regs++] = adev->cg_flags;

3600 3601 3602 3603
	/* rev==2 */
	config[no_regs++] = adev->family;
	config[no_regs++] = adev->external_rev_id;

3604 3605 3606 3607 3608 3609
	/* rev==3 */
	config[no_regs++] = adev->pdev->device;
	config[no_regs++] = adev->pdev->revision;
	config[no_regs++] = adev->pdev->subsystem_device;
	config[no_regs++] = adev->pdev->subsystem_vendor;

3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629
	while (size && (*pos < no_regs * 4)) {
		uint32_t value;

		value = config[*pos >> 2];
		r = put_user(value, (uint32_t *)buf);
		if (r) {
			kfree(config);
			return r;
		}

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	kfree(config);
	return result;
}

3630 3631 3632
static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
A
Al Viro 已提交
3633
	struct amdgpu_device *adev = file_inode(f)->i_private;
3634 3635
	int idx, x, outsize, r, valuesize;
	uint32_t values[16];
3636

3637
	if (size & 3 || *pos & 0x3)
3638 3639
		return -EINVAL;

3640 3641 3642
	if (amdgpu_dpm == 0)
		return -EINVAL;

3643 3644 3645
	/* convert offset to sensor number */
	idx = *pos >> 2;

3646
	valuesize = sizeof(values);
3647
	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3648
		r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
3649 3650 3651
	else
		return -EINVAL;

3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664
	if (size > valuesize)
		return -EINVAL;

	outsize = 0;
	x = 0;
	if (!r) {
		while (size) {
			r = put_user(values[x++], (int32_t *)buf);
			buf += 4;
			size -= 4;
			outsize += 4;
		}
	}
3665

3666
	return !r ? outsize : r;
3667
}
3668

3669 3670 3671 3672 3673 3674
static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
	struct amdgpu_device *adev = f->f_inode->i_private;
	int r, x;
	ssize_t result=0;
3675
	uint32_t offset, se, sh, cu, wave, simd, data[32];
3676 3677 3678 3679 3680

	if (size & 3 || *pos & 3)
		return -EINVAL;

	/* decode offset */
3681 3682 3683 3684 3685 3686
	offset = (*pos & GENMASK_ULL(6, 0));
	se = (*pos & GENMASK_ULL(14, 7)) >> 7;
	sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
	cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
	wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
	simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3687 3688 3689 3690 3691 3692

	/* switch to the specific se/sh/cu */
	mutex_lock(&adev->grbm_idx_mutex);
	amdgpu_gfx_select_se_sh(adev, se, sh, cu);

	x = 0;
3693 3694
	if (adev->gfx.funcs->read_wave_data)
		adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3695 3696 3697 3698

	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
	mutex_unlock(&adev->grbm_idx_mutex);

3699 3700 3701
	if (!x)
		return -EINVAL;

3702
	while (size && (offset < x * 4)) {
3703 3704
		uint32_t value;

3705
		value = data[offset >> 2];
3706 3707 3708 3709 3710 3711
		r = put_user(value, (uint32_t *)buf);
		if (r)
			return r;

		result += 4;
		buf += 4;
3712
		offset += 4;
3713 3714 3715 3716 3717 3718
		size -= 4;
	}

	return result;
}

3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730
static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
	struct amdgpu_device *adev = f->f_inode->i_private;
	int r;
	ssize_t result = 0;
	uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;

	if (size & 3 || *pos & 3)
		return -EINVAL;

	/* decode offset */
3731 3732 3733 3734 3735 3736 3737 3738
	offset = *pos & GENMASK_ULL(11, 0);
	se = (*pos & GENMASK_ULL(19, 12)) >> 12;
	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
	wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
	simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778

	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	/* switch to the specific se/sh/cu */
	mutex_lock(&adev->grbm_idx_mutex);
	amdgpu_gfx_select_se_sh(adev, se, sh, cu);

	if (bank == 0) {
		if (adev->gfx.funcs->read_wave_vgprs)
			adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
	} else {
		if (adev->gfx.funcs->read_wave_sgprs)
			adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
	}

	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
	mutex_unlock(&adev->grbm_idx_mutex);

	while (size) {
		uint32_t value;

		value = data[offset++];
		r = put_user(value, (uint32_t *)buf);
		if (r) {
			result = r;
			goto err;
		}

		result += 4;
		buf += 4;
		size -= 4;
	}

err:
	kfree(data);
	return result;
}

A
Alex Deucher 已提交
3779 3780 3781 3782 3783 3784
static const struct file_operations amdgpu_debugfs_regs_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_regs_read,
	.write = amdgpu_debugfs_regs_write,
	.llseek = default_llseek
};
3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_regs_didt_read,
	.write = amdgpu_debugfs_regs_didt_write,
	.llseek = default_llseek
};
static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_regs_pcie_read,
	.write = amdgpu_debugfs_regs_pcie_write,
	.llseek = default_llseek
};
static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_regs_smc_read,
	.write = amdgpu_debugfs_regs_smc_write,
	.llseek = default_llseek
};

3804 3805 3806 3807 3808 3809
static const struct file_operations amdgpu_debugfs_gca_config_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_gca_config_read,
	.llseek = default_llseek
};

3810 3811 3812 3813 3814 3815
static const struct file_operations amdgpu_debugfs_sensors_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_sensor_read,
	.llseek = default_llseek
};

3816 3817 3818 3819 3820
static const struct file_operations amdgpu_debugfs_wave_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_wave_read,
	.llseek = default_llseek
};
3821 3822 3823 3824 3825
static const struct file_operations amdgpu_debugfs_gpr_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_gpr_read,
	.llseek = default_llseek
};
3826

3827 3828 3829 3830 3831
static const struct file_operations *debugfs_regs[] = {
	&amdgpu_debugfs_regs_fops,
	&amdgpu_debugfs_regs_didt_fops,
	&amdgpu_debugfs_regs_pcie_fops,
	&amdgpu_debugfs_regs_smc_fops,
3832
	&amdgpu_debugfs_gca_config_fops,
3833
	&amdgpu_debugfs_sensors_fops,
3834
	&amdgpu_debugfs_wave_fops,
3835
	&amdgpu_debugfs_gpr_fops,
3836 3837 3838 3839 3840 3841 3842
};

static const char *debugfs_regs_names[] = {
	"amdgpu_regs",
	"amdgpu_regs_didt",
	"amdgpu_regs_pcie",
	"amdgpu_regs_smc",
3843
	"amdgpu_gca_config",
3844
	"amdgpu_sensors",
3845
	"amdgpu_wave",
3846
	"amdgpu_gpr",
3847
};
A
Alex Deucher 已提交
3848 3849 3850 3851 3852

static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
	struct drm_minor *minor = adev->ddev->primary;
	struct dentry *ent, *root = minor->debugfs_root;
3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865
	unsigned i, j;

	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
		ent = debugfs_create_file(debugfs_regs_names[i],
					  S_IFREG | S_IRUGO, root,
					  adev, debugfs_regs[i]);
		if (IS_ERR(ent)) {
			for (j = 0; j < i; j++) {
				debugfs_remove(adev->debugfs_regs[i]);
				adev->debugfs_regs[i] = NULL;
			}
			return PTR_ERR(ent);
		}
A
Alex Deucher 已提交
3866

3867 3868 3869 3870
		if (!i)
			i_size_write(ent->d_inode, adev->rmmio_size);
		adev->debugfs_regs[i] = ent;
	}
A
Alex Deucher 已提交
3871 3872 3873 3874 3875 3876

	return 0;
}

static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
{
3877 3878 3879 3880 3881 3882 3883 3884
	unsigned i;

	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
		if (adev->debugfs_regs[i]) {
			debugfs_remove(adev->debugfs_regs[i]);
			adev->debugfs_regs[i] = NULL;
		}
	}
A
Alex Deucher 已提交
3885 3886
}

3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931
static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct amdgpu_device *adev = dev->dev_private;
	int r = 0, i;

	/* hold on the scheduler */
	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
		struct amdgpu_ring *ring = adev->rings[i];

		if (!ring || !ring->sched.thread)
			continue;
		kthread_park(ring->sched.thread);
	}

	seq_printf(m, "run ib test:\n");
	r = amdgpu_ib_ring_tests(adev);
	if (r)
		seq_printf(m, "ib ring tests failed (%d).\n", r);
	else
		seq_printf(m, "ib ring tests passed.\n");

	/* go on the scheduler */
	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
		struct amdgpu_ring *ring = adev->rings[i];

		if (!ring || !ring->sched.thread)
			continue;
		kthread_unpark(ring->sched.thread);
	}

	return 0;
}

static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
	{"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
};

static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
{
	return amdgpu_debugfs_add_files(adev,
					amdgpu_debugfs_test_ib_ring_list, 1);
}

A
Alex Deucher 已提交
3932 3933 3934 3935
int amdgpu_debugfs_init(struct drm_minor *minor)
{
	return 0;
}
3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957

static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct amdgpu_device *adev = dev->dev_private;

	seq_write(m, adev->bios, adev->bios_size);
	return 0;
}

static const struct drm_info_list amdgpu_vbios_dump_list[] = {
		{"amdgpu_vbios",
		 amdgpu_debugfs_get_vbios_dump,
		 0, NULL},
};

static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
{
	return amdgpu_debugfs_add_files(adev,
					amdgpu_vbios_dump_list, 1);
}
3958
#else
3959
static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3960 3961 3962
{
	return 0;
}
3963 3964 3965 3966
static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
	return 0;
}
3967 3968 3969 3970
static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
{
	return 0;
}
3971
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
A
Alex Deucher 已提交
3972
#endif