hda_intel.c 113.2 KB
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/*
 *
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 *  hda_intel.c - Implementation of primary alsa driver code base
 *                for Intel HD Audio.
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 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc., 59
 *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 *  CONTACTS:
 *
 *  Matt Jared		matt.jared@intel.com
 *  Andy Kopp		andy.kopp@intel.com
 *  Dan Kogan		dan.d.kogan@intel.com
 *
 *  CHANGES:
 *
 *  2004.12.01	Major rewrite by tiwai, merged the work of pshou
 * 
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/reboot.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/clocksource.h>
#include <linux/time.h>
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#include <linux/completion.h>
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#ifdef CONFIG_X86
/* for snoop control */
#include <asm/pgtable.h>
#include <asm/cacheflush.h>
#endif
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#include <sound/core.h>
#include <sound/initval.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/firmware.h>
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#include "hda_codec.h"
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#include "hda_i915.h"
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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
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static char *model[SNDRV_CARDS];
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static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_only[SNDRV_CARDS];
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static int jackpoll_ms[SNDRV_CARDS];
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static bool single_cmd;
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static int enable_msi = -1;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
static char *patch[SNDRV_CARDS];
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
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static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
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					CONFIG_SND_HDA_INPUT_BEEP_MODE};
#endif
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
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module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
module_param_array(model, charp, NULL, 0444);
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MODULE_PARM_DESC(model, "Use the given board model.");
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module_param_array(position_fix, int, NULL, 0444);
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MODULE_PARM_DESC(position_fix, "DMA pointer read method."
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		 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
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module_param_array(bdl_pos_adj, int, NULL, 0644);
MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
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module_param_array(probe_mask, int, NULL, 0444);
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MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
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module_param_array(probe_only, int, NULL, 0444);
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MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
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module_param_array(jackpoll_ms, int, NULL, 0444);
MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
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module_param(single_cmd, bool, 0444);
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MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
		 "(for debugging only).");
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module_param(enable_msi, bint, 0444);
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MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
module_param_array(patch, charp, NULL, 0444);
MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
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module_param_array(beep_mode, bool, NULL, 0444);
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MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
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			    "(0=off, 1=on) (default=1).");
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#endif
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#ifdef CONFIG_PM
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static int param_set_xint(const char *val, const struct kernel_param *kp);
static struct kernel_param_ops param_ops_xint = {
	.set = param_set_xint,
	.get = param_get_int,
};
#define param_check_xint param_check_int

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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
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module_param(power_save, xint, 0644);
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MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
		 "(in second, 0 = disable).");
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/* reset the HD-audio controller in power save mode.
 * this may give more power-saving, but will take longer time to
 * wake up.
 */
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static bool power_save_controller = 1;
module_param(power_save_controller, bool, 0644);
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MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
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#endif /* CONFIG_PM */
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static int align_buffer_size = -1;
module_param(align_buffer_size, bint, 0644);
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MODULE_PARM_DESC(align_buffer_size,
		"Force buffer and period sizes to be multiple of 128 bytes.");

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#ifdef CONFIG_X86
static bool hda_snoop = true;
module_param_named(snoop, hda_snoop, bool, 0444);
MODULE_PARM_DESC(snoop, "Enable/disable snooping");
#define azx_snoop(chip)		(chip)->snoop
#else
#define hda_snoop		true
#define azx_snoop(chip)		true
#endif


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MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
			 "{Intel, ICH6M},"
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			 "{Intel, ICH7},"
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			 "{Intel, ESB2},"
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			 "{Intel, ICH8},"
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			 "{Intel, ICH9},"
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			 "{Intel, ICH10},"
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			 "{Intel, PCH},"
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			 "{Intel, CPT},"
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			 "{Intel, PPT},"
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			 "{Intel, LPT},"
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			 "{Intel, LPT_LP},"
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			 "{Intel, WPT_LP},"
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			 "{Intel, HPT},"
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			 "{Intel, PBG},"
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			 "{Intel, SCH},"
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			 "{ATI, SB450},"
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			 "{ATI, SB600},"
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			 "{ATI, RS600},"
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			 "{ATI, RS690},"
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			 "{ATI, RS780},"
			 "{ATI, R600},"
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			 "{ATI, RV630},"
			 "{ATI, RV610},"
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			 "{ATI, RV670},"
			 "{ATI, RV635},"
			 "{ATI, RV620},"
			 "{ATI, RV770},"
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			 "{VIA, VT8251},"
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			 "{VIA, VT8237A},"
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			 "{SiS, SIS966},"
			 "{ULI, M5461}}");
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MODULE_DESCRIPTION("Intel HDA driver");

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#ifdef CONFIG_SND_VERBOSE_PRINTK
#define SFX	/* nop */
#else
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#define SFX	"hda-intel "
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#endif
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#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
#ifdef CONFIG_SND_HDA_CODEC_HDMI
#define SUPPORT_VGA_SWITCHEROO
#endif
#endif


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/*
 * registers
 */
#define ICH6_REG_GCAP			0x00
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#define   ICH6_GCAP_64OK	(1 << 0)   /* 64bit address support */
#define   ICH6_GCAP_NSDO	(3 << 1)   /* # of serial data out signals */
#define   ICH6_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   ICH6_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   ICH6_GCAP_OSS		(15 << 12) /* # of output streams */
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#define ICH6_REG_VMIN			0x02
#define ICH6_REG_VMAJ			0x03
#define ICH6_REG_OUTPAY			0x04
#define ICH6_REG_INPAY			0x06
#define ICH6_REG_GCTL			0x08
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#define   ICH6_GCTL_RESET	(1 << 0)   /* controller reset */
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#define   ICH6_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   ICH6_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
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#define ICH6_REG_WAKEEN			0x0c
#define ICH6_REG_STATESTS		0x0e
#define ICH6_REG_GSTS			0x10
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#define   ICH6_GSTS_FSTS	(1 << 1)   /* flush status */
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#define ICH6_REG_INTCTL			0x20
#define ICH6_REG_INTSTS			0x24
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#define ICH6_REG_WALLCLK		0x30	/* 24Mhz source */
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#define ICH6_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define ICH6_REG_SSYNC			0x38
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#define ICH6_REG_CORBLBASE		0x40
#define ICH6_REG_CORBUBASE		0x44
#define ICH6_REG_CORBWP			0x48
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#define ICH6_REG_CORBRP			0x4a
#define   ICH6_CORBRP_RST	(1 << 15)  /* read pointer reset */
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#define ICH6_REG_CORBCTL		0x4c
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#define   ICH6_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   ICH6_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
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#define ICH6_REG_CORBSTS		0x4d
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#define   ICH6_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
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#define ICH6_REG_CORBSIZE		0x4e

#define ICH6_REG_RIRBLBASE		0x50
#define ICH6_REG_RIRBUBASE		0x54
#define ICH6_REG_RIRBWP			0x58
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#define   ICH6_RIRBWP_RST	(1 << 15)  /* write pointer reset */
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#define ICH6_REG_RINTCNT		0x5a
#define ICH6_REG_RIRBCTL		0x5c
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#define   ICH6_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   ICH6_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   ICH6_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
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#define ICH6_REG_RIRBSTS		0x5d
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#define   ICH6_RBSTS_IRQ	(1 << 0)   /* response irq */
#define   ICH6_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
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#define ICH6_REG_RIRBSIZE		0x5e

#define ICH6_REG_IC			0x60
#define ICH6_REG_IR			0x64
#define ICH6_REG_IRS			0x68
#define   ICH6_IRS_VALID	(1<<1)
#define   ICH6_IRS_BUSY		(1<<0)

#define ICH6_REG_DPLBASE		0x70
#define ICH6_REG_DPUBASE		0x74
#define   ICH6_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define ICH6_REG_SD_CTL			0x00
#define ICH6_REG_SD_STS			0x03
#define ICH6_REG_SD_LPIB		0x04
#define ICH6_REG_SD_CBL			0x08
#define ICH6_REG_SD_LVI			0x0c
#define ICH6_REG_SD_FIFOW		0x0e
#define ICH6_REG_SD_FIFOSIZE		0x10
#define ICH6_REG_SD_FORMAT		0x12
#define ICH6_REG_SD_BDLPL		0x18
#define ICH6_REG_SD_BDLPU		0x1c

/* PCI space */
#define ICH6_PCIREG_TCSEL	0x44

/*
 * other constants
 */

/* max number of SDs */
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/* ICH, ATI and VIA have 4 playback and 4 capture */
#define ICH6_NUM_CAPTURE	4
#define ICH6_NUM_PLAYBACK	4

/* ULI has 6 playback and 5 capture */
#define ULI_NUM_CAPTURE		5
#define ULI_NUM_PLAYBACK	6

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/* ATI HDMI has 1 playback and 0 capture */
#define ATIHDMI_NUM_CAPTURE	0
#define ATIHDMI_NUM_PLAYBACK	1

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/* TERA has 4 playback and 3 capture */
#define TERA_NUM_CAPTURE	3
#define TERA_NUM_PLAYBACK	4

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/* this number is statically defined for simplicity */
#define MAX_AZX_DEV		16

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/* max number of fragments - we may use more if allocating more pages for BDL */
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#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
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/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

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/* STATESTS int mask: S3,SD2,SD1,SD0 */
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#define AZX_MAX_CODECS		8
#define AZX_DEFAULT_CODECS	4
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#define STATESTS_INT_MASK	((1 << AZX_MAX_CODECS) - 1)
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/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
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#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
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#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
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#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)
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/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
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#define ICH6_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define ICH6_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define ICH6_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */
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/* below are so far hardcoded - should read registers in future */
#define ICH6_MAX_CORB_ENTRIES	256
#define ICH6_MAX_RIRB_ENTRIES	256

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/* position fix mode */
enum {
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	POS_FIX_AUTO,
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	POS_FIX_LPIB,
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	POS_FIX_POSBUF,
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	POS_FIX_VIACOMBO,
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	POS_FIX_COMBO,
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};
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/* Defines for ATI HD Audio support in SB450 south bridge */
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

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/* Defines for Nvidia HDA support */
#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
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#define NVIDIA_HDA_ISTRM_COH          0x4d
#define NVIDIA_HDA_OSTRM_COH          0x4c
#define NVIDIA_HDA_ENABLE_COHBIT      0x01
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/* Defines for Intel SCH HDA snoop control */
#define INTEL_SCH_HDA_DEVC      0x78
#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

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/* Define IN stream 0 FIFO size offset in VIA controller */
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
/* Define VIA HD Audio Device ID*/
#define VIA_HDAC_DEVICE_ID		0x3288

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/* HD Audio class code */
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403
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/*
 */

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struct azx_dev {
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	struct snd_dma_buffer bdl; /* BDL buffer */
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	u32 *posbuf;		/* position buffer pointer */
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	unsigned int bufsize;	/* size of the play buffer in bytes */
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	unsigned int period_bytes; /* size of the period in bytes */
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	unsigned int frags;	/* number for period in the play buffer */
	unsigned int fifo_size;	/* FIFO size */
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	unsigned long start_wallclk;	/* start + minimum wallclk */
	unsigned long period_wallclk;	/* wallclk for period */
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	void __iomem *sd_addr;	/* stream descriptor pointer */
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	u32 sd_int_sta_mask;	/* stream int status mask */
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	/* pcm support */
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	struct snd_pcm_substream *substream;	/* assigned substream,
						 * set in PCM open
						 */
	unsigned int format_val;	/* format value to be set in the
					 * controller and the codec
					 */
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	unsigned char stream_tag;	/* assigned stream */
	unsigned char index;		/* stream index */
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	int assigned_key;		/* last device# key assigned to */
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	unsigned int opened :1;
	unsigned int running :1;
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	unsigned int irq_pending :1;
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	unsigned int prepared:1;
	unsigned int locked:1;
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	/*
	 * For VIA:
	 *  A flag to ensure DMA position is 0
	 *  when link position is not greater than FIFO size
	 */
	unsigned int insufficient :1;
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	unsigned int wc_marked:1;
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	unsigned int no_period_wakeup:1;
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	struct timecounter  azx_tc;
	struct cyclecounter azx_cc;
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#ifdef CONFIG_SND_HDA_DSP_LOADER
	struct mutex dsp_mutex;
#endif
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};

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/* DSP lock helpers */
#ifdef CONFIG_SND_HDA_DSP_LOADER
#define dsp_lock_init(dev)	mutex_init(&(dev)->dsp_mutex)
#define dsp_lock(dev)		mutex_lock(&(dev)->dsp_mutex)
#define dsp_unlock(dev)		mutex_unlock(&(dev)->dsp_mutex)
#define dsp_is_locked(dev)	((dev)->locked)
#else
#define dsp_lock_init(dev)	do {} while (0)
#define dsp_lock(dev)		do {} while (0)
#define dsp_unlock(dev)		do {} while (0)
#define dsp_is_locked(dev)	0
#endif

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/* CORB/RIRB */
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struct azx_rb {
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	u32 *buf;		/* CORB/RIRB buffer
				 * Each CORB entry is 4byte, RIRB is 8byte
				 */
	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */
	/* for RIRB */
	unsigned short rp, wp;	/* read/write pointers */
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	int cmds[AZX_MAX_CODECS];	/* number of pending requests */
	u32 res[AZX_MAX_CODECS];	/* last read value */
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};

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struct azx_pcm {
	struct azx *chip;
	struct snd_pcm *pcm;
	struct hda_codec *codec;
	struct hda_pcm_stream *hinfo[2];
	struct list_head list;
};

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struct azx {
	struct snd_card *card;
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	struct pci_dev *pci;
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	int dev_index;
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	/* chip type specific */
	int driver_type;
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	unsigned int driver_caps;
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	int playback_streams;
	int playback_index_offset;
	int capture_streams;
	int capture_index_offset;
	int num_streams;

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	/* pci resources */
	unsigned long addr;
	void __iomem *remap_addr;
	int irq;

	/* locks */
	spinlock_t reg_lock;
493
	struct mutex open_mutex;
494
	struct completion probe_wait;
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496
	/* streams (x num_streams) */
497
	struct azx_dev *azx_dev;
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	/* PCM */
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	struct list_head pcm_list; /* azx_pcm list */
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	/* HD codec */
	unsigned short codec_mask;
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	int  codec_probe_mask; /* copied from probe_mask option */
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	struct hda_bus *bus;
506
	unsigned int beep_mode;
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	/* CORB/RIRB */
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	struct azx_rb corb;
	struct azx_rb rirb;
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	/* CORB/RIRB and position buffers */
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	struct snd_dma_buffer rb;
	struct snd_dma_buffer posbuf;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
	const struct firmware *fw;
#endif

520
	/* flags */
521
	int position_fix[2]; /* for both playback/capture streams */
522
	int poll_count;
523
	unsigned int running :1;
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	unsigned int initialized :1;
	unsigned int single_cmd :1;
	unsigned int polling_mode :1;
527
	unsigned int msi :1;
528
	unsigned int irq_pending_warned :1;
529
	unsigned int probing :1; /* codec probing phase */
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	unsigned int snoop:1;
531
	unsigned int align_buffer_size:1;
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	unsigned int region_requested:1;

	/* VGA-switcheroo setup */
	unsigned int use_vga_switcheroo:1;
536
	unsigned int vga_switcheroo_registered:1;
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	unsigned int init_failed:1; /* delayed init failed */
	unsigned int disabled:1; /* disabled by VGA-switcher */
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	/* for debugging */
541
	unsigned int last_cmd[AZX_MAX_CODECS];
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	/* for pending irqs */
	struct work_struct irq_pending_work;
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#ifdef CONFIG_SND_HDA_I915
	struct work_struct probe_work;
#endif

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	/* reboot notifier (for mysterious hangup problem at power-down) */
	struct notifier_block reboot_notifier;
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	/* card list (for power_save trigger) */
	struct list_head list;
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#ifdef CONFIG_SND_HDA_DSP_LOADER
	struct azx_dev saved_azx_dev;
#endif
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	/* secondary power domain for hdmi audio under vga device */
	struct dev_pm_domain hdmi_pm_domain;
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};

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#define CREATE_TRACE_POINTS
#include "hda_intel_trace.h"

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/* driver types */
enum {
	AZX_DRIVER_ICH,
570
	AZX_DRIVER_PCH,
571
	AZX_DRIVER_SCH,
572
	AZX_DRIVER_HDMI,
573
	AZX_DRIVER_ATI,
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	AZX_DRIVER_ATIHDMI,
575
	AZX_DRIVER_ATIHDMI_NS,
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	AZX_DRIVER_VIA,
	AZX_DRIVER_SIS,
	AZX_DRIVER_ULI,
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	AZX_DRIVER_NVIDIA,
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	AZX_DRIVER_TERA,
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	AZX_DRIVER_CTX,
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	AZX_DRIVER_CTHDA,
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	AZX_DRIVER_GENERIC,
584
	AZX_NUM_DRIVERS, /* keep this as last entry */
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};

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/* driver quirks (capabilities) */
/* bits 0-7 are used for indicating driver type */
#define AZX_DCAPS_NO_TCSEL	(1 << 8)	/* No Intel TCSEL bit */
#define AZX_DCAPS_NO_MSI	(1 << 9)	/* No MSI support */
#define AZX_DCAPS_ATI_SNOOP	(1 << 10)	/* ATI snoop enable */
#define AZX_DCAPS_NVIDIA_SNOOP	(1 << 11)	/* Nvidia snoop enable */
#define AZX_DCAPS_SCH_SNOOP	(1 << 12)	/* SCH/PCH snoop enable */
#define AZX_DCAPS_RIRB_DELAY	(1 << 13)	/* Long delay in read loop */
#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)	/* Put a delay before read */
#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */
#define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */
#define AZX_DCAPS_POSFIX_VIA	(1 << 17)	/* Use VIACOMBO as default */
#define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */
#define AZX_DCAPS_SYNC_WRITE	(1 << 19)	/* sync each cmd write */
601
#define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */
602
#define AZX_DCAPS_BUFSIZE	(1 << 21)	/* no buffer size alignment */
603
#define AZX_DCAPS_ALIGN_BUFSIZE	(1 << 22)	/* buffer size alignment */
604
#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */
605
#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */
606
#define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */
607
#define AZX_DCAPS_I915_POWERWELL (1 << 27)	/* HSW i915 power well support */
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/* quirks for Intel PCH */
610
#define AZX_DCAPS_INTEL_PCH_NOPM \
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	(AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
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	 AZX_DCAPS_COUNT_LPIB_DELAY)

#define AZX_DCAPS_INTEL_PCH \
	(AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
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#define AZX_DCAPS_INTEL_HASWELL \
	(AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
	 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
	 AZX_DCAPS_I915_POWERWELL)

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/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
	(AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
	 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)

/* quirks for ATI/AMD HDMI */
#define AZX_DCAPS_PRESET_ATI_HDMI \
	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)

/* quirks for Nvidia */
#define AZX_DCAPS_PRESET_NVIDIA \
633
	(AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
634
	 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
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#define AZX_DCAPS_PRESET_CTHDA \
	(AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)

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/*
 * VGA-switcher support
 */
#ifdef SUPPORT_VGA_SWITCHEROO
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#define use_vga_switcheroo(chip)	((chip)->use_vga_switcheroo)
#else
#define use_vga_switcheroo(chip)	0
#endif

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static char *driver_short_names[] = {
649
	[AZX_DRIVER_ICH] = "HDA Intel",
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	[AZX_DRIVER_PCH] = "HDA Intel PCH",
651
	[AZX_DRIVER_SCH] = "HDA Intel MID",
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	[AZX_DRIVER_HDMI] = "HDA Intel HDMI",
653
	[AZX_DRIVER_ATI] = "HDA ATI SB",
654
	[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
655
	[AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
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	[AZX_DRIVER_VIA] = "HDA VIA VT82xx",
	[AZX_DRIVER_SIS] = "HDA SIS966",
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	[AZX_DRIVER_ULI] = "HDA ULI M5461",
	[AZX_DRIVER_NVIDIA] = "HDA NVidia",
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	[AZX_DRIVER_TERA] = "HDA Teradici", 
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	[AZX_DRIVER_CTX] = "HDA Creative", 
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	[AZX_DRIVER_CTHDA] = "HDA Creative",
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	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
664 665
};

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/*
 * macros for easy use
 */
#define azx_writel(chip,reg,value) \
	writel(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readl(chip,reg) \
	readl((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writew(chip,reg,value) \
	writew(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readw(chip,reg) \
	readw((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writeb(chip,reg,value) \
	writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readb(chip,reg) \
	readb((chip)->remap_addr + ICH6_REG_##reg)

#define azx_sd_writel(dev,reg,value) \
	writel(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readl(dev,reg) \
	readl((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writew(dev,reg,value) \
	writew(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readw(dev,reg) \
	readw((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writeb(dev,reg,value) \
	writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readb(dev,reg) \
	readb((dev)->sd_addr + ICH6_REG_##reg)

/* for pcm support */
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#define get_azx_dev(substream) (substream->runtime->private_data)
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#ifdef CONFIG_X86
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static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
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{
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	int pages;

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	if (azx_snoop(chip))
		return;
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	if (!dmab || !dmab->area || !dmab->bytes)
		return;

#ifdef CONFIG_SND_DMA_SGBUF
	if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
		struct snd_sg_buf *sgbuf = dmab->private_data;
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		if (on)
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			set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
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		else
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			set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
		return;
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	}
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#endif

	pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
	if (on)
		set_memory_wc((unsigned long)dmab->area, pages);
	else
		set_memory_wb((unsigned long)dmab->area, pages);
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}

static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
				 bool on)
{
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	__mark_pages_wc(chip, buf, on);
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}
static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
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				   struct snd_pcm_substream *substream, bool on)
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{
	if (azx_dev->wc_marked != on) {
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		__mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
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		azx_dev->wc_marked = on;
	}
}
#else
/* NOP for other archs */
static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
				 bool on)
{
}
static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
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				   struct snd_pcm_substream *substream, bool on)
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{
}
#endif

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static int azx_acquire_irq(struct azx *chip, int do_disconnect);
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static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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/*
 * Interface for HD codec
 */

/*
 * CORB / RIRB interface
 */
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static int azx_alloc_cmd_io(struct azx *chip)
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{
	int err;

	/* single page (at least 4096 bytes) must suffice for both ringbuffes */
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	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
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				  PAGE_SIZE, &chip->rb);
	if (err < 0) {
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		snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
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		return err;
	}
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	mark_pages_wc(chip, &chip->rb, true);
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	return 0;
}

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static void azx_init_cmd_io(struct azx *chip)
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{
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	spin_lock_irq(&chip->reg_lock);
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	/* CORB set up */
	chip->corb.addr = chip->rb.addr;
	chip->corb.buf = (u32 *)chip->rb.area;
	azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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	azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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	/* set the corb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, CORBSIZE, 0x02);
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	/* set the corb write pointer to 0 */
	azx_writew(chip, CORBWP, 0);
	/* reset the corb hw read pointer */
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	azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
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	/* enable corb dma */
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	azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
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	/* RIRB set up */
	chip->rirb.addr = chip->rb.addr + 2048;
	chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
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	chip->rirb.wp = chip->rirb.rp = 0;
	memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
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	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
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	azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
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	/* set the rirb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, RIRBSIZE, 0x02);
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	/* reset the rirb hw write pointer */
805
	azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
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	/* set N=1, get RIRB response interrupt for new entry */
807
	if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
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		azx_writew(chip, RINTCNT, 0xc0);
	else
		azx_writew(chip, RINTCNT, 1);
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	/* enable rirb dma and response irq */
	azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
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	spin_unlock_irq(&chip->reg_lock);
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}

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static void azx_free_cmd_io(struct azx *chip)
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{
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	spin_lock_irq(&chip->reg_lock);
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	/* disable ringbuffer DMAs */
	azx_writeb(chip, RIRBCTL, 0);
	azx_writeb(chip, CORBCTL, 0);
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	spin_unlock_irq(&chip->reg_lock);
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}

825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846
static unsigned int azx_command_addr(u32 cmd)
{
	unsigned int addr = cmd >> 28;

	if (addr >= AZX_MAX_CODECS) {
		snd_BUG();
		addr = 0;
	}

	return addr;
}

static unsigned int azx_response_addr(u32 res)
{
	unsigned int addr = res & 0xf;

	if (addr >= AZX_MAX_CODECS) {
		snd_BUG();
		addr = 0;
	}

	return addr;
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}

/* send a command */
850
static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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{
852
	struct azx *chip = bus->private_data;
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	unsigned int addr = azx_command_addr(val);
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	unsigned int wp, rp;
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	spin_lock_irq(&chip->reg_lock);

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	/* add command to corb */
859 860 861 862
	wp = azx_readw(chip, CORBWP);
	if (wp == 0xffff) {
		/* something wrong, controller likely turned to D3 */
		spin_unlock_irq(&chip->reg_lock);
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		return -EIO;
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	}
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	wp++;
	wp %= ICH6_MAX_CORB_ENTRIES;

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	rp = azx_readw(chip, CORBRP);
	if (wp == rp) {
		/* oops, it's full */
		spin_unlock_irq(&chip->reg_lock);
		return -EAGAIN;
	}

875
	chip->rirb.cmds[addr]++;
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	chip->corb.buf[wp] = cpu_to_le32(val);
	azx_writel(chip, CORBWP, wp);
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	spin_unlock_irq(&chip->reg_lock);

	return 0;
}

#define ICH6_RIRB_EX_UNSOL_EV	(1<<4)

/* retrieve RIRB entry - called from interrupt handler */
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static void azx_update_rirb(struct azx *chip)
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{
	unsigned int rp, wp;
890
	unsigned int addr;
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	u32 res, res_ex;

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	wp = azx_readw(chip, RIRBWP);
	if (wp == 0xffff) {
		/* something wrong, controller likely turned to D3 */
		return;
	}

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	if (wp == chip->rirb.wp)
		return;
	chip->rirb.wp = wp;
902

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	while (chip->rirb.rp != wp) {
		chip->rirb.rp++;
		chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;

		rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
		res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
		res = le32_to_cpu(chip->rirb.buf[rp]);
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		addr = azx_response_addr(res_ex);
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		if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
			snd_hda_queue_unsol_event(chip->bus, res, res_ex);
913 914
		else if (chip->rirb.cmds[addr]) {
			chip->rirb.res[addr] = res;
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			smp_wmb();
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			chip->rirb.cmds[addr]--;
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		} else if (printk_ratelimit()) {
			snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, last cmd=%#08x\n",
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				   pci_name(chip->pci),
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				   res, res_ex,
				   chip->last_cmd[addr]);
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		}
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	}
}

/* receive a response */
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static unsigned int azx_rirb_get_response(struct hda_bus *bus,
					  unsigned int addr)
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{
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	struct azx *chip = bus->private_data;
931
	unsigned long timeout;
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	unsigned long loopcounter;
933
	int do_poll = 0;
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 again:
	timeout = jiffies + msecs_to_jiffies(1000);
937 938

	for (loopcounter = 0;; loopcounter++) {
939
		if (chip->polling_mode || do_poll) {
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			spin_lock_irq(&chip->reg_lock);
			azx_update_rirb(chip);
			spin_unlock_irq(&chip->reg_lock);
		}
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		if (!chip->rirb.cmds[addr]) {
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			smp_rmb();
946
			bus->rirb_error = 0;
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			if (!do_poll)
				chip->poll_count = 0;
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			return chip->rirb.res[addr]; /* the last value */
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		}
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		if (time_after(jiffies, timeout))
			break;
954
		if (bus->needs_damn_long_delay || loopcounter > 3000)
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			msleep(2); /* temporary workaround */
		else {
			udelay(10);
			cond_resched();
		}
960
	}
961

962 963 964
	if (!bus->no_response_fallback)
		return -1;

965
	if (!chip->polling_mode && chip->poll_count < 2) {
966
		snd_printdd(SFX "%s: azx_get_response timeout, "
967
			   "polling the codec once: last cmd=0x%08x\n",
968
			   pci_name(chip->pci), chip->last_cmd[addr]);
969 970 971 972 973 974
		do_poll = 1;
		chip->poll_count++;
		goto again;
	}


975
	if (!chip->polling_mode) {
976
		snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
977
			   "switching to polling mode: last cmd=0x%08x\n",
978
			   pci_name(chip->pci), chip->last_cmd[addr]);
979 980 981 982
		chip->polling_mode = 1;
		goto again;
	}

983
	if (chip->msi) {
984
		snd_printk(KERN_WARNING SFX "%s: No response from codec, "
985
			   "disabling MSI: last cmd=0x%08x\n",
986
			   pci_name(chip->pci), chip->last_cmd[addr]);
987 988 989 990
		free_irq(chip->irq, chip);
		chip->irq = -1;
		pci_disable_msi(chip->pci);
		chip->msi = 0;
991 992
		if (azx_acquire_irq(chip, 1) < 0) {
			bus->rirb_error = 1;
993
			return -1;
994
		}
995 996 997
		goto again;
	}

998 999 1000 1001 1002 1003 1004 1005
	if (chip->probing) {
		/* If this critical timeout happens during the codec probing
		 * phase, this is likely an access to a non-existing codec
		 * slot.  Better to return an error and reset the system.
		 */
		return -1;
	}

1006 1007 1008
	/* a fatal communication error; need either to reset or to fallback
	 * to the single_cmd mode
	 */
1009
	bus->rirb_error = 1;
1010
	if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1011 1012 1013 1014 1015 1016
		bus->response_reset = 1;
		return -1; /* give a chance to retry */
	}

	snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
		   "switching to single_cmd mode: last cmd=0x%08x\n",
1017
		   chip->last_cmd[addr]);
1018 1019
	chip->single_cmd = 1;
	bus->response_reset = 0;
1020
	/* release CORB/RIRB */
1021
	azx_free_cmd_io(chip);
1022 1023
	/* disable unsolicited responses */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1024
	return -1;
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1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
}

/*
 * Use the single immediate command instead of CORB/RIRB for simplicity
 *
 * Note: according to Intel, this is not preferred use.  The command was
 *       intended for the BIOS only, and may get confused with unsolicited
 *       responses.  So, we shouldn't use it for normal operation from the
 *       driver.
 *       I left the codes, however, for debugging/testing purposes.
 */

1037
/* receive a response */
1038
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1039 1040 1041 1042 1043 1044 1045
{
	int timeout = 50;

	while (timeout--) {
		/* check IRV busy bit */
		if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
			/* reuse rirb.res as the response return value */
1046
			chip->rirb.res[addr] = azx_readl(chip, IR);
1047 1048 1049 1050 1051
			return 0;
		}
		udelay(1);
	}
	if (printk_ratelimit())
1052 1053
		snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
			   pci_name(chip->pci), azx_readw(chip, IRS));
1054
	chip->rirb.res[addr] = -1;
1055 1056 1057
	return -EIO;
}

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1058
/* send a command */
1059
static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
L
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1060
{
1061
	struct azx *chip = bus->private_data;
1062
	unsigned int addr = azx_command_addr(val);
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1063 1064
	int timeout = 50;

1065
	bus->rirb_error = 0;
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1066 1067
	while (timeout--) {
		/* check ICB busy bit */
1068
		if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
L
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1069
			/* Clear IRV valid bit */
1070 1071
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_VALID);
L
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1072
			azx_writel(chip, IC, val);
1073 1074
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_BUSY);
1075
			return azx_single_wait_for_response(chip, addr);
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1076 1077 1078
		}
		udelay(1);
	}
1079
	if (printk_ratelimit())
1080 1081
		snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
			   pci_name(chip->pci), azx_readw(chip, IRS), val);
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	return -EIO;
}

/* receive a response */
1086 1087
static unsigned int azx_single_get_response(struct hda_bus *bus,
					    unsigned int addr)
L
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1088
{
1089
	struct azx *chip = bus->private_data;
1090
	return chip->rirb.res[addr];
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1091 1092
}

1093 1094 1095 1096 1097 1098 1099 1100
/*
 * The below are the main callbacks from hda_codec.
 *
 * They are just the skeleton to call sub-callbacks according to the
 * current setting of chip->single_cmd.
 */

/* send a command */
1101
static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1102
{
1103
	struct azx *chip = bus->private_data;
1104

1105 1106
	if (chip->disabled)
		return 0;
1107
	chip->last_cmd[azx_command_addr(val)] = val;
1108
	if (chip->single_cmd)
1109
		return azx_single_send_cmd(bus, val);
1110
	else
1111
		return azx_corb_send_cmd(bus, val);
1112 1113 1114
}

/* get a response */
1115 1116
static unsigned int azx_get_response(struct hda_bus *bus,
				     unsigned int addr)
1117
{
1118
	struct azx *chip = bus->private_data;
1119 1120
	if (chip->disabled)
		return 0;
1121
	if (chip->single_cmd)
1122
		return azx_single_get_response(bus, addr);
1123
	else
1124
		return azx_rirb_get_response(bus, addr);
1125 1126
}

1127
#ifdef CONFIG_PM
1128
static void azx_power_notify(struct hda_bus *bus, bool power_up);
1129
#endif
1130

1131 1132 1133 1134 1135 1136 1137 1138 1139
#ifdef CONFIG_SND_HDA_DSP_LOADER
static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
				unsigned int byte_size,
				struct snd_dma_buffer *bufp);
static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
static void azx_load_dsp_cleanup(struct hda_bus *bus,
				 struct snd_dma_buffer *dmab);
#endif

1140
/* enter link reset */
1141
static void azx_enter_link_reset(struct azx *chip)
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
{
	unsigned long timeout;

	/* reset controller */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);

	timeout = jiffies + msecs_to_jiffies(100);
	while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
			time_before(jiffies, timeout))
		usleep_range(500, 1000);
}

1154 1155
/* exit link reset */
static void azx_exit_link_reset(struct azx *chip)
L
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1156
{
1157
	unsigned long timeout;
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1158

1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169
	azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);

	timeout = jiffies + msecs_to_jiffies(100);
	while (!azx_readb(chip, GCTL) &&
			time_before(jiffies, timeout))
		usleep_range(500, 1000);
}

/* reset codec link */
static int azx_reset(struct azx *chip, int full_reset)
{
1170 1171 1172
	if (!full_reset)
		goto __skip;

1173
	/* clear STATESTS */
1174
	azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1175

L
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1176
	/* reset controller */
1177
	azx_enter_link_reset(chip);
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1178 1179 1180 1181

	/* delay for >= 100us for codec PLL to settle per spec
	 * Rev 0.9 section 5.5.1
	 */
1182
	usleep_range(500, 1000);
L
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1183 1184

	/* Bring controller out of reset */
1185
	azx_exit_link_reset(chip);
L
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1186

1187
	/* Brent Chartrand said to wait >= 540us for codecs to initialize */
1188
	usleep_range(1000, 1200);
L
Linus Torvalds 已提交
1189

1190
      __skip:
L
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1191
	/* check to see if controller is ready */
1192
	if (!azx_readb(chip, GCTL)) {
1193
		snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
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1194 1195 1196
		return -EBUSY;
	}

M
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1197
	/* Accept unsolicited responses */
1198 1199 1200
	if (!chip->single_cmd)
		azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
			   ICH6_GCTL_UNSOL);
M
Matt 已提交
1201

L
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1202
	/* detect codecs */
1203
	if (!chip->codec_mask) {
L
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1204
		chip->codec_mask = azx_readw(chip, STATESTS);
1205
		snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
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	}

	return 0;
}


/*
 * Lowlevel interface
 */  

/* enable interrupts */
1217
static void azx_int_enable(struct azx *chip)
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{
	/* enable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
		   ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
}

/* disable interrupts */
1225
static void azx_int_disable(struct azx *chip)
L
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1226 1227 1228 1229
{
	int i;

	/* disable interrupts in stream descriptor */
1230
	for (i = 0; i < chip->num_streams; i++) {
1231
		struct azx_dev *azx_dev = &chip->azx_dev[i];
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1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244
		azx_sd_writeb(azx_dev, SD_CTL,
			      azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
	}

	/* disable SIE for all streams */
	azx_writeb(chip, INTCTL, 0);

	/* disable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
		   ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
}

/* clear interrupts */
1245
static void azx_int_clear(struct azx *chip)
L
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1246 1247 1248 1249
{
	int i;

	/* clear stream status */
1250
	for (i = 0; i < chip->num_streams; i++) {
1251
		struct azx_dev *azx_dev = &chip->azx_dev[i];
L
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1252 1253 1254 1255
		azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
	}

	/* clear STATESTS */
1256
	azx_writew(chip, STATESTS, STATESTS_INT_MASK);
L
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1257 1258 1259 1260 1261 1262 1263 1264 1265

	/* clear rirb status */
	azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);

	/* clear int status */
	azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
}

/* start a stream */
1266
static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
L
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1267
{
1268 1269 1270 1271 1272
	/*
	 * Before stream start, initialize parameter
	 */
	azx_dev->insufficient = 1;

L
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1273
	/* enable SIE */
1274 1275
	azx_writel(chip, INTCTL,
		   azx_readl(chip, INTCTL) | (1 << azx_dev->index));
L
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1276 1277 1278 1279 1280
	/* set DMA start and interrupt mask */
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_DMA_START | SD_INT_MASK);
}

1281 1282
/* stop DMA */
static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
L
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1283 1284 1285 1286
{
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
		      ~(SD_CTL_DMA_START | SD_INT_MASK));
	azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1287 1288 1289 1290 1291 1292
}

/* stop a stream */
static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
{
	azx_stream_clear(chip, azx_dev);
L
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1293
	/* disable SIE */
1294 1295
	azx_writel(chip, INTCTL,
		   azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
L
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1296 1297 1298 1299
}


/*
1300
 * reset and start the controller registers
L
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1301
 */
1302
static void azx_init_chip(struct azx *chip, int full_reset)
L
Linus Torvalds 已提交
1303
{
1304 1305
	if (chip->initialized)
		return;
L
Linus Torvalds 已提交
1306 1307

	/* reset controller */
1308
	azx_reset(chip, full_reset);
L
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1309 1310 1311 1312 1313 1314

	/* initialize interrupts */
	azx_int_clear(chip);
	azx_int_enable(chip);

	/* initialize the codec command I/O */
1315 1316
	if (!chip->single_cmd)
		azx_init_cmd_io(chip);
L
Linus Torvalds 已提交
1317

1318 1319
	/* program the position buffer */
	azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
T
Takashi Iwai 已提交
1320
	azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1321

1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	chip->initialized = 1;
}

/*
 * initialize the PCI registers
 */
/* update bits in a PCI register byte */
static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
			    unsigned char mask, unsigned char val)
{
	unsigned char data;

	pci_read_config_byte(pci, reg, &data);
	data &= ~mask;
	data |= (val & mask);
	pci_write_config_byte(pci, reg, data);
}

static void azx_init_pci(struct azx *chip)
{
	/* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
	 * Ensuring these bits are 0 clears playback static on some HD Audio
1345 1346
	 * codecs.
	 * The PCI register TCSEL is defined in the Intel manuals.
1347
	 */
1348
	if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1349
		snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1350
		update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1351
	}
1352

1353 1354 1355 1356
	/* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
	 * we need to enable snoop.
	 */
	if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1357
		snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1358
		update_pci_byte(chip->pci,
T
Takashi Iwai 已提交
1359 1360
				ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
				azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1361 1362 1363 1364
	}

	/* For NVIDIA HDA, enable snoop */
	if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1365
		snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1366 1367 1368
		update_pci_byte(chip->pci,
				NVIDIA_HDA_TRANSREG_ADDR,
				0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1369 1370 1371 1372 1373 1374
		update_pci_byte(chip->pci,
				NVIDIA_HDA_ISTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
		update_pci_byte(chip->pci,
				NVIDIA_HDA_OSTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
1375 1376 1377 1378
	}

	/* Enable SCH/PCH snoop if needed */
	if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
T
Takashi Iwai 已提交
1379
		unsigned short snoop;
T
Takashi Iwai 已提交
1380
		pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
T
Takashi Iwai 已提交
1381 1382 1383 1384 1385 1386
		if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
		    (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
			snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
			if (!azx_snoop(chip))
				snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
			pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
T
Takashi Iwai 已提交
1387 1388 1389
			pci_read_config_word(chip->pci,
				INTEL_SCH_HDA_DEVC, &snoop);
		}
1390 1391
		snd_printdd(SFX "%s: SCH snoop: %s\n",
				pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
T
Takashi Iwai 已提交
1392
				? "Disabled" : "Enabled");
V
Vinod G 已提交
1393
        }
L
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1394 1395 1396
}


1397 1398
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);

L
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1399 1400 1401
/*
 * interrupt handler
 */
1402
static irqreturn_t azx_interrupt(int irq, void *dev_id)
L
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1403
{
1404 1405
	struct azx *chip = dev_id;
	struct azx_dev *azx_dev;
L
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1406
	u32 status;
1407
	u8 sd_status;
1408
	int i, ok;
L
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1409

1410
#ifdef CONFIG_PM_RUNTIME
1411 1412 1413
	if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
		if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
			return IRQ_NONE;
1414 1415
#endif

L
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1416 1417
	spin_lock(&chip->reg_lock);

1418 1419
	if (chip->disabled) {
		spin_unlock(&chip->reg_lock);
1420
		return IRQ_NONE;
1421
	}
1422

L
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1423
	status = azx_readl(chip, INTSTS);
1424
	if (status == 0 || status == 0xffffffff) {
L
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1425 1426 1427 1428
		spin_unlock(&chip->reg_lock);
		return IRQ_NONE;
	}
	
1429
	for (i = 0; i < chip->num_streams; i++) {
L
Linus Torvalds 已提交
1430 1431
		azx_dev = &chip->azx_dev[i];
		if (status & azx_dev->sd_int_sta_mask) {
1432
			sd_status = azx_sd_readb(azx_dev, SD_STS);
L
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1433
			azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1434 1435
			if (!azx_dev->substream || !azx_dev->running ||
			    !(sd_status & SD_INT_COMPLETE))
1436 1437
				continue;
			/* check whether this IRQ is really acceptable */
1438 1439
			ok = azx_position_ok(chip, azx_dev);
			if (ok == 1) {
1440
				azx_dev->irq_pending = 0;
L
Linus Torvalds 已提交
1441 1442 1443
				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
1444
			} else if (ok == 0 && chip->bus && chip->bus->workq) {
1445 1446
				/* bogus IRQ, process it later */
				azx_dev->irq_pending = 1;
T
Takashi Iwai 已提交
1447 1448
				queue_work(chip->bus->workq,
					   &chip->irq_pending_work);
L
Linus Torvalds 已提交
1449 1450 1451 1452 1453 1454 1455
			}
		}
	}

	/* clear rirb int */
	status = azx_readb(chip, RIRBSTS);
	if (status & RIRB_INT_MASK) {
1456
		if (status & RIRB_INT_RESPONSE) {
1457
			if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1458
				udelay(80);
L
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1459
			azx_update_rirb(chip);
1460
		}
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1461 1462 1463 1464 1465
		azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
	}

#if 0
	/* clear state status int */
1466 1467
	if (azx_readw(chip, STATESTS) & 0x04)
		azx_writew(chip, STATESTS, 0x04);
L
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1468 1469 1470 1471 1472 1473 1474
#endif
	spin_unlock(&chip->reg_lock);
	
	return IRQ_HANDLED;
}


1475 1476 1477
/*
 * set up a BDL entry
 */
1478
static int setup_bdle(struct azx *chip,
1479
		      struct snd_dma_buffer *dmab,
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
		      struct azx_dev *azx_dev, u32 **bdlp,
		      int ofs, int size, int with_ioc)
{
	u32 *bdl = *bdlp;

	while (size > 0) {
		dma_addr_t addr;
		int chunk;

		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
			return -EINVAL;

1492
		addr = snd_sgbuf_get_addr(dmab, ofs);
1493 1494
		/* program the address field of the BDL entry */
		bdl[0] = cpu_to_le32((u32)addr);
T
Takashi Iwai 已提交
1495
		bdl[1] = cpu_to_le32(upper_32_bits(addr));
1496
		/* program the size field of the BDL entry */
1497
		chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1498 1499 1500 1501 1502 1503
		/* one BDLE cannot cross 4K boundary on CTHDA chips */
		if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
			u32 remain = 0x1000 - (ofs & 0xfff);
			if (chunk > remain)
				chunk = remain;
		}
1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517
		bdl[2] = cpu_to_le32(chunk);
		/* program the IOC to enable interrupt
		 * only when the whole fragment is processed
		 */
		size -= chunk;
		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
		bdl += 4;
		azx_dev->frags++;
		ofs += chunk;
	}
	*bdlp = bdl;
	return ofs;
}

L
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1518 1519 1520
/*
 * set up BDL entries
 */
1521 1522
static int azx_setup_periods(struct azx *chip,
			     struct snd_pcm_substream *substream,
T
Takashi Iwai 已提交
1523
			     struct azx_dev *azx_dev)
L
Linus Torvalds 已提交
1524
{
T
Takashi Iwai 已提交
1525 1526
	u32 *bdl;
	int i, ofs, periods, period_bytes;
1527
	int pos_adj;
L
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1528 1529 1530 1531 1532

	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);

1533
	period_bytes = azx_dev->period_bytes;
T
Takashi Iwai 已提交
1534 1535
	periods = azx_dev->bufsize / period_bytes;

L
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1536
	/* program the initial BDL entries */
T
Takashi Iwai 已提交
1537 1538 1539
	bdl = (u32 *)azx_dev->bdl.area;
	ofs = 0;
	azx_dev->frags = 0;
1540
	pos_adj = bdl_pos_adj[chip->dev_index];
1541
	if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1542
		struct snd_pcm_runtime *runtime = substream->runtime;
1543
		int pos_align = pos_adj;
1544
		pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1545
		if (!pos_adj)
1546 1547 1548 1549
			pos_adj = pos_align;
		else
			pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
				pos_align;
1550 1551
		pos_adj = frames_to_bytes(runtime, pos_adj);
		if (pos_adj >= period_bytes) {
1552 1553
			snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
				   pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1554 1555
			pos_adj = 0;
		} else {
1556 1557
			ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
					 azx_dev,
1558
					 &bdl, ofs, pos_adj, true);
1559 1560
			if (ofs < 0)
				goto error;
T
Takashi Iwai 已提交
1561
		}
1562 1563
	} else
		pos_adj = 0;
1564 1565
	for (i = 0; i < periods; i++) {
		if (i == periods - 1 && pos_adj)
1566 1567
			ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
					 azx_dev, &bdl, ofs,
1568 1569
					 period_bytes - pos_adj, 0);
		else
1570 1571
			ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
					 azx_dev, &bdl, ofs,
1572
					 period_bytes,
1573
					 !azx_dev->no_period_wakeup);
1574 1575
		if (ofs < 0)
			goto error;
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1576
	}
T
Takashi Iwai 已提交
1577
	return 0;
1578 1579

 error:
1580 1581
	snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
		   pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1582
	return -EINVAL;
L
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1583 1584
}

1585 1586
/* reset stream */
static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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1587 1588 1589 1590
{
	unsigned char val;
	int timeout;

1591 1592
	azx_stream_clear(chip, azx_dev);

1593 1594
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_STREAM_RESET);
L
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1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608
	udelay(3);
	timeout = 300;
	while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;
	val &= ~SD_CTL_STREAM_RESET;
	azx_sd_writeb(azx_dev, SD_CTL, val);
	udelay(3);

	timeout = 300;
	/* waiting for hardware to report that the stream is out of reset */
	while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;
1609 1610 1611

	/* reset first position - may not be synced with hw at this time */
	*azx_dev->posbuf = 0;
1612
}
L
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1613

1614 1615 1616 1617 1618
/*
 * set up the SD for streaming
 */
static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
{
T
Takashi Iwai 已提交
1619
	unsigned int val;
1620 1621
	/* make sure the run bit is zero for SD */
	azx_stream_clear(chip, azx_dev);
L
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1622
	/* program the stream_tag */
T
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1623 1624 1625 1626 1627 1628
	val = azx_sd_readl(azx_dev, SD_CTL);
	val = (val & ~SD_CTL_STREAM_TAG_MASK) |
		(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
	if (!azx_snoop(chip))
		val |= SD_CTL_TRAFFIC_PRIO;
	azx_sd_writel(azx_dev, SD_CTL, val);
L
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1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641

	/* program the length of samples in cyclic buffer */
	azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);

	/* program the stream format */
	/* this value needs to be the same as the one programmed */
	azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);

	/* program the stream LVI (last valid index) of the BDL */
	azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);

	/* program the BDL address */
	/* lower BDL address */
T
Takashi Iwai 已提交
1642
	azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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1643
	/* upper BDL address */
T
Takashi Iwai 已提交
1644
	azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
L
Linus Torvalds 已提交
1645

1646
	/* enable the position buffer */
1647 1648
	if (chip->position_fix[0] != POS_FIX_LPIB ||
	    chip->position_fix[1] != POS_FIX_LPIB) {
1649 1650 1651 1652
		if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
			azx_writel(chip, DPLBASE,
				(u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
	}
1653

L
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1654
	/* set the interrupt enable bits in the descriptor control register */
1655 1656
	azx_sd_writel(azx_dev, SD_CTL,
		      azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
L
Linus Torvalds 已提交
1657 1658 1659 1660

	return 0;
}

1661 1662 1663 1664 1665 1666 1667 1668 1669
/*
 * Probe the given codec address
 */
static int probe_codec(struct azx *chip, int addr)
{
	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
	unsigned int res;

1670
	mutex_lock(&chip->bus->cmd_mutex);
1671 1672
	chip->probing = 1;
	azx_send_cmd(chip->bus, cmd);
1673
	res = azx_get_response(chip->bus, addr);
1674
	chip->probing = 0;
1675
	mutex_unlock(&chip->bus->cmd_mutex);
1676 1677
	if (res == -1)
		return -EIO;
1678
	snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1679 1680 1681
	return 0;
}

1682 1683
static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
				 struct hda_pcm *cpcm);
1684
static void azx_stop_chip(struct azx *chip);
L
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1685

1686 1687 1688 1689 1690 1691
static void azx_bus_reset(struct hda_bus *bus)
{
	struct azx *chip = bus->private_data;

	bus->in_reset = 1;
	azx_stop_chip(chip);
1692
	azx_init_chip(chip, 1);
1693
#ifdef CONFIG_PM
1694
	if (chip->initialized) {
1695 1696 1697
		struct azx_pcm *p;
		list_for_each_entry(p, &chip->pcm_list, list)
			snd_pcm_suspend_all(p->pcm);
1698 1699 1700
		snd_hda_suspend(chip->bus);
		snd_hda_resume(chip->bus);
	}
1701
#endif
1702 1703 1704
	bus->in_reset = 0;
}

1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720
static int get_jackpoll_interval(struct azx *chip)
{
	int i = jackpoll_ms[chip->dev_index];
	unsigned int j;
	if (i == 0)
		return 0;
	if (i < 50 || i > 60000)
		j = 0;
	else
		j = msecs_to_jiffies(i);
	if (j == 0)
		snd_printk(KERN_WARNING SFX
			   "jackpoll_ms value out of range: %d\n", i);
	return j;
}

L
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1721 1722 1723 1724
/*
 * Codec initialization
 */

1725
/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1726
static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1727
	[AZX_DRIVER_NVIDIA] = 8,
1728
	[AZX_DRIVER_TERA] = 1,
1729 1730
};

1731
static int azx_codec_create(struct azx *chip, const char *model)
L
Linus Torvalds 已提交
1732 1733
{
	struct hda_bus_template bus_temp;
1734 1735
	int c, codecs, err;
	int max_slots;
L
Linus Torvalds 已提交
1736 1737 1738 1739 1740

	memset(&bus_temp, 0, sizeof(bus_temp));
	bus_temp.private_data = chip;
	bus_temp.modelname = model;
	bus_temp.pci = chip->pci;
1741 1742
	bus_temp.ops.command = azx_send_cmd;
	bus_temp.ops.get_response = azx_get_response;
1743
	bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1744
	bus_temp.ops.bus_reset = azx_bus_reset;
1745
#ifdef CONFIG_PM
1746
	bus_temp.power_save = &power_save;
1747 1748
	bus_temp.ops.pm_notify = azx_power_notify;
#endif
1749 1750 1751 1752 1753
#ifdef CONFIG_SND_HDA_DSP_LOADER
	bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
	bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
	bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
#endif
L
Linus Torvalds 已提交
1754

1755 1756
	err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
	if (err < 0)
L
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1757 1758
		return err;

1759
	if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1760
		snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1761
		chip->bus->needs_damn_long_delay = 1;
1762
	}
1763

1764
	codecs = 0;
1765 1766
	max_slots = azx_max_codecs[chip->driver_type];
	if (!max_slots)
1767
		max_slots = AZX_DEFAULT_CODECS;
1768 1769 1770

	/* First try to probe all given codec slots */
	for (c = 0; c < max_slots; c++) {
1771
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1772 1773 1774 1775
			if (probe_codec(chip, c) < 0) {
				/* Some BIOSen give you wrong codec addresses
				 * that don't exist
				 */
1776
				snd_printk(KERN_WARNING SFX
1777 1778
					   "%s: Codec #%d probe error; "
					   "disabling it...\n", pci_name(chip->pci), c);
1779 1780 1781
				chip->codec_mask &= ~(1 << c);
				/* More badly, accessing to a non-existing
				 * codec often screws up the controller chip,
P
Paul Menzel 已提交
1782
				 * and disturbs the further communications.
1783 1784 1785 1786 1787
				 * Thus if an error occurs during probing,
				 * better to reset the controller chip to
				 * get back to the sanity state.
				 */
				azx_stop_chip(chip);
1788
				azx_init_chip(chip, 1);
1789 1790 1791 1792
			}
		}
	}

1793 1794 1795 1796
	/* AMD chipsets often cause the communication stalls upon certain
	 * sequence like the pin-detection.  It seems that forcing the synced
	 * access works around the stall.  Grrr...
	 */
1797
	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1798 1799
		snd_printd(SFX "%s: Enable sync_write for stable communication\n",
			pci_name(chip->pci));
1800 1801 1802 1803
		chip->bus->sync_write = 1;
		chip->bus->allow_bus_reset = 1;
	}

1804
	/* Then create codec instances */
1805
	for (c = 0; c < max_slots; c++) {
1806
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1807
			struct hda_codec *codec;
1808
			err = snd_hda_codec_new(chip->bus, c, &codec);
L
Linus Torvalds 已提交
1809 1810
			if (err < 0)
				continue;
1811
			codec->jackpoll_interval = get_jackpoll_interval(chip);
1812
			codec->beep_mode = chip->beep_mode;
L
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1813
			codecs++;
1814 1815 1816
		}
	}
	if (!codecs) {
1817
		snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
L
Linus Torvalds 已提交
1818 1819
		return -ENXIO;
	}
1820 1821
	return 0;
}
L
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1822

1823
/* configure each codec instance */
1824
static int azx_codec_configure(struct azx *chip)
1825 1826 1827 1828 1829
{
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list) {
		snd_hda_codec_configure(codec);
	}
L
Linus Torvalds 已提交
1830 1831 1832 1833 1834 1835 1836 1837 1838
	return 0;
}


/*
 * PCM support
 */

/* assign a stream for the PCM */
1839 1840
static inline struct azx_dev *
azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
L
Linus Torvalds 已提交
1841
{
1842
	int dev, i, nums;
1843
	struct azx_dev *res = NULL;
1844 1845 1846
	/* make a non-zero unique key for the substream */
	int key = (substream->pcm->device << 16) | (substream->number << 2) |
		(substream->stream + 1);
1847 1848

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1849 1850 1851 1852 1853 1854
		dev = chip->playback_index_offset;
		nums = chip->playback_streams;
	} else {
		dev = chip->capture_index_offset;
		nums = chip->capture_streams;
	}
1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865
	for (i = 0; i < nums; i++, dev++) {
		struct azx_dev *azx_dev = &chip->azx_dev[dev];
		dsp_lock(azx_dev);
		if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
			res = azx_dev;
			if (res->assigned_key == key) {
				res->opened = 1;
				res->assigned_key = key;
				dsp_unlock(azx_dev);
				return azx_dev;
			}
L
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1866
		}
1867 1868
		dsp_unlock(azx_dev);
	}
1869
	if (res) {
1870
		dsp_lock(res);
1871
		res->opened = 1;
1872
		res->assigned_key = key;
1873
		dsp_unlock(res);
1874 1875
	}
	return res;
L
Linus Torvalds 已提交
1876 1877 1878
}

/* release the assigned stream */
1879
static inline void azx_release_device(struct azx_dev *azx_dev)
L
Linus Torvalds 已提交
1880 1881 1882 1883
{
	azx_dev->opened = 0;
}

1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
static cycle_t azx_cc_read(const struct cyclecounter *cc)
{
	struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
	struct snd_pcm_substream *substream = azx_dev->substream;
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;

	return azx_readl(chip, WALLCLK);
}

static void azx_timecounter_init(struct snd_pcm_substream *substream,
				bool force, cycle_t last)
{
	struct azx_dev *azx_dev = get_azx_dev(substream);
	struct timecounter *tc = &azx_dev->azx_tc;
	struct cyclecounter *cc = &azx_dev->azx_cc;
	u64 nsec;

	cc->read = azx_cc_read;
	cc->mask = CLOCKSOURCE_MASK(32);

	/*
	 * Converting from 24 MHz to ns means applying a 125/3 factor.
	 * To avoid any saturation issues in intermediate operations,
	 * the 125 factor is applied first. The division is applied
	 * last after reading the timecounter value.
	 * Applying the 1/3 factor as part of the multiplication
	 * requires at least 20 bits for a decent precision, however
	 * overflows occur after about 4 hours or less, not a option.
	 */

	cc->mult = 125; /* saturation after 195 years */
	cc->shift = 0;

	nsec = 0; /* audio time is elapsed time since trigger */
	timecounter_init(tc, cc, nsec);
	if (force)
		/*
		 * force timecounter to use predefined value,
		 * used for synchronized starts
		 */
		tc->cycle_last = last;
}

1928
static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941
				u64 nsec)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
	u64 codec_frames, codec_nsecs;

	if (!hinfo->ops.get_delay)
		return nsec;

	codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
	codec_nsecs = div_u64(codec_frames * 1000000000LL,
			      substream->runtime->rate);

1942 1943 1944
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		return nsec + codec_nsecs;

1945 1946 1947
	return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
}

1948 1949 1950 1951 1952 1953 1954 1955
static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
				struct timespec *ts)
{
	struct azx_dev *azx_dev = get_azx_dev(substream);
	u64 nsec;

	nsec = timecounter_read(&azx_dev->azx_tc);
	nsec = div_u64(nsec, 3); /* can be optimized */
1956
	nsec = azx_adjust_codec_delay(substream, nsec);
1957 1958 1959 1960 1961 1962

	*ts = ns_to_timespec(nsec);

	return 0;
}

1963
static struct snd_pcm_hardware azx_pcm_hw = {
1964 1965
	.info =			(SNDRV_PCM_INFO_MMAP |
				 SNDRV_PCM_INFO_INTERLEAVED |
L
Linus Torvalds 已提交
1966 1967
				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
				 SNDRV_PCM_INFO_MMAP_VALID |
1968 1969
				 /* No full-resume yet implemented */
				 /* SNDRV_PCM_INFO_RESUME |*/
1970
				 SNDRV_PCM_INFO_PAUSE |
1971
				 SNDRV_PCM_INFO_SYNC_START |
1972
				 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1973
				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
L
Linus Torvalds 已提交
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987
	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
	.rates =		SNDRV_PCM_RATE_48000,
	.rate_min =		48000,
	.rate_max =		48000,
	.channels_min =		2,
	.channels_max =		2,
	.buffer_bytes_max =	AZX_MAX_BUF_SIZE,
	.period_bytes_min =	128,
	.period_bytes_max =	AZX_MAX_BUF_SIZE / 2,
	.periods_min =		2,
	.periods_max =		AZX_MAX_FRAG,
	.fifo_size =		0,
};

1988
static int azx_pcm_open(struct snd_pcm_substream *substream)
L
Linus Torvalds 已提交
1989 1990 1991
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1992 1993 1994
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev;
	struct snd_pcm_runtime *runtime = substream->runtime;
L
Linus Torvalds 已提交
1995 1996
	unsigned long flags;
	int err;
1997
	int buff_step;
L
Linus Torvalds 已提交
1998

1999
	mutex_lock(&chip->open_mutex);
2000
	azx_dev = azx_assign_device(chip, substream);
L
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2001
	if (azx_dev == NULL) {
2002
		mutex_unlock(&chip->open_mutex);
L
Linus Torvalds 已提交
2003 2004 2005 2006 2007 2008 2009 2010 2011
		return -EBUSY;
	}
	runtime->hw = azx_pcm_hw;
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;
	snd_pcm_limit_hw_rates(runtime);
	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2012 2013 2014 2015 2016 2017

	/* avoid wrap-around with wall-clock */
	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
				20,
				178000000);

2018
	if (chip->align_buffer_size)
2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
		/* constrain buffer sizes to be multiple of 128
		   bytes. This is more efficient in terms of memory
		   access but isn't required by the HDA spec and
		   prevents users from specifying exact period/buffer
		   sizes. For example for 44.1kHz, a period size set
		   to 20ms will be rounded to 19.59ms. */
		buff_step = 128;
	else
		/* Don't enforce steps on buffer sizes, still need to
		   be multiple of 4 bytes (HDA spec). Tested on Intel
		   HDA controllers, may not work on all devices where
		   option needs to be disabled */
		buff_step = 4;

2033
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2034
				   buff_step);
2035
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2036
				   buff_step);
2037
	snd_hda_power_up_d3wait(apcm->codec);
2038 2039
	err = hinfo->ops.open(hinfo, apcm->codec, substream);
	if (err < 0) {
L
Linus Torvalds 已提交
2040
		azx_release_device(azx_dev);
2041
		snd_hda_power_down(apcm->codec);
2042
		mutex_unlock(&chip->open_mutex);
L
Linus Torvalds 已提交
2043 2044
		return err;
	}
2045
	snd_pcm_limit_hw_rates(runtime);
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
	/* sanity check */
	if (snd_BUG_ON(!runtime->hw.channels_min) ||
	    snd_BUG_ON(!runtime->hw.channels_max) ||
	    snd_BUG_ON(!runtime->hw.formats) ||
	    snd_BUG_ON(!runtime->hw.rates)) {
		azx_release_device(azx_dev);
		hinfo->ops.close(hinfo, apcm->codec, substream);
		snd_hda_power_down(apcm->codec);
		mutex_unlock(&chip->open_mutex);
		return -EINVAL;
	}
2057 2058 2059 2060 2061 2062

	/* disable WALLCLOCK timestamps for capture streams
	   until we figure out how to handle digital inputs */
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;

L
Linus Torvalds 已提交
2063 2064 2065 2066 2067 2068
	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = substream;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	runtime->private_data = azx_dev;
2069
	snd_pcm_set_sync(substream);
2070
	mutex_unlock(&chip->open_mutex);
L
Linus Torvalds 已提交
2071 2072 2073
	return 0;
}

2074
static int azx_pcm_close(struct snd_pcm_substream *substream)
L
Linus Torvalds 已提交
2075 2076 2077
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2078 2079
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
L
Linus Torvalds 已提交
2080 2081
	unsigned long flags;

2082
	mutex_lock(&chip->open_mutex);
L
Linus Torvalds 已提交
2083 2084 2085 2086 2087 2088
	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = NULL;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	azx_release_device(azx_dev);
	hinfo->ops.close(hinfo, apcm->codec, substream);
2089
	snd_hda_power_down(apcm->codec);
2090
	mutex_unlock(&chip->open_mutex);
L
Linus Torvalds 已提交
2091 2092 2093
	return 0;
}

2094 2095
static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *hw_params)
L
Linus Torvalds 已提交
2096
{
T
Takashi Iwai 已提交
2097 2098
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
2099
	struct azx_dev *azx_dev = get_azx_dev(substream);
T
Takashi Iwai 已提交
2100
	int ret;
2101

2102 2103 2104 2105 2106 2107
	dsp_lock(azx_dev);
	if (dsp_is_locked(azx_dev)) {
		ret = -EBUSY;
		goto unlock;
	}

2108
	mark_runtime_wc(chip, azx_dev, substream, false);
2109 2110 2111
	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
T
Takashi Iwai 已提交
2112
	ret = snd_pcm_lib_malloc_pages(substream,
2113
					params_buffer_bytes(hw_params));
T
Takashi Iwai 已提交
2114
	if (ret < 0)
2115
		goto unlock;
2116
	mark_runtime_wc(chip, azx_dev, substream, true);
2117 2118
 unlock:
	dsp_unlock(azx_dev);
T
Takashi Iwai 已提交
2119
	return ret;
L
Linus Torvalds 已提交
2120 2121
}

2122
static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
L
Linus Torvalds 已提交
2123 2124
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2125
	struct azx_dev *azx_dev = get_azx_dev(substream);
T
Takashi Iwai 已提交
2126
	struct azx *chip = apcm->chip;
L
Linus Torvalds 已提交
2127 2128 2129
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];

	/* reset BDL address */
2130 2131 2132 2133 2134 2135 2136 2137 2138
	dsp_lock(azx_dev);
	if (!dsp_is_locked(azx_dev)) {
		azx_sd_writel(azx_dev, SD_BDLPL, 0);
		azx_sd_writel(azx_dev, SD_BDLPU, 0);
		azx_sd_writel(azx_dev, SD_CTL, 0);
		azx_dev->bufsize = 0;
		azx_dev->period_bytes = 0;
		azx_dev->format_val = 0;
	}
L
Linus Torvalds 已提交
2139

2140
	snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
L
Linus Torvalds 已提交
2141

2142
	mark_runtime_wc(chip, azx_dev, substream, false);
2143 2144
	azx_dev->prepared = 0;
	dsp_unlock(azx_dev);
L
Linus Torvalds 已提交
2145 2146 2147
	return snd_pcm_lib_free_pages(substream);
}

2148
static int azx_pcm_prepare(struct snd_pcm_substream *substream)
L
Linus Torvalds 已提交
2149 2150
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2151 2152
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
L
Linus Torvalds 已提交
2153
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2154
	struct snd_pcm_runtime *runtime = substream->runtime;
2155
	unsigned int bufsize, period_bytes, format_val, stream_tag;
2156
	int err;
2157 2158 2159
	struct hda_spdif_out *spdif =
		snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
	unsigned short ctls = spdif ? spdif->ctls : 0;
L
Linus Torvalds 已提交
2160

2161 2162 2163 2164 2165 2166
	dsp_lock(azx_dev);
	if (dsp_is_locked(azx_dev)) {
		err = -EBUSY;
		goto unlock;
	}

2167
	azx_stream_reset(chip, azx_dev);
2168 2169 2170
	format_val = snd_hda_calc_stream_format(runtime->rate,
						runtime->channels,
						runtime->format,
2171
						hinfo->maxbps,
2172
						ctls);
2173
	if (!format_val) {
2174
		snd_printk(KERN_ERR SFX
2175 2176
			   "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
			   pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2177 2178
		err = -EINVAL;
		goto unlock;
L
Linus Torvalds 已提交
2179 2180
	}

2181 2182 2183
	bufsize = snd_pcm_lib_buffer_bytes(substream);
	period_bytes = snd_pcm_lib_period_bytes(substream);

2184 2185
	snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
		    pci_name(chip->pci), bufsize, format_val);
2186 2187 2188

	if (bufsize != azx_dev->bufsize ||
	    period_bytes != azx_dev->period_bytes ||
2189 2190
	    format_val != azx_dev->format_val ||
	    runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2191 2192 2193
		azx_dev->bufsize = bufsize;
		azx_dev->period_bytes = period_bytes;
		azx_dev->format_val = format_val;
2194
		azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2195 2196
		err = azx_setup_periods(chip, substream, azx_dev);
		if (err < 0)
2197
			goto unlock;
2198 2199
	}

2200 2201 2202
	/* wallclk has 24Mhz clock source */
	azx_dev->period_wallclk = (((runtime->period_size * 24000) /
						runtime->rate) * 1000);
L
Linus Torvalds 已提交
2203 2204 2205 2206 2207 2208
	azx_setup_controller(chip, azx_dev);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
	else
		azx_dev->fifo_size = 0;

2209 2210
	stream_tag = azx_dev->stream_tag;
	/* CA-IBG chips need the playback stream starting from 1 */
2211
	if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2212 2213
	    stream_tag > chip->capture_streams)
		stream_tag -= chip->capture_streams;
2214
	err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2215
				     azx_dev->format_val, substream);
2216 2217 2218 2219 2220 2221

 unlock:
	if (!err)
		azx_dev->prepared = 1;
	dsp_unlock(azx_dev);
	return err;
L
Linus Torvalds 已提交
2222 2223
}

2224
static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
L
Linus Torvalds 已提交
2225 2226
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2227
	struct azx *chip = apcm->chip;
2228 2229
	struct azx_dev *azx_dev;
	struct snd_pcm_substream *s;
2230
	int rstart = 0, start, nsync = 0, sbits = 0;
2231
	int nwait, timeout;
L
Linus Torvalds 已提交
2232

2233 2234 2235
	azx_dev = get_azx_dev(substream);
	trace_azx_pcm_trigger(chip, azx_dev, cmd);

2236 2237 2238
	if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
		return -EPIPE;

L
Linus Torvalds 已提交
2239
	switch (cmd) {
2240 2241
	case SNDRV_PCM_TRIGGER_START:
		rstart = 1;
L
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2242 2243
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
2244
		start = 1;
L
Linus Torvalds 已提交
2245 2246
		break;
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2247
	case SNDRV_PCM_TRIGGER_SUSPEND:
L
Linus Torvalds 已提交
2248
	case SNDRV_PCM_TRIGGER_STOP:
2249
		start = 0;
L
Linus Torvalds 已提交
2250 2251
		break;
	default:
2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264
		return -EINVAL;
	}

	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
		sbits |= 1 << azx_dev->index;
		nsync++;
		snd_pcm_trigger_done(s, substream);
	}

	spin_lock(&chip->reg_lock);
2265 2266 2267 2268 2269 2270 2271 2272

	/* first, set SYNC bits of corresponding streams */
	if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
		azx_writel(chip, OLD_SSYNC,
			azx_readl(chip, OLD_SSYNC) | sbits);
	else
		azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);

2273 2274 2275 2276
	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
2277 2278 2279 2280 2281
		if (start) {
			azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
			if (!rstart)
				azx_dev->start_wallclk -=
						azx_dev->period_wallclk;
2282
			azx_stream_start(chip, azx_dev);
2283
		} else {
2284
			azx_stream_stop(chip, azx_dev);
2285
		}
2286
		azx_dev->running = start;
L
Linus Torvalds 已提交
2287 2288
	}
	spin_unlock(&chip->reg_lock);
2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320
	if (start) {
		/* wait until all FIFOs get ready */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (!(azx_sd_readb(azx_dev, SD_STS) &
				      SD_STS_FIFO_READY))
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
	} else {
		/* wait until all RUN bits are cleared */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (azx_sd_readb(azx_dev, SD_CTL) &
				    SD_CTL_DMA_START)
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
L
Linus Torvalds 已提交
2321
	}
2322 2323 2324 2325 2326 2327 2328
	spin_lock(&chip->reg_lock);
	/* reset SYNC bits */
	if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
		azx_writel(chip, OLD_SSYNC,
			azx_readl(chip, OLD_SSYNC) & ~sbits);
	else
		azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344
	if (start) {
		azx_timecounter_init(substream, 0, 0);
		if (nsync > 1) {
			cycle_t cycle_last;

			/* same start cycle for master and group */
			azx_dev = get_azx_dev(substream);
			cycle_last = azx_dev->azx_tc.cycle_last;

			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_timecounter_init(s, 1, cycle_last);
			}
		}
	}
2345
	spin_unlock(&chip->reg_lock);
2346
	return 0;
L
Linus Torvalds 已提交
2347 2348
}

2349 2350 2351 2352 2353 2354 2355 2356 2357
/* get the current DMA position with correction on VIA chips */
static unsigned int azx_via_get_position(struct azx *chip,
					 struct azx_dev *azx_dev)
{
	unsigned int link_pos, mini_pos, bound_pos;
	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
	unsigned int fifo_size;

	link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2358
	if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404
		/* Playback, no problem using link position */
		return link_pos;
	}

	/* Capture */
	/* For new chipset,
	 * use mod to get the DMA position just like old chipset
	 */
	mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
	mod_dma_pos %= azx_dev->period_bytes;

	/* azx_dev->fifo_size can't get FIFO size of in stream.
	 * Get from base address + offset.
	 */
	fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);

	if (azx_dev->insufficient) {
		/* Link position never gather than FIFO size */
		if (link_pos <= fifo_size)
			return 0;

		azx_dev->insufficient = 0;
	}

	if (link_pos <= fifo_size)
		mini_pos = azx_dev->bufsize + link_pos - fifo_size;
	else
		mini_pos = link_pos - fifo_size;

	/* Find nearest previous boudary */
	mod_mini_pos = mini_pos % azx_dev->period_bytes;
	mod_link_pos = link_pos % azx_dev->period_bytes;
	if (mod_link_pos >= fifo_size)
		bound_pos = link_pos - mod_link_pos;
	else if (mod_dma_pos >= mod_mini_pos)
		bound_pos = mini_pos - mod_mini_pos;
	else {
		bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
		if (bound_pos >= azx_dev->bufsize)
			bound_pos = 0;
	}

	/* Calculate real DMA position we want */
	return bound_pos + mod_dma_pos;
}

2405
static unsigned int azx_get_position(struct azx *chip,
2406 2407
				     struct azx_dev *azx_dev,
				     bool with_check)
L
Linus Torvalds 已提交
2408
{
2409 2410
	struct snd_pcm_substream *substream = azx_dev->substream;
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
L
Linus Torvalds 已提交
2411
	unsigned int pos;
2412 2413
	int stream = substream->stream;
	struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2414
	int delay = 0;
L
Linus Torvalds 已提交
2415

2416 2417 2418 2419 2420 2421
	switch (chip->position_fix[stream]) {
	case POS_FIX_LPIB:
		/* read LPIB */
		pos = azx_sd_readl(azx_dev, SD_LPIB);
		break;
	case POS_FIX_VIACOMBO:
2422
		pos = azx_via_get_position(chip, azx_dev);
2423 2424 2425 2426
		break;
	default:
		/* use the position buffer */
		pos = le32_to_cpu(*azx_dev->posbuf);
2427
		if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2428 2429 2430 2431 2432 2433 2434 2435 2436 2437
			if (!pos || pos == (u32)-1) {
				printk(KERN_WARNING
				       "hda-intel: Invalid position buffer, "
				       "using LPIB read method instead.\n");
				chip->position_fix[stream] = POS_FIX_LPIB;
				pos = azx_sd_readl(azx_dev, SD_LPIB);
			} else
				chip->position_fix[stream] = POS_FIX_POSBUF;
		}
		break;
2438
	}
2439

L
Linus Torvalds 已提交
2440 2441
	if (pos >= azx_dev->bufsize)
		pos = 0;
2442 2443

	/* calculate runtime delay from LPIB */
2444
	if (substream->runtime &&
2445 2446 2447 2448 2449 2450 2451 2452 2453 2454
	    chip->position_fix[stream] == POS_FIX_POSBUF &&
	    (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
		unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
		if (stream == SNDRV_PCM_STREAM_PLAYBACK)
			delay = pos - lpib_pos;
		else
			delay = lpib_pos - pos;
		if (delay < 0)
			delay += azx_dev->bufsize;
		if (delay >= azx_dev->period_bytes) {
2455
			snd_printk(KERN_WARNING SFX
2456
				   "%s: Unstable LPIB (%d >= %d); "
2457
				   "disabling LPIB delay counting\n",
2458
				   pci_name(chip->pci), delay, azx_dev->period_bytes);
2459 2460
			delay = 0;
			chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2461
		}
2462
		delay = bytes_to_frames(substream->runtime, delay);
2463
	}
2464 2465 2466 2467 2468 2469 2470 2471

	if (substream->runtime) {
		if (hinfo->ops.get_delay)
			delay += hinfo->ops.get_delay(hinfo, apcm->codec,
						      substream);
		substream->runtime->delay = delay;
	}

2472
	trace_azx_get_position(chip, azx_dev, pos, delay);
2473 2474 2475 2476 2477 2478 2479 2480 2481
	return pos;
}

static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
	return bytes_to_frames(substream->runtime,
2482
			       azx_get_position(chip, azx_dev, false));
2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495
}

/*
 * Check whether the current DMA position is acceptable for updating
 * periods.  Returns non-zero if it's OK.
 *
 * Many HD-audio controllers appear pretty inaccurate about
 * the update-IRQ timing.  The IRQ is issued before actually the
 * data is processed.  So, we need to process it afterwords in a
 * workqueue.
 */
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
{
2496
	u32 wallclk;
2497 2498
	unsigned int pos;

2499 2500
	wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
	if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2501 2502
		return -1;	/* bogus (too early) interrupt */

2503
	pos = azx_get_position(chip, azx_dev, true);
2504

2505 2506
	if (WARN_ONCE(!azx_dev->period_bytes,
		      "hda-intel: zero azx_dev->period_bytes"))
2507
		return -1; /* this shouldn't happen! */
2508
	if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2509 2510 2511
	    pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
		/* NG - it's below the first next period boundary */
		return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2512
	azx_dev->start_wallclk += wallclk;
2513 2514 2515 2516 2517 2518 2519 2520 2521
	return 1; /* OK, it's fine */
}

/*
 * The work for pending PCM period updates.
 */
static void azx_irq_pending_work(struct work_struct *work)
{
	struct azx *chip = container_of(work, struct azx, irq_pending_work);
2522
	int i, pending, ok;
2523

2524 2525 2526 2527 2528 2529 2530 2531
	if (!chip->irq_pending_warned) {
		printk(KERN_WARNING
		       "hda-intel: IRQ timing workaround is activated "
		       "for card #%d. Suggest a bigger bdl_pos_adj.\n",
		       chip->card->number);
		chip->irq_pending_warned = 1;
	}

2532 2533 2534 2535 2536 2537 2538 2539 2540
	for (;;) {
		pending = 0;
		spin_lock_irq(&chip->reg_lock);
		for (i = 0; i < chip->num_streams; i++) {
			struct azx_dev *azx_dev = &chip->azx_dev[i];
			if (!azx_dev->irq_pending ||
			    !azx_dev->substream ||
			    !azx_dev->running)
				continue;
2541 2542
			ok = azx_position_ok(chip, azx_dev);
			if (ok > 0) {
2543 2544 2545 2546
				azx_dev->irq_pending = 0;
				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
2547 2548
			} else if (ok < 0) {
				pending = 0;	/* too early */
2549 2550 2551 2552 2553 2554
			} else
				pending++;
		}
		spin_unlock_irq(&chip->reg_lock);
		if (!pending)
			return;
2555
		msleep(1);
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567
	}
}

/* clear irq_pending flags and assure no on-going workq */
static void azx_clear_irq_pending(struct azx *chip)
{
	int i;

	spin_lock_irq(&chip->reg_lock);
	for (i = 0; i < chip->num_streams; i++)
		chip->azx_dev[i].irq_pending = 0;
	spin_unlock_irq(&chip->reg_lock);
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2568 2569
}

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2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583
#ifdef CONFIG_X86
static int azx_pcm_mmap(struct snd_pcm_substream *substream,
			struct vm_area_struct *area)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	if (!azx_snoop(chip))
		area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
	return snd_pcm_lib_default_mmap(substream, area);
}
#else
#define azx_pcm_mmap	NULL
#endif

2584
static struct snd_pcm_ops azx_pcm_ops = {
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2585 2586 2587 2588 2589 2590 2591 2592
	.open = azx_pcm_open,
	.close = azx_pcm_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = azx_pcm_hw_params,
	.hw_free = azx_pcm_hw_free,
	.prepare = azx_pcm_prepare,
	.trigger = azx_pcm_trigger,
	.pointer = azx_pcm_pointer,
2593
	.wall_clock =  azx_get_wallclock_tstamp,
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2594
	.mmap = azx_pcm_mmap,
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2595
	.page = snd_pcm_sgbuf_ops_page,
L
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2596 2597
};

2598
static void azx_pcm_free(struct snd_pcm *pcm)
L
Linus Torvalds 已提交
2599
{
2600 2601
	struct azx_pcm *apcm = pcm->private_data;
	if (apcm) {
2602
		list_del(&apcm->list);
2603 2604
		kfree(apcm);
	}
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2605 2606
}

2607 2608
#define MAX_PREALLOC_SIZE	(32 * 1024 * 1024)

2609
static int
2610 2611
azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
		      struct hda_pcm *cpcm)
L
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2612
{
2613
	struct azx *chip = bus->private_data;
2614
	struct snd_pcm *pcm;
L
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2615
	struct azx_pcm *apcm;
2616
	int pcm_dev = cpcm->device;
2617
	unsigned int size;
2618
	int s, err;
L
Linus Torvalds 已提交
2619

2620 2621
	list_for_each_entry(apcm, &chip->pcm_list, list) {
		if (apcm->pcm->device == pcm_dev) {
2622 2623
			snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
				   pci_name(chip->pci), pcm_dev);
2624 2625
			return -EBUSY;
		}
2626 2627 2628 2629
	}
	err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
			  cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
			  cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
L
Linus Torvalds 已提交
2630 2631 2632
			  &pcm);
	if (err < 0)
		return err;
T
Takashi Iwai 已提交
2633
	strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2634
	apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
L
Linus Torvalds 已提交
2635 2636 2637
	if (apcm == NULL)
		return -ENOMEM;
	apcm->chip = chip;
2638
	apcm->pcm = pcm;
L
Linus Torvalds 已提交
2639 2640 2641
	apcm->codec = codec;
	pcm->private_data = apcm;
	pcm->private_free = azx_pcm_free;
2642 2643
	if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
		pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2644
	list_add_tail(&apcm->list, &chip->pcm_list);
2645 2646 2647 2648 2649 2650 2651
	cpcm->pcm = pcm;
	for (s = 0; s < 2; s++) {
		apcm->hinfo[s] = &cpcm->stream[s];
		if (cpcm->stream[s].substreams)
			snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
	}
	/* buffer pre-allocation */
2652 2653 2654
	size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
	if (size > MAX_PREALLOC_SIZE)
		size = MAX_PREALLOC_SIZE;
T
Takashi Iwai 已提交
2655
	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
L
Linus Torvalds 已提交
2656
					      snd_dma_pci_data(chip->pci),
2657
					      size, MAX_PREALLOC_SIZE);
L
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2658 2659 2660 2661 2662 2663
	return 0;
}

/*
 * mixer creation - all stuff is implemented in hda module
 */
2664
static int azx_mixer_create(struct azx *chip)
L
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2665 2666 2667 2668 2669 2670 2671 2672
{
	return snd_hda_build_controls(chip->bus);
}


/*
 * initialize SD streams
 */
2673
static int azx_init_stream(struct azx *chip)
L
Linus Torvalds 已提交
2674 2675 2676 2677
{
	int i;

	/* initialize each stream (aka device)
2678 2679
	 * assign the starting bdl address to each stream (device)
	 * and initialize
L
Linus Torvalds 已提交
2680
	 */
2681
	for (i = 0; i < chip->num_streams; i++) {
2682
		struct azx_dev *azx_dev = &chip->azx_dev[i];
2683
		azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
L
Linus Torvalds 已提交
2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695
		/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
		azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
		/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
		azx_dev->sd_int_sta_mask = 1 << i;
		/* stream tag: must be non-zero and unique */
		azx_dev->index = i;
		azx_dev->stream_tag = i + 1;
	}

	return 0;
}

2696 2697
static int azx_acquire_irq(struct azx *chip, int do_disconnect)
{
2698 2699
	if (request_irq(chip->pci->irq, azx_interrupt,
			chip->msi ? 0 : IRQF_SHARED,
2700
			KBUILD_MODNAME, chip)) {
2701 2702 2703 2704 2705 2706 2707
		printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
		       "disabling device\n", chip->pci->irq);
		if (do_disconnect)
			snd_card_disconnect(chip->card);
		return -1;
	}
	chip->irq = chip->pci->irq;
2708
	pci_intx(chip->pci, !chip->msi);
2709 2710 2711
	return 0;
}

L
Linus Torvalds 已提交
2712

2713 2714
static void azx_stop_chip(struct azx *chip)
{
2715
	if (!chip->initialized)
2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731
		return;

	/* disable interrupts */
	azx_int_disable(chip);
	azx_int_clear(chip);

	/* disable CORB/RIRB */
	azx_free_cmd_io(chip);

	/* disable position buffer */
	azx_writel(chip, DPLBASE, 0);
	azx_writel(chip, DPUBASE, 0);

	chip->initialized = 0;
}

2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
#ifdef CONFIG_SND_HDA_DSP_LOADER
/*
 * DSP loading code (e.g. for CA0132)
 */

/* use the first stream for loading DSP */
static struct azx_dev *
azx_get_dsp_loader_dev(struct azx *chip)
{
	return &chip->azx_dev[chip->playback_index_offset];
}

static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
				unsigned int byte_size,
				struct snd_dma_buffer *bufp)
{
	u32 *bdl;
	struct azx *chip = bus->private_data;
	struct azx_dev *azx_dev;
	int err;

2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765
	azx_dev = azx_get_dsp_loader_dev(chip);

	dsp_lock(azx_dev);
	spin_lock_irq(&chip->reg_lock);
	if (azx_dev->running || azx_dev->locked) {
		spin_unlock_irq(&chip->reg_lock);
		err = -EBUSY;
		goto unlock;
	}
	azx_dev->prepared = 0;
	chip->saved_azx_dev = *azx_dev;
	azx_dev->locked = 1;
	spin_unlock_irq(&chip->reg_lock);
2766 2767 2768 2769 2770

	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
				  snd_dma_pci_data(chip->pci),
				  byte_size, bufp);
	if (err < 0)
2771
		goto err_alloc;
2772

2773
	mark_pages_wc(chip, bufp, true);
2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
	azx_dev->bufsize = byte_size;
	azx_dev->period_bytes = byte_size;
	azx_dev->format_val = format;

	azx_stream_reset(chip, azx_dev);

	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);

	azx_dev->frags = 0;
	bdl = (u32 *)azx_dev->bdl.area;
	err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
	if (err < 0)
		goto error;

	azx_setup_controller(chip, azx_dev);
2791
	dsp_unlock(azx_dev);
2792 2793 2794
	return azx_dev->stream_tag;

 error:
2795 2796
	mark_pages_wc(chip, bufp, false);
	snd_dma_free_pages(bufp);
2797 2798 2799 2800 2801 2802 2803 2804
 err_alloc:
	spin_lock_irq(&chip->reg_lock);
	if (azx_dev->opened)
		*azx_dev = chip->saved_azx_dev;
	azx_dev->locked = 0;
	spin_unlock_irq(&chip->reg_lock);
 unlock:
	dsp_unlock(azx_dev);
2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825
	return err;
}

static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
{
	struct azx *chip = bus->private_data;
	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);

	if (start)
		azx_stream_start(chip, azx_dev);
	else
		azx_stream_stop(chip, azx_dev);
	azx_dev->running = start;
}

static void azx_load_dsp_cleanup(struct hda_bus *bus,
				 struct snd_dma_buffer *dmab)
{
	struct azx *chip = bus->private_data;
	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);

2826
	if (!dmab->area || !azx_dev->locked)
2827 2828
		return;

2829
	dsp_lock(azx_dev);
2830 2831 2832 2833 2834 2835 2836 2837
	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);
	azx_sd_writel(azx_dev, SD_CTL, 0);
	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;

2838
	mark_pages_wc(chip, dmab, false);
2839
	snd_dma_free_pages(dmab);
2840
	dmab->area = NULL;
2841

2842 2843 2844 2845 2846 2847
	spin_lock_irq(&chip->reg_lock);
	if (azx_dev->opened)
		*azx_dev = chip->saved_azx_dev;
	azx_dev->locked = 0;
	spin_unlock_irq(&chip->reg_lock);
	dsp_unlock(azx_dev);
2848 2849 2850
}
#endif /* CONFIG_SND_HDA_DSP_LOADER */

2851
#ifdef CONFIG_PM
2852
/* power-up/down the controller */
2853
static void azx_power_notify(struct hda_bus *bus, bool power_up)
2854
{
2855
	struct azx *chip = bus->private_data;
2856

2857 2858 2859
	if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
		return;

2860
	if (power_up)
2861 2862 2863
		pm_runtime_get_sync(&chip->pci->dev);
	else
		pm_runtime_put_sync(&chip->pci->dev);
2864
}
2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906

static DEFINE_MUTEX(card_list_lock);
static LIST_HEAD(card_list);

static void azx_add_card_list(struct azx *chip)
{
	mutex_lock(&card_list_lock);
	list_add(&chip->list, &card_list);
	mutex_unlock(&card_list_lock);
}

static void azx_del_card_list(struct azx *chip)
{
	mutex_lock(&card_list_lock);
	list_del_init(&chip->list);
	mutex_unlock(&card_list_lock);
}

/* trigger power-save check at writing parameter */
static int param_set_xint(const char *val, const struct kernel_param *kp)
{
	struct azx *chip;
	struct hda_codec *c;
	int prev = power_save;
	int ret = param_set_int(val, kp);

	if (ret || prev == power_save)
		return ret;

	mutex_lock(&card_list_lock);
	list_for_each_entry(chip, &card_list, list) {
		if (!chip->bus || chip->disabled)
			continue;
		list_for_each_entry(c, &chip->bus->codec_list, list)
			snd_hda_power_sync(c);
	}
	mutex_unlock(&card_list_lock);
	return 0;
}
#else
#define azx_add_card_list(chip) /* NOP */
#define azx_del_card_list(chip) /* NOP */
2907
#endif /* CONFIG_PM */
2908

2909
#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2910 2911 2912
/*
 * power management
 */
2913
static int azx_suspend(struct device *dev)
L
Linus Torvalds 已提交
2914
{
2915 2916
	struct pci_dev *pci = to_pci_dev(dev);
	struct snd_card *card = dev_get_drvdata(dev);
T
Takashi Iwai 已提交
2917
	struct azx *chip = card->private_data;
2918
	struct azx_pcm *p;
L
Linus Torvalds 已提交
2919

2920 2921 2922
	if (chip->disabled)
		return 0;

T
Takashi Iwai 已提交
2923
	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2924
	azx_clear_irq_pending(chip);
2925 2926
	list_for_each_entry(p, &chip->pcm_list, list)
		snd_pcm_suspend_all(p->pcm);
2927
	if (chip->initialized)
2928
		snd_hda_suspend(chip->bus);
2929
	azx_stop_chip(chip);
2930
	azx_enter_link_reset(chip);
2931
	if (chip->irq >= 0) {
2932
		free_irq(chip->irq, chip);
2933 2934
		chip->irq = -1;
	}
2935
	if (chip->msi)
2936
		pci_disable_msi(chip->pci);
T
Takashi Iwai 已提交
2937 2938
	pci_disable_device(pci);
	pci_save_state(pci);
2939
	pci_set_power_state(pci, PCI_D3hot);
2940 2941
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
		hda_display_power(false);
L
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2942 2943 2944
	return 0;
}

2945
static int azx_resume(struct device *dev)
L
Linus Torvalds 已提交
2946
{
2947 2948
	struct pci_dev *pci = to_pci_dev(dev);
	struct snd_card *card = dev_get_drvdata(dev);
T
Takashi Iwai 已提交
2949
	struct azx *chip = card->private_data;
L
Linus Torvalds 已提交
2950

2951 2952 2953
	if (chip->disabled)
		return 0;

2954 2955
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
		hda_display_power(true);
2956 2957
	pci_set_power_state(pci, PCI_D0);
	pci_restore_state(pci);
2958 2959 2960 2961 2962 2963 2964
	if (pci_enable_device(pci) < 0) {
		printk(KERN_ERR "hda-intel: pci_enable_device failed, "
		       "disabling device\n");
		snd_card_disconnect(card);
		return -EIO;
	}
	pci_set_master(pci);
2965 2966 2967 2968
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
	if (azx_acquire_irq(chip, 1) < 0)
2969
		return -EIO;
2970
	azx_init_pci(chip);
2971

2972
	azx_init_chip(chip, 1);
2973

L
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2974
	snd_hda_resume(chip->bus);
T
Takashi Iwai 已提交
2975
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
L
Linus Torvalds 已提交
2976 2977
	return 0;
}
2978 2979 2980 2981 2982 2983 2984 2985
#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */

#ifdef CONFIG_PM_RUNTIME
static int azx_runtime_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;

2986 2987 2988 2989 2990 2991
	if (chip->disabled)
		return 0;

	if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
		return 0;

2992 2993 2994 2995
	/* enable controller wake up event */
	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
		  STATESTS_INT_MASK);

2996
	azx_stop_chip(chip);
2997 2998
	if (!chip->bus->avoid_link_reset)
		azx_enter_link_reset(chip);
2999
	azx_clear_irq_pending(chip);
3000 3001
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
		hda_display_power(false);
3002 3003 3004 3005 3006 3007 3008
	return 0;
}

static int azx_runtime_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
3009 3010 3011
	struct hda_bus *bus;
	struct hda_codec *codec;
	int status;
3012

3013 3014 3015 3016 3017 3018
	if (chip->disabled)
		return 0;

	if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
		return 0;

3019 3020
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
		hda_display_power(true);
3021 3022 3023 3024

	/* Read STATESTS before controller reset */
	status = azx_readw(chip, STATESTS);

3025 3026
	azx_init_pci(chip);
	azx_init_chip(chip, 1);
3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039

	bus = chip->bus;
	if (status && bus) {
		list_for_each_entry(codec, &bus->codec_list, list)
			if (status & (1 << codec->addr))
				queue_delayed_work(codec->bus->workq,
						   &codec->jackpoll_work, codec->jackpoll_interval);
	}

	/* disable controller Wake Up event*/
	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
			~STATESTS_INT_MASK);

3040 3041
	return 0;
}
3042 3043 3044 3045 3046 3047

static int azx_runtime_idle(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;

3048 3049 3050
	if (chip->disabled)
		return 0;

3051 3052 3053 3054 3055 3056 3057
	if (!power_save_controller ||
	    !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
		return -EBUSY;

	return 0;
}

3058 3059 3060 3061 3062
#endif /* CONFIG_PM_RUNTIME */

#ifdef CONFIG_PM
static const struct dev_pm_ops azx_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3063
	SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3064 3065
};

3066 3067 3068
#define AZX_PM_OPS	&azx_pm
#else
#define AZX_PM_OPS	NULL
3069
#endif /* CONFIG_PM */
L
Linus Torvalds 已提交
3070 3071


T
Takashi Iwai 已提交
3072 3073 3074 3075 3076 3077
/*
 * reboot notifier for hang-up problem at power-down
 */
static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
{
	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3078
	snd_hda_bus_reboot_notify(chip->bus);
T
Takashi Iwai 已提交
3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094
	azx_stop_chip(chip);
	return NOTIFY_OK;
}

static void azx_notifier_register(struct azx *chip)
{
	chip->reboot_notifier.notifier_call = azx_halt;
	register_reboot_notifier(&chip->reboot_notifier);
}

static void azx_notifier_unregister(struct azx *chip)
{
	if (chip->reboot_notifier.notifier_call)
		unregister_reboot_notifier(&chip->reboot_notifier);
}

3095
static int azx_probe_continue(struct azx *chip);
3096

3097
#ifdef SUPPORT_VGA_SWITCHEROO
3098
static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3099 3100 3101 3102 3103 3104 3105 3106

static void azx_vs_set_state(struct pci_dev *pci,
			     enum vga_switcheroo_state state)
{
	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;
	bool disabled;

3107
	wait_for_completion(&chip->probe_wait);
3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120
	if (chip->init_failed)
		return;

	disabled = (state == VGA_SWITCHEROO_OFF);
	if (chip->disabled == disabled)
		return;

	if (!chip->bus) {
		chip->disabled = disabled;
		if (!disabled) {
			snd_printk(KERN_INFO SFX
				   "%s: Start delayed initialization\n",
				   pci_name(chip->pci));
3121
			if (azx_probe_continue(chip) < 0) {
3122 3123 3124 3125 3126 3127 3128 3129
				snd_printk(KERN_ERR SFX
					   "%s: initialization error\n",
					   pci_name(chip->pci));
				chip->init_failed = true;
			}
		}
	} else {
		snd_printk(KERN_INFO SFX
3130 3131
			   "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
			   disabled ? "Disabling" : "Enabling");
3132
		if (disabled) {
3133
			pm_runtime_put_sync_suspend(&pci->dev);
3134
			azx_suspend(&pci->dev);
3135 3136 3137 3138
			/* when we get suspended by vga switcheroo we end up in D3cold,
			 * however we have no ACPI handle, so pci/acpi can't put us there,
			 * put ourselves there */
			pci->current_state = PCI_D3cold;
3139
			chip->disabled = true;
3140
			if (snd_hda_lock_devices(chip->bus))
3141 3142
				snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
					   pci_name(chip->pci));
3143 3144
		} else {
			snd_hda_unlock_devices(chip->bus);
3145
			pm_runtime_get_noresume(&pci->dev);
3146
			chip->disabled = false;
3147
			azx_resume(&pci->dev);
3148 3149 3150 3151 3152 3153 3154 3155 3156
		}
	}
}

static bool azx_vs_can_switch(struct pci_dev *pci)
{
	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;

3157
	wait_for_completion(&chip->probe_wait);
3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
	if (chip->init_failed)
		return false;
	if (chip->disabled || !chip->bus)
		return true;
	if (snd_hda_lock_devices(chip->bus))
		return false;
	snd_hda_unlock_devices(chip->bus);
	return true;
}

3168
static void init_vga_switcheroo(struct azx *chip)
3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184
{
	struct pci_dev *p = get_bound_vga(chip->pci);
	if (p) {
		snd_printk(KERN_INFO SFX
			   "%s: Handle VGA-switcheroo audio client\n",
			   pci_name(chip->pci));
		chip->use_vga_switcheroo = 1;
		pci_dev_put(p);
	}
}

static const struct vga_switcheroo_client_ops azx_vs_ops = {
	.set_gpu_state = azx_vs_set_state,
	.can_switch = azx_vs_can_switch,
};

3185
static int register_vga_switcheroo(struct azx *chip)
3186
{
3187 3188
	int err;

3189 3190 3191 3192 3193
	if (!chip->use_vga_switcheroo)
		return 0;
	/* FIXME: currently only handling DIS controller
	 * is there any machine with two switchable HDMI audio controllers?
	 */
3194
	err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3195 3196
						    VGA_SWITCHEROO_DIS,
						    chip->bus != NULL);
3197 3198 3199
	if (err < 0)
		return err;
	chip->vga_switcheroo_registered = 1;
3200 3201 3202

	/* register as an optimus hdmi audio power domain */
	vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
3203
	return 0;
3204 3205 3206 3207
}
#else
#define init_vga_switcheroo(chip)		/* NOP */
#define register_vga_switcheroo(chip)		0
3208
#define check_hdmi_disabled(pci)	false
3209 3210
#endif /* SUPPORT_VGA_SWITCHER */

L
Linus Torvalds 已提交
3211 3212 3213
/*
 * destructor
 */
3214
static int azx_free(struct azx *chip)
L
Linus Torvalds 已提交
3215
{
W
Wang Xingchao 已提交
3216
	struct pci_dev *pci = chip->pci;
T
Takashi Iwai 已提交
3217 3218
	int i;

W
Wang Xingchao 已提交
3219 3220 3221 3222
	if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
			&& chip->running)
		pm_runtime_get_noresume(&pci->dev);

3223 3224
	azx_del_card_list(chip);

T
Takashi Iwai 已提交
3225 3226
	azx_notifier_unregister(chip);

3227
	chip->init_failed = 1; /* to be sure */
3228
	complete_all(&chip->probe_wait);
3229

3230 3231 3232
	if (use_vga_switcheroo(chip)) {
		if (chip->disabled && chip->bus)
			snd_hda_unlock_devices(chip->bus);
3233 3234
		if (chip->vga_switcheroo_registered)
			vga_switcheroo_unregister_client(chip->pci);
3235 3236
	}

3237
	if (chip->initialized) {
3238
		azx_clear_irq_pending(chip);
3239
		for (i = 0; i < chip->num_streams; i++)
L
Linus Torvalds 已提交
3240
			azx_stream_stop(chip, &chip->azx_dev[i]);
3241
		azx_stop_chip(chip);
L
Linus Torvalds 已提交
3242 3243
	}

3244
	if (chip->irq >= 0)
L
Linus Torvalds 已提交
3245
		free_irq(chip->irq, (void*)chip);
3246
	if (chip->msi)
3247
		pci_disable_msi(chip->pci);
3248 3249
	if (chip->remap_addr)
		iounmap(chip->remap_addr);
L
Linus Torvalds 已提交
3250

T
Takashi Iwai 已提交
3251 3252
	if (chip->azx_dev) {
		for (i = 0; i < chip->num_streams; i++)
T
Takashi Iwai 已提交
3253 3254
			if (chip->azx_dev[i].bdl.area) {
				mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
T
Takashi Iwai 已提交
3255
				snd_dma_free_pages(&chip->azx_dev[i].bdl);
T
Takashi Iwai 已提交
3256
			}
T
Takashi Iwai 已提交
3257
	}
T
Takashi Iwai 已提交
3258 3259
	if (chip->rb.area) {
		mark_pages_wc(chip, &chip->rb, false);
L
Linus Torvalds 已提交
3260
		snd_dma_free_pages(&chip->rb);
T
Takashi Iwai 已提交
3261 3262 3263
	}
	if (chip->posbuf.area) {
		mark_pages_wc(chip, &chip->posbuf, false);
L
Linus Torvalds 已提交
3264
		snd_dma_free_pages(&chip->posbuf);
T
Takashi Iwai 已提交
3265
	}
3266 3267
	if (chip->region_requested)
		pci_release_regions(chip->pci);
L
Linus Torvalds 已提交
3268
	pci_disable_device(chip->pci);
3269
	kfree(chip->azx_dev);
3270 3271 3272 3273
#ifdef CONFIG_SND_HDA_PATCH_LOADER
	if (chip->fw)
		release_firmware(chip->fw);
#endif
3274 3275 3276 3277
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
		hda_display_power(false);
		hda_i915_exit();
	}
L
Linus Torvalds 已提交
3278 3279 3280 3281 3282
	kfree(chip);

	return 0;
}

3283
static int azx_dev_free(struct snd_device *device)
L
Linus Torvalds 已提交
3284 3285 3286 3287
{
	return azx_free(device->device_data);
}

3288
#ifdef SUPPORT_VGA_SWITCHEROO
3289 3290 3291
/*
 * Check of disabled HDMI controller by vga-switcheroo
 */
3292
static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314
{
	struct pci_dev *p;

	/* check only discrete GPU */
	switch (pci->vendor) {
	case PCI_VENDOR_ID_ATI:
	case PCI_VENDOR_ID_AMD:
	case PCI_VENDOR_ID_NVIDIA:
		if (pci->devfn == 1) {
			p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
							pci->bus->number, 0);
			if (p) {
				if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
					return p;
				pci_dev_put(p);
			}
		}
		break;
	}
	return NULL;
}

3315
static bool check_hdmi_disabled(struct pci_dev *pci)
3316 3317 3318 3319 3320
{
	bool vga_inactive = false;
	struct pci_dev *p = get_bound_vga(pci);

	if (p) {
3321
		if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3322 3323 3324 3325 3326
			vga_inactive = true;
		pci_dev_put(p);
	}
	return vga_inactive;
}
3327
#endif /* SUPPORT_VGA_SWITCHEROO */
3328

3329 3330 3331
/*
 * white/black-listing for position_fix
 */
3332
static struct snd_pci_quirk position_fix_list[] = {
T
Takashi Iwai 已提交
3333 3334
	SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
	SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3335
	SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
T
Takashi Iwai 已提交
3336
	SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3337
	SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
D
Daniel T Chen 已提交
3338
	SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3339
	SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3340
	SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3341
	SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3342
	SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3343
	SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3344
	SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3345
	SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3346
	SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3347 3348 3349
	{}
};

3350
static int check_position_fix(struct azx *chip, int fix)
3351 3352 3353
{
	const struct snd_pci_quirk *q;

3354
	switch (fix) {
3355
	case POS_FIX_AUTO:
3356 3357
	case POS_FIX_LPIB:
	case POS_FIX_POSBUF:
3358
	case POS_FIX_VIACOMBO:
3359
	case POS_FIX_COMBO:
3360 3361 3362 3363 3364 3365 3366 3367 3368 3369
		return fix;
	}

	q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
	if (q) {
		printk(KERN_INFO
		       "hda_intel: position_fix set to %d "
		       "for device %04x:%04x\n",
		       q->value, q->subvendor, q->subdevice);
		return q->value;
3370
	}
3371 3372

	/* Check VIA/ATI HD Audio Controller exist */
3373
	if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3374
		snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3375
		return POS_FIX_VIACOMBO;
3376 3377
	}
	if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3378
		snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3379
		return POS_FIX_LPIB;
3380
	}
3381
	return POS_FIX_AUTO;
3382 3383
}

3384 3385 3386
/*
 * black-lists for probe_mask
 */
3387
static struct snd_pci_quirk probe_mask_list[] = {
3388 3389 3390 3391 3392 3393
	/* Thinkpad often breaks the controller communication when accessing
	 * to the non-working (or non-existing) modem codec slot.
	 */
	SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3394 3395
	/* broken BIOS */
	SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3396 3397
	/* including bogus ALC268 in slot#2 that conflicts with ALC888 */
	SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3398
	/* forced codec slots */
3399
	SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3400
	SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3401 3402
	/* WinFast VP200 H (Teradici) user reported broken communication */
	SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3403 3404 3405
	{}
};

3406 3407
#define AZX_FORCE_CODEC_MASK	0x100

3408
static void check_probe_mask(struct azx *chip, int dev)
3409 3410 3411
{
	const struct snd_pci_quirk *q;

3412 3413
	chip->codec_probe_mask = probe_mask[dev];
	if (chip->codec_probe_mask == -1) {
3414 3415 3416 3417 3418 3419
		q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
		if (q) {
			printk(KERN_INFO
			       "hda_intel: probe_mask set to 0x%x "
			       "for device %04x:%04x\n",
			       q->value, q->subvendor, q->subdevice);
3420
			chip->codec_probe_mask = q->value;
3421 3422
		}
	}
3423 3424 3425 3426 3427 3428 3429 3430

	/* check forced option */
	if (chip->codec_probe_mask != -1 &&
	    (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
		chip->codec_mask = chip->codec_probe_mask & 0xff;
		printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
		       chip->codec_mask);
	}
3431 3432
}

3433
/*
T
Takashi Iwai 已提交
3434
 * white/black-list for enable_msi
3435
 */
3436
static struct snd_pci_quirk msi_black_list[] = {
T
Takashi Iwai 已提交
3437
	SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3438
	SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3439
	SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3440
	SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3441
	SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3442
	SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3443 3444 3445
	{}
};

3446
static void check_msi(struct azx *chip)
3447 3448 3449
{
	const struct snd_pci_quirk *q;

T
Takashi Iwai 已提交
3450 3451
	if (enable_msi >= 0) {
		chip->msi = !!enable_msi;
3452
		return;
T
Takashi Iwai 已提交
3453 3454 3455
	}
	chip->msi = 1;	/* enable MSI as default */
	q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3456 3457 3458 3459 3460
	if (q) {
		printk(KERN_INFO
		       "hda_intel: msi for device %04x:%04x set to %d\n",
		       q->subvendor, q->subdevice, q->value);
		chip->msi = q->value;
3461 3462 3463 3464
		return;
	}

	/* NVidia chipsets seem to cause troubles with MSI */
3465 3466
	if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
		printk(KERN_INFO "hda_intel: Disabling MSI\n");
3467
		chip->msi = 0;
3468 3469 3470
	}
}

3471
/* check the snoop mode availability */
3472
static void azx_check_snoop_available(struct azx *chip)
3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491
{
	bool snoop = chip->snoop;

	switch (chip->driver_type) {
	case AZX_DRIVER_VIA:
		/* force to non-snoop mode for a new VIA controller
		 * when BIOS is set
		 */
		if (snoop) {
			u8 val;
			pci_read_config_byte(chip->pci, 0x42, &val);
			if (!(val & 0x80) && chip->pci->revision == 0x30)
				snoop = false;
		}
		break;
	case AZX_DRIVER_ATIHDMI_NS:
		/* new ATI HDMI requires non-snoop */
		snoop = false;
		break;
3492 3493 3494
	case AZX_DRIVER_CTHDA:
		snoop = false;
		break;
3495 3496 3497
	}

	if (snoop != chip->snoop) {
3498 3499
		snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
			   pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3500 3501 3502
		chip->snoop = snoop;
	}
}
3503

3504 3505 3506 3507 3508 3509 3510
#ifdef CONFIG_SND_HDA_I915
static void azx_probe_work(struct work_struct *work)
{
	azx_probe_continue(container_of(work, struct azx, probe_work));
}
#endif

L
Linus Torvalds 已提交
3511 3512 3513
/*
 * constructor
 */
3514 3515 3516
static int azx_create(struct snd_card *card, struct pci_dev *pci,
		      int dev, unsigned int driver_caps,
		      struct azx **rchip)
L
Linus Torvalds 已提交
3517
{
3518
	static struct snd_device_ops ops = {
L
Linus Torvalds 已提交
3519 3520
		.dev_free = azx_dev_free,
	};
3521 3522
	struct azx *chip;
	int err;
L
Linus Torvalds 已提交
3523 3524

	*rchip = NULL;
3525

3526 3527
	err = pci_enable_device(pci);
	if (err < 0)
L
Linus Torvalds 已提交
3528 3529
		return err;

3530
	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3531
	if (!chip) {
3532
		snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
L
Linus Torvalds 已提交
3533 3534 3535 3536 3537
		pci_disable_device(pci);
		return -ENOMEM;
	}

	spin_lock_init(&chip->reg_lock);
3538
	mutex_init(&chip->open_mutex);
L
Linus Torvalds 已提交
3539 3540 3541
	chip->card = card;
	chip->pci = pci;
	chip->irq = -1;
3542 3543
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
3544
	check_msi(chip);
3545
	chip->dev_index = dev;
3546
	INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3547
	INIT_LIST_HEAD(&chip->pcm_list);
3548
	INIT_LIST_HEAD(&chip->list);
3549
	init_vga_switcheroo(chip);
3550
	init_completion(&chip->probe_wait);
L
Linus Torvalds 已提交
3551

3552 3553
	chip->position_fix[0] = chip->position_fix[1] =
		check_position_fix(chip, position_fix[dev]);
3554 3555 3556 3557 3558 3559
	/* combo mode uses LPIB for playback */
	if (chip->position_fix[0] == POS_FIX_COMBO) {
		chip->position_fix[0] = POS_FIX_LPIB;
		chip->position_fix[1] = POS_FIX_AUTO;
	}

3560
	check_probe_mask(chip, dev);
3561

3562
	chip->single_cmd = single_cmd;
T
Takashi Iwai 已提交
3563
	chip->snoop = hda_snoop;
3564
	azx_check_snoop_available(chip);
3565

3566 3567
	if (bdl_pos_adj[dev] < 0) {
		switch (chip->driver_type) {
3568
		case AZX_DRIVER_ICH:
3569
		case AZX_DRIVER_PCH:
3570
			bdl_pos_adj[dev] = 1;
3571 3572
			break;
		default:
3573
			bdl_pos_adj[dev] = 32;
3574 3575 3576 3577
			break;
		}
	}

3578 3579
	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err < 0) {
3580 3581
		snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
		   pci_name(chip->pci));
3582 3583 3584 3585
		azx_free(chip);
		return err;
	}

3586 3587 3588 3589 3590
#ifdef CONFIG_SND_HDA_I915
	/* continue probing in work context as may trigger request module */
	INIT_WORK(&chip->probe_work, azx_probe_work);
#endif

3591
	*rchip = chip;
3592

3593 3594 3595
	return 0;
}

3596
static int azx_first_init(struct azx *chip)
3597 3598 3599 3600 3601 3602 3603
{
	int dev = chip->dev_index;
	struct pci_dev *pci = chip->pci;
	struct snd_card *card = chip->card;
	int i, err;
	unsigned short gcap;

3604 3605 3606 3607 3608 3609 3610 3611 3612 3613
#if BITS_PER_LONG != 64
	/* Fix up base address on ULI M5461 */
	if (chip->driver_type == AZX_DRIVER_ULI) {
		u16 tmp3;
		pci_read_config_word(pci, 0x40, &tmp3);
		pci_write_config_word(pci, 0x40, tmp3 | 0x10);
		pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
	}
#endif

3614
	err = pci_request_regions(pci, "ICH HD audio");
3615
	if (err < 0)
L
Linus Torvalds 已提交
3616
		return err;
3617
	chip->region_requested = 1;
L
Linus Torvalds 已提交
3618

3619
	chip->addr = pci_resource_start(pci, 0);
3620
	chip->remap_addr = pci_ioremap_bar(pci, 0);
L
Linus Torvalds 已提交
3621
	if (chip->remap_addr == NULL) {
3622
		snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3623
		return -ENXIO;
L
Linus Torvalds 已提交
3624 3625
	}

3626 3627 3628
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
3629

3630 3631
	if (azx_acquire_irq(chip, 0) < 0)
		return -EBUSY;
L
Linus Torvalds 已提交
3632 3633 3634 3635

	pci_set_master(pci);
	synchronize_irq(chip->irq);

3636
	gcap = azx_readw(chip, GCAP);
3637
	snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3638

3639
	/* disable SB600 64bit support for safety */
3640
	if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3641 3642 3643 3644 3645 3646 3647 3648 3649 3650
		struct pci_dev *p_smbus;
		p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
					 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
					 NULL);
		if (p_smbus) {
			if (p_smbus->revision < 0x30)
				gcap &= ~ICH6_GCAP_64OK;
			pci_dev_put(p_smbus);
		}
	}
3651

3652 3653
	/* disable 64bit DMA address on some devices */
	if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3654
		snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3655
		gcap &= ~ICH6_GCAP_64OK;
3656
	}
3657

3658
	/* disable buffer size rounding to 128-byte multiples if supported */
3659 3660 3661 3662 3663 3664 3665 3666 3667 3668
	if (align_buffer_size >= 0)
		chip->align_buffer_size = !!align_buffer_size;
	else {
		if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
			chip->align_buffer_size = 0;
		else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
			chip->align_buffer_size = 1;
		else
			chip->align_buffer_size = 1;
	}
3669

3670
	/* allow 64bit DMA address if supported by H/W */
3671
	if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3672
		pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3673
	else {
3674 3675
		pci_set_dma_mask(pci, DMA_BIT_MASK(32));
		pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3676
	}
3677

3678 3679 3680 3681 3682 3683
	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
3684 3685 3686 3687 3688 3689 3690 3691
		/* gcap didn't give any info, switching to old method */

		switch (chip->driver_type) {
		case AZX_DRIVER_ULI:
			chip->playback_streams = ULI_NUM_PLAYBACK;
			chip->capture_streams = ULI_NUM_CAPTURE;
			break;
		case AZX_DRIVER_ATIHDMI:
3692
		case AZX_DRIVER_ATIHDMI_NS:
3693 3694 3695
			chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
			chip->capture_streams = ATIHDMI_NUM_CAPTURE;
			break;
3696
		case AZX_DRIVER_GENERIC:
3697 3698 3699 3700 3701
		default:
			chip->playback_streams = ICH6_NUM_PLAYBACK;
			chip->capture_streams = ICH6_NUM_CAPTURE;
			break;
		}
3702
	}
3703 3704
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
3705
	chip->num_streams = chip->playback_streams + chip->capture_streams;
3706 3707
	chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
				GFP_KERNEL);
3708
	if (!chip->azx_dev) {
3709
		snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3710
		return -ENOMEM;
3711 3712
	}

T
Takashi Iwai 已提交
3713
	for (i = 0; i < chip->num_streams; i++) {
3714
		dsp_lock_init(&chip->azx_dev[i]);
T
Takashi Iwai 已提交
3715 3716 3717 3718 3719
		/* allocate memory for the BDL for each stream */
		err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
					  snd_dma_pci_data(chip->pci),
					  BDL_SIZE, &chip->azx_dev[i].bdl);
		if (err < 0) {
3720
			snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3721
			return -ENOMEM;
T
Takashi Iwai 已提交
3722
		}
T
Takashi Iwai 已提交
3723
		mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
L
Linus Torvalds 已提交
3724
	}
3725
	/* allocate memory for the position buffer */
3726 3727 3728 3729
	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
				  chip->num_streams * 8, &chip->posbuf);
	if (err < 0) {
3730
		snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3731
		return -ENOMEM;
L
Linus Torvalds 已提交
3732
	}
T
Takashi Iwai 已提交
3733
	mark_pages_wc(chip, &chip->posbuf, true);
L
Linus Torvalds 已提交
3734
	/* allocate CORB/RIRB */
3735 3736
	err = azx_alloc_cmd_io(chip);
	if (err < 0)
3737
		return err;
L
Linus Torvalds 已提交
3738 3739 3740 3741 3742

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
3743
	azx_init_pci(chip);
3744
	azx_init_chip(chip, (probe_only[dev] & 2) == 0);
L
Linus Torvalds 已提交
3745 3746

	/* codec detection */
3747
	if (!chip->codec_mask) {
3748
		snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3749
		return -ENODEV;
L
Linus Torvalds 已提交
3750 3751
	}

3752
	strcpy(card->driver, "HDA-Intel");
T
Takashi Iwai 已提交
3753 3754 3755 3756 3757
	strlcpy(card->shortname, driver_short_names[chip->driver_type],
		sizeof(card->shortname));
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, chip->addr, chip->irq);
3758

L
Linus Torvalds 已提交
3759 3760 3761
	return 0;
}

3762 3763
static void power_down_all_codecs(struct azx *chip)
{
3764
#ifdef CONFIG_PM
3765 3766 3767 3768 3769 3770 3771 3772 3773 3774
	/* The codecs were powered up in snd_hda_codec_new().
	 * Now all initialization done, so turn them down if possible
	 */
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list) {
		snd_hda_power_down(codec);
	}
#endif
}

3775
#ifdef CONFIG_SND_HDA_PATCH_LOADER
3776 3777 3778 3779 3780 3781 3782 3783
/* callback from request_firmware_nowait() */
static void azx_firmware_cb(const struct firmware *fw, void *context)
{
	struct snd_card *card = context;
	struct azx *chip = card->private_data;
	struct pci_dev *pci = chip->pci;

	if (!fw) {
3784 3785
		snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
			   pci_name(chip->pci));
3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800
		goto error;
	}

	chip->fw = fw;
	if (!chip->disabled) {
		/* continue probing */
		if (azx_probe_continue(chip))
			goto error;
	}
	return; /* OK */

 error:
	snd_card_free(card);
	pci_set_drvdata(pci, NULL);
}
3801
#endif
3802

3803 3804
static int azx_probe(struct pci_dev *pci,
		     const struct pci_device_id *pci_id)
L
Linus Torvalds 已提交
3805
{
3806
	static int dev;
3807 3808
	struct snd_card *card;
	struct azx *chip;
3809
	bool probe_now;
3810
	int err;
L
Linus Torvalds 已提交
3811

3812 3813 3814 3815 3816 3817 3818
	if (dev >= SNDRV_CARDS)
		return -ENODEV;
	if (!enable[dev]) {
		dev++;
		return -ENOENT;
	}

3819 3820
	err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
	if (err < 0) {
3821
		snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3822
		return err;
L
Linus Torvalds 已提交
3823 3824
	}

3825 3826
	snd_card_set_dev(card, &pci->dev);

3827
	err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
W
Wu Fengguang 已提交
3828 3829
	if (err < 0)
		goto out_free;
T
Takashi Iwai 已提交
3830
	card->private_data = chip;
3831 3832 3833 3834 3835 3836

	pci_set_drvdata(pci, card);

	err = register_vga_switcheroo(chip);
	if (err < 0) {
		snd_printk(KERN_ERR SFX
3837
			   "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3838 3839 3840 3841
		goto out_free;
	}

	if (check_hdmi_disabled(pci)) {
3842
		snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3843
			   pci_name(pci));
3844
		snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3845 3846 3847
		chip->disabled = true;
	}

3848
	probe_now = !chip->disabled;
L
Linus Torvalds 已提交
3849

3850 3851
#ifdef CONFIG_SND_HDA_PATCH_LOADER
	if (patch[dev] && *patch[dev]) {
3852 3853
		snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
			   pci_name(pci), patch[dev]);
3854 3855 3856
		err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
					      &pci->dev, GFP_KERNEL, card,
					      azx_firmware_cb);
3857 3858
		if (err < 0)
			goto out_free;
3859
		probe_now = false; /* continued in azx_firmware_cb() */
3860 3861 3862
	}
#endif /* CONFIG_SND_HDA_PATCH_LOADER */

3863 3864 3865 3866 3867 3868 3869 3870 3871 3872
	/* continue probing in work context, avoid request_module deadlock */
	if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
#ifdef CONFIG_SND_HDA_I915
		probe_now = false;
		schedule_work(&chip->probe_work);
#else
		snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
#endif
	}

3873
	if (probe_now) {
3874 3875 3876 3877 3878 3879
		err = azx_probe_continue(chip);
		if (err < 0)
			goto out_free;
	}

	dev++;
3880
	complete_all(&chip->probe_wait);
3881 3882 3883 3884 3885 3886 3887
	return 0;

out_free:
	snd_card_free(card);
	return err;
}

3888
static int azx_probe_continue(struct azx *chip)
3889
{
W
Wang Xingchao 已提交
3890
	struct pci_dev *pci = chip->pci;
3891 3892 3893
	int dev = chip->dev_index;
	int err;

3894 3895
	/* Request power well for Haswell HDA controller and codec */
	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3896
#ifdef CONFIG_SND_HDA_I915
3897 3898 3899 3900 3901
		err = hda_i915_init();
		if (err < 0) {
			snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
			goto out_free;
		}
3902
#endif
3903 3904 3905
		hda_display_power(true);
	}

3906 3907 3908 3909
	err = azx_first_init(chip);
	if (err < 0)
		goto out_free;

3910 3911 3912 3913
#ifdef CONFIG_SND_HDA_INPUT_BEEP
	chip->beep_mode = beep_mode[dev];
#endif

L
Linus Torvalds 已提交
3914
	/* create codec instances */
3915
	err = azx_codec_create(chip, model[dev]);
W
Wu Fengguang 已提交
3916 3917
	if (err < 0)
		goto out_free;
3918
#ifdef CONFIG_SND_HDA_PATCH_LOADER
3919 3920 3921
	if (chip->fw) {
		err = snd_hda_load_patch(chip->bus, chip->fw->size,
					 chip->fw->data);
3922 3923
		if (err < 0)
			goto out_free;
3924
#ifndef CONFIG_PM
3925 3926
		release_firmware(chip->fw); /* no longer needed */
		chip->fw = NULL;
3927
#endif
3928 3929
	}
#endif
3930
	if ((probe_only[dev] & 1) == 0) {
3931 3932 3933 3934
		err = azx_codec_configure(chip);
		if (err < 0)
			goto out_free;
	}
L
Linus Torvalds 已提交
3935 3936

	/* create PCM streams */
3937
	err = snd_hda_build_pcms(chip->bus);
W
Wu Fengguang 已提交
3938 3939
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
3940 3941

	/* create mixer controls */
3942
	err = azx_mixer_create(chip);
W
Wu Fengguang 已提交
3943 3944
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
3945

3946
	err = snd_card_register(chip->card);
W
Wu Fengguang 已提交
3947 3948
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
3949

3950 3951
	chip->running = 1;
	power_down_all_codecs(chip);
T
Takashi Iwai 已提交
3952
	azx_notifier_register(chip);
3953
	azx_add_card_list(chip);
3954
	if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
W
Wang Xingchao 已提交
3955
		pm_runtime_put_noidle(&pci->dev);
L
Linus Torvalds 已提交
3956

3957 3958
	return 0;

W
Wu Fengguang 已提交
3959
out_free:
3960
	chip->init_failed = 1;
W
Wu Fengguang 已提交
3961
	return err;
L
Linus Torvalds 已提交
3962 3963
}

3964
static void azx_remove(struct pci_dev *pci)
L
Linus Torvalds 已提交
3965
{
3966
	struct snd_card *card = pci_get_drvdata(pci);
3967

3968 3969
	if (card)
		snd_card_free(card);
L
Linus Torvalds 已提交
3970 3971 3972
}

/* PCI IDs */
3973
static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3974
	/* CPT */
3975
	{ PCI_DEVICE(0x8086, 0x1c20),
3976
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3977
	/* PBG */
3978
	{ PCI_DEVICE(0x8086, 0x1d20),
3979
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3980
	/* Panther Point */
3981
	{ PCI_DEVICE(0x8086, 0x1e20),
3982
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3983 3984
	/* Lynx Point */
	{ PCI_DEVICE(0x8086, 0x8c20),
3985
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3986 3987 3988 3989 3990
	/* Wellsburg */
	{ PCI_DEVICE(0x8086, 0x8d20),
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
	{ PCI_DEVICE(0x8086, 0x8d21),
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3991 3992
	/* Lynx Point-LP */
	{ PCI_DEVICE(0x8086, 0x9c20),
3993
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3994 3995
	/* Lynx Point-LP */
	{ PCI_DEVICE(0x8086, 0x9c21),
3996
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3997 3998 3999
	/* Wildcat Point-LP */
	{ PCI_DEVICE(0x8086, 0x9ca0),
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4000
	/* Haswell */
4001
	{ PCI_DEVICE(0x8086, 0x0a0c),
4002
	  .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
4003
	{ PCI_DEVICE(0x8086, 0x0c0c),
4004
	  .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
4005
	{ PCI_DEVICE(0x8086, 0x0d0c),
4006
	  .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
4007 4008
	/* 5 Series/3400 */
	{ PCI_DEVICE(0x8086, 0x3b56),
4009
	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4010
	/* Poulsbo */
4011
	{ PCI_DEVICE(0x8086, 0x811b),
4012 4013
	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
	/* Oaktrail */
4014
	{ PCI_DEVICE(0x8086, 0x080a),
4015
	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4016 4017 4018
	/* BayTrail */
	{ PCI_DEVICE(0x8086, 0x0f04),
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4019
	/* ICH */
4020
	{ PCI_DEVICE(0x8086, 0x2668),
4021 4022
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH6 */
4023
	{ PCI_DEVICE(0x8086, 0x27d8),
4024 4025
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH7 */
4026
	{ PCI_DEVICE(0x8086, 0x269a),
4027 4028
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ESB2 */
4029
	{ PCI_DEVICE(0x8086, 0x284b),
4030 4031
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH8 */
4032
	{ PCI_DEVICE(0x8086, 0x293e),
4033 4034
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH9 */
4035
	{ PCI_DEVICE(0x8086, 0x293f),
4036 4037
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH9 */
4038
	{ PCI_DEVICE(0x8086, 0x3a3e),
4039 4040
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH10 */
4041
	{ PCI_DEVICE(0x8086, 0x3a6e),
4042 4043
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH10 */
4044 4045 4046 4047
	/* Generic Intel */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
4048
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4049 4050 4051 4052 4053 4054 4055 4056
	/* ATI SB 450/600/700/800/900 */
	{ PCI_DEVICE(0x1002, 0x437b),
	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
	{ PCI_DEVICE(0x1002, 0x4383),
	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
	/* AMD Hudson */
	{ PCI_DEVICE(0x1022, 0x780d),
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4057
	/* ATI HDMI */
4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085
	{ PCI_DEVICE(0x1002, 0x793b),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x7919),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x960f),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x970f),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa00),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa08),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa10),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa18),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa20),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa28),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa30),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa38),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa40),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa48),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101
	{ PCI_DEVICE(0x1002, 0xaa50),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa58),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa60),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa68),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa80),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa88),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa90),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa98),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4102 4103 4104 4105 4106 4107 4108 4109
	{ PCI_DEVICE(0x1002, 0x9902),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaaa0),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaaa8),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaab0),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4110
	/* VIA VT8251/VT8237A */
4111 4112
	{ PCI_DEVICE(0x1106, 0x3288),
	  .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4113 4114 4115 4116
	/* VIA GFX VT7122/VX900 */
	{ PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
	/* VIA GFX VT6122/VX11 */
	{ PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4117 4118 4119 4120 4121
	/* SIS966 */
	{ PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
	/* ULI M5461 */
	{ PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
	/* NVIDIA MCP */
4122 4123 4124
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
4125
	  .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4126
	/* Teradici */
4127 4128
	{ PCI_DEVICE(0x6549, 0x1200),
	  .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4129 4130
	{ PCI_DEVICE(0x6549, 0x2200),
	  .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4131
	/* Creative X-Fi (CA0110-IBG) */
4132 4133 4134 4135 4136
	/* CTHDA chips */
	{ PCI_DEVICE(0x1102, 0x0010),
	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
	{ PCI_DEVICE(0x1102, 0x0012),
	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4137 4138 4139 4140 4141
#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
	/* the following entry conflicts with snd-ctxfi driver,
	 * as ctxfi driver mutates from HD-audio to native mode with
	 * a special command sequence.
	 */
4142 4143 4144
	{ PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
4145
	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4146
	  AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4147 4148
#else
	/* this entry seems still valid -- i.e. without emu20kx chip */
4149 4150
	{ PCI_DEVICE(0x1102, 0x0009),
	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4151
	  AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4152
#endif
4153 4154
	/* Vortex86MX */
	{ PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4155 4156
	/* VMware HDAudio */
	{ PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4157
	/* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4158 4159 4160
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
4161
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4162 4163 4164
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
4165
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
L
Linus Torvalds 已提交
4166 4167 4168 4169 4170
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, azx_ids);

/* pci_driver definition */
4171
static struct pci_driver azx_driver = {
4172
	.name = KBUILD_MODNAME,
L
Linus Torvalds 已提交
4173 4174
	.id_table = azx_ids,
	.probe = azx_probe,
4175
	.remove = azx_remove,
4176 4177 4178
	.driver = {
		.pm = AZX_PM_OPS,
	},
L
Linus Torvalds 已提交
4179 4180
};

4181
module_pci_driver(azx_driver);