intel_dp.c 67.9 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "drm_dp_helper.h"
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#define DP_RECEIVER_CAP_SIZE	0xf
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#define DP_LINK_STATUS_SIZE	6
#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

#define DP_LINK_CONFIGURATION_SIZE	9

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struct intel_dp {
	struct intel_encoder base;
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	uint32_t output_reg;
	uint32_t DP;
	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
	bool has_audio;
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	enum hdmi_force_audio force_audio;
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	uint32_t color_range;
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	int dpms_mode;
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	uint8_t link_bw;
	uint8_t lane_count;
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	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
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	struct i2c_adapter adapter;
	struct i2c_algo_dp_aux_data algo;
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	bool is_pch_edp;
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	uint8_t	train_set[4];
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	int panel_power_up_delay;
	int panel_power_down_delay;
	int panel_power_cycle_delay;
	int backlight_on_delay;
	int backlight_off_delay;
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	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
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	struct delayed_work panel_vdd_work;
	bool want_panel_vdd;
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};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
	return intel_dp->base.type == INTEL_OUTPUT_EDP;
}

/**
 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a PCH DP port attached
 * to an eDP panel, false otherwise.  Helpful for determining whether we
 * may need FDI resources for a given DP output or not.
 */
static bool is_pch_edp(struct intel_dp *intel_dp)
{
	return intel_dp->is_pch_edp;
}

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/**
 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a CPU eDP port.
 */
static bool is_cpu_edp(struct intel_dp *intel_dp)
{
	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
}

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static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
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	return container_of(encoder, struct intel_dp, base.base);
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}
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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_dp, base);
}

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/**
 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 * @encoder: DRM encoder
 *
 * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 * by intel_display.c.
 */
bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp;

	if (!encoder)
		return false;

	intel_dp = enc_to_intel_dp(encoder);

	return is_pch_edp(intel_dp);
}

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static void intel_dp_start_link_train(struct intel_dp *intel_dp);
static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
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static void intel_dp_link_down(struct intel_dp *intel_dp);
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void
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intel_edp_link_config(struct intel_encoder *intel_encoder,
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		       int *lane_num, int *link_bw)
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{
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	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
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	*lane_num = intel_dp->lane_count;
	if (intel_dp->link_bw == DP_LINK_BW_1_62)
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		*link_bw = 162000;
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	else if (intel_dp->link_bw == DP_LINK_BW_2_7)
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		*link_bw = 270000;
}

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static int
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intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
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	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
	switch (max_lane_count) {
	case 1: case 2: case 4:
		break;
	default:
		max_lane_count = 4;
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	}
	return max_lane_count;
}

static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

static int
intel_dp_link_clock(uint8_t link_bw)
{
	if (link_bw == DP_LINK_BW_2_7)
		return 270000;
	else
		return 162000;
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
	int max_lanes = intel_dp_max_lane_count(intel_dp);
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	int max_rate, mode_rate;
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	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
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			return MODE_PANEL;
	}

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	mode_rate = intel_dp_link_required(mode->clock, 24);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);

	if (mode_rate > max_rate) {
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			mode_rate = intel_dp_link_required(mode->clock, 18);
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			if (mode_rate > max_rate)
				return MODE_CLOCK_HIGH;
			else
				mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
	}
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(PCH_PP_STATUS),
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			      I915_READ(PCH_PP_CONTROL));
	}
}

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static int
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intel_dp_aux_ch(struct intel_dp *intel_dp,
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		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
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	uint32_t output_reg = intel_dp->output_reg;
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	struct drm_device *dev = intel_dp->base.base.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = output_reg + 0x10;
	uint32_t ch_data = ch_ctl + 4;
	int i;
	int recv_bytes;
	uint32_t status;
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	uint32_t aux_clock_divider;
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	int try, precharge = 5;
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	intel_dp_check_edp(intel_dp);
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
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	 */
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	if (is_cpu_edp(intel_dp)) {
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		if (IS_GEN6(dev) || IS_GEN7(dev))
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
	} else if (HAS_PCH_SPLIT(dev))
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		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
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	else
		aux_clock_divider = intel_hrawclk(dev) / 2;

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
		status = I915_READ(ch_ctl);
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		return -EBUSY;
	}

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	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
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		for (i = 0; i < send_bytes; i += 4)
			I915_WRITE(ch_data + i,
				   pack_aux(send + i, send_bytes - i));
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		/* Send the command and wait for it to complete */
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		I915_WRITE(ch_ctl,
			   DP_AUX_CH_CTL_SEND_BUSY |
			   DP_AUX_CH_CTL_TIME_OUT_400us |
			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		for (;;) {
			status = I915_READ(ch_ctl);
			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
				break;
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			udelay(100);
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		}
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		/* Clear done status and any errors */
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		I915_WRITE(ch_ctl,
			   status |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
			continue;
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		return -EBUSY;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		return -EIO;
	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		return -ETIMEDOUT;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	return recv_bytes;
}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_dp *intel_dp,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

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	intel_dp_check_edp(intel_dp);
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	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
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				      reply, reply_bytes);
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		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
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			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
}

static int
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intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
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{
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	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
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	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
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	unsigned retry;
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	int msg_bytes;
	int reply_bytes;
	int ret;

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	intel_dp_check_edp(intel_dp);
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	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
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	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

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	for (retry = 0; retry < 5; retry++) {
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
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		if (ret < 0) {
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			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
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			return ret;
		}
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		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
			udelay(100);
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

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		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
622
			DRM_DEBUG_KMS("aux_i2c nack\n");
623 624
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
625
			DRM_DEBUG_KMS("aux_i2c defer\n");
626 627 628
			udelay(100);
			break;
		default:
629
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
630 631 632
			return -EREMOTEIO;
		}
	}
633 634 635

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
636 637
}

638
static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
639
static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
640

641
static int
C
Chris Wilson 已提交
642
intel_dp_i2c_init(struct intel_dp *intel_dp,
643
		  struct intel_connector *intel_connector, const char *name)
644
{
645 646
	int	ret;

Z
Zhenyu Wang 已提交
647
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
648 649 650 651
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

652
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
653 654
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
655
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
656 657 658 659
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

660 661
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
662
	ironlake_edp_panel_vdd_off(intel_dp, false);
663
	return ret;
664 665 666 667 668 669
}

static bool
intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
		    struct drm_display_mode *adjusted_mode)
{
670
	struct drm_device *dev = encoder->dev;
C
Chris Wilson 已提交
671
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
672
	int lane_count, clock;
C
Chris Wilson 已提交
673 674
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
675
	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
676 677
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

678 679
	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
		intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
680 681
		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
					mode, adjusted_mode);
682 683 684 685
		/*
		 * the mode->clock is used to calculate the Data&Link M/N
		 * of the pipe. For the eDP the fixed clock should be used.
		 */
686
		mode->clock = intel_dp->panel_fixed_mode->clock;
687 688
	}

689 690
	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
		for (clock = 0; clock <= max_clock; clock++) {
691
			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
692

693
			if (intel_dp_link_required(mode->clock, bpp)
694
					<= link_avail) {
C
Chris Wilson 已提交
695 696 697
				intel_dp->link_bw = bws[clock];
				intel_dp->lane_count = lane_count;
				adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
698 699
				DRM_DEBUG_KMS("Display port link bw %02x lane "
						"count %d clock %d\n",
C
Chris Wilson 已提交
700
				       intel_dp->link_bw, intel_dp->lane_count,
701 702 703 704 705
				       adjusted_mode->clock);
				return true;
			}
		}
	}
706

707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
	return false;
}

struct intel_dp_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

static void
intel_reduce_ratio(uint32_t *num, uint32_t *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
728
intel_dp_compute_m_n(int bpp,
729 730 731 732 733 734
		     int nlanes,
		     int pixel_clock,
		     int link_clock,
		     struct intel_dp_m_n *m_n)
{
	m_n->tu = 64;
735
	m_n->gmch_m = (pixel_clock * bpp) >> 3;
736 737 738 739 740 741 742 743 744 745 746 747 748
	m_n->gmch_n = link_clock * nlanes;
	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
}

void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
749
	struct drm_encoder *encoder;
750 751
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
752
	int lane_count = 4;
753
	struct intel_dp_m_n m_n;
754
	int pipe = intel_crtc->pipe;
755 756

	/*
757
	 * Find the lane count in the intel_encoder private
758
	 */
759
	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
C
Chris Wilson 已提交
760
		struct intel_dp *intel_dp;
761

762
		if (encoder->crtc != crtc)
763 764
			continue;

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Chris Wilson 已提交
765
		intel_dp = enc_to_intel_dp(encoder);
766 767 768
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
		{
C
Chris Wilson 已提交
769
			lane_count = intel_dp->lane_count;
770
			break;
771 772 773 774 775 776 777 778
		}
	}

	/*
	 * Compute the GMCH and Link ratios. The '3' here is
	 * the number of bytes_per_pixel post-LUT, which we always
	 * set up for 8-bits of R/G/B, or 3 bytes total.
	 */
779
	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
780 781
			     mode->clock, adjusted_mode->clock, &m_n);

782
	if (HAS_PCH_SPLIT(dev)) {
783 784 785 786 787 788
		I915_WRITE(TRANSDATA_M1(pipe),
			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
			   m_n.gmch_m);
		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
789
	} else {
790 791 792 793 794 795
		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
			   m_n.gmch_m);
		I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
796 797 798
	}
}

799 800 801
static void ironlake_edp_pll_on(struct drm_encoder *encoder);
static void ironlake_edp_pll_off(struct drm_encoder *encoder);

802 803 804 805
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
806
	struct drm_device *dev = encoder->dev;
807
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
808
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
809
	struct drm_crtc *crtc = intel_dp->base.base.crtc;
810 811
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

812 813 814 815 816 817 818 819
	/* Turn on the eDP PLL if needed */
	if (is_edp(intel_dp)) {
		if (!is_pch_edp(intel_dp))
			ironlake_edp_pll_on(encoder);
		else
			ironlake_edp_pll_off(encoder);
	}

820
	/*
K
Keith Packard 已提交
821
	 * There are four kinds of DP registers:
822 823
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
824 825
	 * 	SNB CPU
	 *	IVB CPU
826 827 828 829 830 831 832 833 834 835
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
836

837 838 839 840 841
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
842

843 844 845
	/* Handle DP bits in common between all three register formats */

	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
846

C
Chris Wilson 已提交
847
	switch (intel_dp->lane_count) {
848
	case 1:
C
Chris Wilson 已提交
849
		intel_dp->DP |= DP_PORT_WIDTH_1;
850 851
		break;
	case 2:
C
Chris Wilson 已提交
852
		intel_dp->DP |= DP_PORT_WIDTH_2;
853 854
		break;
	case 4:
C
Chris Wilson 已提交
855
		intel_dp->DP |= DP_PORT_WIDTH_4;
856 857
		break;
	}
858 859 860
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
C
Chris Wilson 已提交
861
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
862 863
		intel_write_eld(encoder, adjusted_mode);
	}
C
Chris Wilson 已提交
864 865 866
	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	intel_dp->link_configuration[0] = intel_dp->link_bw;
	intel_dp->link_configuration[1] = intel_dp->lane_count;
867
	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
868
	/*
869
	 * Check for DPCD version > 1.1 and enhanced framing support
870
	 */
871 872
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
C
Chris Wilson 已提交
873
		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
874 875
	}

876
	/* Split out the IBX/CPU vs CPT settings */
877

K
Keith Packard 已提交
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		intel_dp->DP |= intel_crtc->pipe << 29;

		/* don't miss out required setting for eDP */
		intel_dp->DP |= DP_PLL_ENABLE;
		if (adjusted_mode->clock < 200000)
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
		else
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920
		intel_dp->DP |= intel_dp->color_range;

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		if (intel_crtc->pipe == 1)
			intel_dp->DP |= DP_PIPEB_SELECT;

		if (is_cpu_edp(intel_dp)) {
			/* don't miss out required setting for eDP */
			intel_dp->DP |= DP_PLL_ENABLE;
			if (adjusted_mode->clock < 200000)
				intel_dp->DP |= DP_PLL_FREQ_160MHZ;
			else
				intel_dp->DP |= DP_PLL_FREQ_270MHZ;
		}
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
921
	}
922 923
}

924 925 926 927 928 929 930 931 932 933 934 935
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
936
{
937 938
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
939

940 941 942 943
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		      mask, value,
		      I915_READ(PCH_PP_STATUS),
		      I915_READ(PCH_PP_CONTROL));
944

945 946 947 948
	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
			  I915_READ(PCH_PP_STATUS),
			  I915_READ(PCH_PP_CONTROL));
949
	}
950
}
951

952 953 954 955
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
956 957
}

958 959 960 961 962 963 964 965 966 967 968 969 970
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


971 972 973 974 975 976 977 978 979 980 981
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
{
	u32	control = I915_READ(PCH_PP_CONTROL);

	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
982 983
}

984 985 986 987 988 989
static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

990 991
	if (!is_edp(intel_dp))
		return;
992
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
993

994 995 996 997
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
998

999 1000 1001 1002 1003
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1004 1005 1006
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1007
	pp = ironlake_get_pp_control(dev_priv);
1008 1009 1010
	pp |= EDP_FORCE_VDD;
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1011 1012
	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1013 1014 1015 1016 1017

	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1018
		DRM_DEBUG_KMS("eDP was not running\n");
1019 1020
		msleep(intel_dp->panel_power_up_delay);
	}
1021 1022
}

1023
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1024 1025 1026 1027 1028
{
	struct drm_device *dev = intel_dp->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1029
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1030
		pp = ironlake_get_pp_control(dev_priv);
1031 1032 1033 1034 1035 1036 1037
		pp &= ~EDP_FORCE_VDD;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);

		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1038 1039

		msleep(intel_dp->panel_power_down_delay);
1040 1041
	}
}
1042

1043 1044 1045 1046 1047 1048
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
	struct drm_device *dev = intel_dp->base.base.dev;

1049
	mutex_lock(&dev->mode_config.mutex);
1050
	ironlake_panel_vdd_off_sync(intel_dp);
1051
	mutex_unlock(&dev->mode_config.mutex);
1052 1053 1054 1055
}

static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
1056 1057
	if (!is_edp(intel_dp))
		return;
1058

1059 1060
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1061

1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1075 1076
}

1077
static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1078
{
1079
	struct drm_device *dev = intel_dp->base.base.dev;
1080
	struct drm_i915_private *dev_priv = dev->dev_private;
1081
	u32 pp;
1082

1083
	if (!is_edp(intel_dp))
1084
		return;
1085 1086 1087 1088 1089

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1090
		return;
1091
	}
1092

1093
	ironlake_wait_panel_power_cycle(intel_dp);
1094

1095
	pp = ironlake_get_pp_control(dev_priv);
1096 1097 1098 1099 1100 1101
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1102

1103
	pp |= POWER_TARGET_ON;
1104 1105 1106
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1107
	I915_WRITE(PCH_PP_CONTROL, pp);
1108
	POSTING_READ(PCH_PP_CONTROL);
1109

1110
	ironlake_wait_panel_on(intel_dp);
1111

1112 1113 1114 1115 1116
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1117 1118
}

1119
static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1120
{
1121
	struct drm_device *dev = intel_dp->base.base.dev;
1122
	struct drm_i915_private *dev_priv = dev->dev_private;
1123
	u32 pp;
1124

1125 1126
	if (!is_edp(intel_dp))
		return;
1127

1128
	DRM_DEBUG_KMS("Turn eDP power off\n");
1129

1130
	WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1131

1132 1133 1134 1135
	pp = ironlake_get_pp_control(dev_priv);
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1136

1137
	ironlake_wait_panel_off(intel_dp);
1138 1139
}

1140
static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1141
{
1142
	struct drm_device *dev = intel_dp->base.base.dev;
1143 1144 1145
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1146 1147 1148
	if (!is_edp(intel_dp))
		return;

1149
	DRM_DEBUG_KMS("\n");
1150 1151 1152 1153 1154 1155
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1156
	msleep(intel_dp->backlight_on_delay);
1157
	pp = ironlake_get_pp_control(dev_priv);
1158 1159
	pp |= EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1160
	POSTING_READ(PCH_PP_CONTROL);
1161 1162
}

1163
static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1164
{
1165
	struct drm_device *dev = intel_dp->base.base.dev;
1166 1167 1168
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1169 1170 1171
	if (!is_edp(intel_dp))
		return;

1172
	DRM_DEBUG_KMS("\n");
1173
	pp = ironlake_get_pp_control(dev_priv);
1174 1175
	pp &= ~EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1176 1177
	POSTING_READ(PCH_PP_CONTROL);
	msleep(intel_dp->backlight_off_delay);
1178
}
1179

1180 1181 1182 1183 1184 1185 1186 1187
static void ironlake_edp_pll_on(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1188
	dpa_ctl |= DP_PLL_ENABLE;
1189
	I915_WRITE(DP_A, dpa_ctl);
1190 1191
	POSTING_READ(DP_A);
	udelay(200);
1192 1193 1194 1195 1196 1197 1198 1199 1200
}

static void ironlake_edp_pll_off(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	dpa_ctl = I915_READ(DP_A);
1201
	dpa_ctl &= ~DP_PLL_ENABLE;
1202
	I915_WRITE(DP_A, dpa_ctl);
1203
	POSTING_READ(DP_A);
1204 1205 1206
	udelay(200);
}

1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236
/* If the sink supports it, try to set the power state appropriately */
static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1237 1238 1239 1240
static void intel_dp_prepare(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1241 1242 1243
	ironlake_edp_backlight_off(intel_dp);
	ironlake_edp_panel_off(intel_dp);

1244
	/* Wake up the sink first */
1245
	ironlake_edp_panel_vdd_on(intel_dp);
1246
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1247
	intel_dp_link_down(intel_dp);
1248
	ironlake_edp_panel_vdd_off(intel_dp, false);
1249

1250 1251 1252
	/* Make sure the panel is off before trying to
	 * change the mode
	 */
1253 1254 1255 1256 1257
}

static void intel_dp_commit(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1258 1259
	struct drm_device *dev = encoder->dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1260

1261
	ironlake_edp_panel_vdd_on(intel_dp);
1262
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1263
	intel_dp_start_link_train(intel_dp);
1264
	ironlake_edp_panel_on(intel_dp);
1265
	ironlake_edp_panel_vdd_off(intel_dp, true);
1266
	intel_dp_complete_link_train(intel_dp);
1267
	ironlake_edp_backlight_on(intel_dp);
1268 1269

	intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1270 1271 1272

	if (HAS_PCH_CPT(dev))
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1273 1274
}

1275 1276 1277
static void
intel_dp_dpms(struct drm_encoder *encoder, int mode)
{
C
Chris Wilson 已提交
1278
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1279
	struct drm_device *dev = encoder->dev;
1280
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
1281
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1282 1283

	if (mode != DRM_MODE_DPMS_ON) {
1284 1285 1286
		ironlake_edp_backlight_off(intel_dp);
		ironlake_edp_panel_off(intel_dp);

1287
		ironlake_edp_panel_vdd_on(intel_dp);
1288
		intel_dp_sink_dpms(intel_dp, mode);
1289
		intel_dp_link_down(intel_dp);
1290
		ironlake_edp_panel_vdd_off(intel_dp, false);
1291 1292 1293

		if (is_cpu_edp(intel_dp))
			ironlake_edp_pll_off(encoder);
1294
	} else {
1295 1296 1297
		if (is_cpu_edp(intel_dp))
			ironlake_edp_pll_on(encoder);

1298
		ironlake_edp_panel_vdd_on(intel_dp);
1299
		intel_dp_sink_dpms(intel_dp, mode);
1300
		if (!(dp_reg & DP_PORT_EN)) {
1301
			intel_dp_start_link_train(intel_dp);
1302
			ironlake_edp_panel_on(intel_dp);
1303
			ironlake_edp_panel_vdd_off(intel_dp, true);
1304
			intel_dp_complete_link_train(intel_dp);
1305
		} else
1306 1307
			ironlake_edp_panel_vdd_off(intel_dp, false);
		ironlake_edp_backlight_on(intel_dp);
1308
	}
1309
	intel_dp->dpms_mode = mode;
1310 1311 1312
}

/*
1313 1314
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1315 1316
 */
static bool
1317 1318
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1319
{
1320 1321
	int ret, i;

1322 1323 1324 1325
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1326
	for (i = 0; i < 3; i++) {
1327 1328 1329
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1330 1331 1332
			return true;
		msleep(1);
	}
1333

1334
	return false;
1335 1336 1337 1338 1339 1340 1341
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1342
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1343
{
1344 1345
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1346
					      link_status,
1347
					      DP_LINK_STATUS_SIZE);
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
}

static uint8_t
intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		     int r)
{
	return link_status[r - DP_LANE0_1_STATUS];
}

static uint8_t
1358
intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1359 1360 1361 1362 1363
				 int lane)
{
	int	    s = ((lane & 1) ?
			 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
			 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1364
	uint8_t l = adjust_request[lane>>1];
1365 1366 1367 1368 1369

	return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
}

static uint8_t
1370
intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1371 1372 1373 1374 1375
				      int lane)
{
	int	    s = ((lane & 1) ?
			 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
			 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1376
	uint8_t l = adjust_request[lane>>1];
1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399

	return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
}


#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1400
intel_dp_voltage_max(struct intel_dp *intel_dp)
1401
{
K
Keith Packard 已提交
1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
	struct drm_device *dev = intel_dp->base.base.dev;

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_800;
	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
	struct drm_device *dev = intel_dp->base.base.dev;

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1439 1440 1441 1442
	}
}

static void
1443
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1444 1445 1446 1447
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
1448
	uint8_t	*adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
K
Keith Packard 已提交
1449 1450
	uint8_t voltage_max;
	uint8_t preemph_max;
1451

1452
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1453 1454
		uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
		uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1455 1456 1457 1458 1459 1460 1461

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
1462
	voltage_max = intel_dp_voltage_max(intel_dp);
1463 1464
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1465

K
Keith Packard 已提交
1466 1467 1468
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1469 1470

	for (lane = 0; lane < 4; lane++)
1471
		intel_dp->train_set[lane] = v | p;
1472 1473 1474
}

static uint32_t
1475
intel_dp_signal_levels(uint8_t train_set)
1476
{
1477
	uint32_t	signal_levels = 0;
1478

1479
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
1494
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

1512 1513 1514 1515
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
1516 1517 1518
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
1519
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1520 1521 1522 1523
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1524
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1525 1526
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1527
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1528 1529
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1530
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1531 1532
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1533
	default:
1534 1535 1536
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1537 1538 1539
	}
}

K
Keith Packard 已提交
1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

1571 1572 1573 1574 1575
static uint8_t
intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
		      int lane)
{
	int s = (lane & 1) * 4;
1576
	uint8_t l = link_status[lane>>1];
1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600

	return (l >> s) & 0xf;
}

/* Check for clock recovery is done on all channels */
static bool
intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
{
	int lane;
	uint8_t lane_status;

	for (lane = 0; lane < lane_count; lane++) {
		lane_status = intel_get_lane_status(link_status, lane);
		if ((lane_status & DP_LANE_CR_DONE) == 0)
			return false;
	}
	return true;
}

/* Check to see if channel eq is done on all channels */
#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
			 DP_LANE_CHANNEL_EQ_DONE|\
			 DP_LANE_SYMBOL_LOCKED)
static bool
1601
intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1602 1603 1604 1605 1606
{
	uint8_t lane_align;
	uint8_t lane_status;
	int lane;

1607
	lane_align = intel_dp_link_status(link_status,
1608 1609 1610
					  DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		return false;
1611
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1612
		lane_status = intel_get_lane_status(link_status, lane);
1613 1614 1615 1616 1617 1618 1619
		if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
			return false;
	}
	return true;
}

static bool
C
Chris Wilson 已提交
1620
intel_dp_set_link_train(struct intel_dp *intel_dp,
1621
			uint32_t dp_reg_value,
1622
			uint8_t dp_train_pat)
1623
{
1624
	struct drm_device *dev = intel_dp->base.base.dev;
1625 1626 1627
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

C
Chris Wilson 已提交
1628 1629
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
	POSTING_READ(intel_dp->output_reg);
1630

C
Chris Wilson 已提交
1631
	intel_dp_aux_native_write_1(intel_dp,
1632 1633 1634
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

C
Chris Wilson 已提交
1635
	ret = intel_dp_aux_native_write(intel_dp,
1636
					DP_TRAINING_LANE0_SET,
1637 1638 1639
					intel_dp->train_set,
					intel_dp->lane_count);
	if (ret != intel_dp->lane_count)
1640 1641 1642 1643 1644
		return false;

	return true;
}

1645
/* Enable corresponding port and start training pattern 1 */
1646
static void
1647
intel_dp_start_link_train(struct intel_dp *intel_dp)
1648
{
1649
	struct drm_device *dev = intel_dp->base.base.dev;
1650
	struct drm_i915_private *dev_priv = dev->dev_private;
1651
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1652 1653 1654
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
1655
	int voltage_tries, loop_tries;
1656
	u32 reg;
C
Chris Wilson 已提交
1657
	uint32_t DP = intel_dp->DP;
1658

1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
	/*
	 * On CPT we have to enable the port in training pattern 1, which
	 * will happen below in intel_dp_set_link_train.  Otherwise, enable
	 * the port and wait for it to become active.
	 */
	if (!HAS_PCH_CPT(dev)) {
		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
		POSTING_READ(intel_dp->output_reg);
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	}
1669

1670 1671 1672 1673
	/* Write the link configuration data */
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
				  intel_dp->link_configuration,
				  DP_LINK_CONFIGURATION_SIZE);
1674 1675

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
1676 1677

	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1678 1679 1680
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
	else
		DP &= ~DP_LINK_TRAIN_MASK;
1681
	memset(intel_dp->train_set, 0, 4);
1682
	voltage = 0xff;
1683 1684
	voltage_tries = 0;
	loop_tries = 0;
1685 1686
	clock_recovery = false;
	for (;;) {
1687
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1688
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1689
		uint32_t    signal_levels;
1690

K
Keith Packard 已提交
1691 1692 1693 1694 1695

		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1696
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1697 1698
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
1699 1700
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1701 1702
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}
1703

K
Keith Packard 已提交
1704
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1705 1706 1707 1708
			reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
		else
			reg = DP | DP_LINK_TRAIN_PAT_1;

C
Chris Wilson 已提交
1709
		if (!intel_dp_set_link_train(intel_dp, reg,
1710 1711
					     DP_TRAINING_PATTERN_1 |
					     DP_LINK_SCRAMBLING_DISABLE))
1712 1713 1714
			break;
		/* Set training pattern 1 */

1715
		udelay(100);
1716 1717
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
1718
			break;
1719
		}
1720

1721 1722
		if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
			DRM_DEBUG_KMS("clock recovery OK\n");
1723 1724 1725 1726 1727 1728 1729
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1730
				break;
1731 1732 1733 1734 1735 1736 1737 1738 1739 1740
		if (i == intel_dp->lane_count) {
			++loop_tries;
			if (loop_tries == 5) {
				DRM_DEBUG_KMS("too many full retries, give up\n");
				break;
			}
			memset(intel_dp->train_set, 0, 4);
			voltage_tries = 0;
			continue;
		}
1741

1742 1743
		/* Check to see if we've tried the same voltage 5 times */
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1744 1745 1746
			++voltage_tries;
			if (voltage_tries == 5) {
				DRM_DEBUG_KMS("too many voltage retries, give up\n");
1747
				break;
1748
			}
1749
		} else
1750
			voltage_tries = 0;
1751
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1752

1753
		/* Compute new intel_dp->train_set as requested by target */
1754
		intel_get_adjust_train(intel_dp, link_status);
1755 1756
	}

1757 1758 1759 1760 1761 1762
	intel_dp->DP = DP;
}

static void
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
1763
	struct drm_device *dev = intel_dp->base.base.dev;
1764 1765
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool channel_eq = false;
1766
	int tries, cr_tries;
1767 1768 1769
	u32 reg;
	uint32_t DP = intel_dp->DP;

1770 1771
	/* channel equalization */
	tries = 0;
1772
	cr_tries = 0;
1773 1774
	channel_eq = false;
	for (;;) {
1775
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1776
		uint32_t    signal_levels;
1777
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1778

1779 1780 1781 1782 1783 1784
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

K
Keith Packard 已提交
1785 1786 1787 1788
		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1789
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1790 1791
			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
		} else {
1792
			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1793 1794 1795
			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
		}

K
Keith Packard 已提交
1796
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1797 1798 1799
			reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
		else
			reg = DP | DP_LINK_TRAIN_PAT_2;
1800 1801

		/* channel eq pattern */
C
Chris Wilson 已提交
1802
		if (!intel_dp_set_link_train(intel_dp, reg,
1803 1804
					     DP_TRAINING_PATTERN_2 |
					     DP_LINK_SCRAMBLING_DISABLE))
1805 1806
			break;

1807
		udelay(400);
1808
		if (!intel_dp_get_link_status(intel_dp, link_status))
1809 1810
			break;

1811
		/* Make sure clock is still ok */
1812
		if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1813 1814 1815 1816 1817
			intel_dp_start_link_train(intel_dp);
			cr_tries++;
			continue;
		}

1818
		if (intel_channel_eq_ok(intel_dp, link_status)) {
1819 1820 1821
			channel_eq = true;
			break;
		}
1822

1823 1824 1825 1826 1827 1828 1829 1830
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
			tries = 0;
			cr_tries++;
			continue;
		}
1831

1832
		/* Compute new intel_dp->train_set as requested by target */
1833
		intel_get_adjust_train(intel_dp, link_status);
1834
		++tries;
1835
	}
1836

K
Keith Packard 已提交
1837
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1838 1839 1840 1841
		reg = DP | DP_LINK_TRAIN_OFF_CPT;
	else
		reg = DP | DP_LINK_TRAIN_OFF;

C
Chris Wilson 已提交
1842 1843 1844
	I915_WRITE(intel_dp->output_reg, reg);
	POSTING_READ(intel_dp->output_reg);
	intel_dp_aux_native_write_1(intel_dp,
1845 1846 1847 1848
				    DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
}

static void
C
Chris Wilson 已提交
1849
intel_dp_link_down(struct intel_dp *intel_dp)
1850
{
1851
	struct drm_device *dev = intel_dp->base.base.dev;
1852
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
1853
	uint32_t DP = intel_dp->DP;
1854

1855 1856 1857
	if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
		return;

1858
	DRM_DEBUG_KMS("\n");
1859

1860
	if (is_edp(intel_dp)) {
1861
		DP &= ~DP_PLL_ENABLE;
C
Chris Wilson 已提交
1862 1863
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);
1864 1865 1866
		udelay(100);
	}

K
Keith Packard 已提交
1867
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1868
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
1869
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1870 1871
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
1872
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1873
	}
1874
	POSTING_READ(intel_dp->output_reg);
1875

1876
	msleep(17);
1877

1878
	if (is_edp(intel_dp)) {
K
Keith Packard 已提交
1879
		if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1880 1881 1882 1883
			DP |= DP_LINK_TRAIN_OFF_CPT;
		else
			DP |= DP_LINK_TRAIN_OFF;
	}
1884

1885 1886
	if (!HAS_PCH_CPT(dev) &&
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1887 1888
		struct drm_crtc *crtc = intel_dp->base.base.crtc;

1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915
		if (crtc == NULL) {
			/* We can arrive here never having been attached
			 * to a CRTC, for instance, due to inheriting
			 * random state from the BIOS.
			 *
			 * If the pipe is not running, play safe and
			 * wait for the clocks to stabilise before
			 * continuing.
			 */
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
			intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1916 1917
	}

1918
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
1919 1920
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
1921
	msleep(intel_dp->panel_power_down_delay);
1922 1923
}

1924 1925
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
1926 1927
{
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1928
					   sizeof(intel_dp->dpcd)) &&
1929
	    (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1930
		return true;
1931 1932
	}

1933
	return false;
1934 1935
}

1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
}

1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

static void
C
Chris Wilson 已提交
1967
intel_dp_check_link_status(struct intel_dp *intel_dp)
1968
{
1969
	u8 sink_irq_vector;
1970
	u8 link_status[DP_LINK_STATUS_SIZE];
1971

1972 1973
	if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
		return;
1974

1975
	if (!intel_dp->base.base.crtc)
1976 1977
		return;

1978
	/* Try to read receiver status if the link appears to be up */
1979
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
1980
		intel_dp_link_down(intel_dp);
1981 1982 1983
		return;
	}

1984
	/* Now read the DPCD to see if it's actually running */
1985
	if (!intel_dp_get_dpcd(intel_dp)) {
1986 1987 1988 1989
		intel_dp_link_down(intel_dp);
		return;
	}

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2004
	if (!intel_channel_eq_ok(intel_dp, link_status)) {
2005 2006
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
			      drm_get_encoder_name(&intel_dp->base.base));
2007 2008 2009
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
	}
2010 2011
}

2012
static enum drm_connector_status
2013
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2014
{
2015 2016 2017
	if (intel_dp_get_dpcd(intel_dp))
		return connector_status_connected;
	return connector_status_disconnected;
2018 2019
}

2020
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2021
ironlake_dp_detect(struct intel_dp *intel_dp)
2022 2023 2024
{
	enum drm_connector_status status;

2025 2026 2027 2028 2029 2030 2031
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		status = intel_panel_detect(intel_dp->base.base.dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2032

2033
	return intel_dp_detect_dpcd(intel_dp);
2034 2035
}

2036
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2037
g4x_dp_detect(struct intel_dp *intel_dp)
2038
{
2039
	struct drm_device *dev = intel_dp->base.base.dev;
2040
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
2041
	uint32_t temp, bit;
2042

C
Chris Wilson 已提交
2043
	switch (intel_dp->output_reg) {
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
	case DP_B:
		bit = DPB_HOTPLUG_INT_STATUS;
		break;
	case DP_C:
		bit = DPC_HOTPLUG_INT_STATUS;
		break;
	case DP_D:
		bit = DPD_HOTPLUG_INT_STATUS;
		break;
	default:
		return connector_status_unknown;
	}

	temp = I915_READ(PORT_HOTPLUG_STAT);

	if ((temp & bit) == 0)
		return connector_status_disconnected;

2062
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2063 2064
}

2065 2066 2067 2068 2069 2070 2071 2072
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid	*edid;

	ironlake_edp_panel_vdd_on(intel_dp);
	edid = drm_get_edid(connector, adapter);
2073
	ironlake_edp_panel_vdd_off(intel_dp, false);
2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
	return edid;
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	int	ret;

	ironlake_edp_panel_vdd_on(intel_dp);
	ret = intel_ddc_get_modes(connector, adapter);
2085
	ironlake_edp_panel_vdd_off(intel_dp, false);
2086 2087 2088 2089
	return ret;
}


Z
Zhenyu Wang 已提交
2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
 *
 * \return true if DP port is connected.
 * \return false if DP port is disconnected.
 */
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct drm_device *dev = intel_dp->base.base.dev;
	enum drm_connector_status status;
	struct edid *edid = NULL;

	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
2110

2111 2112 2113 2114
	DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
		      intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
		      intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
		      intel_dp->dpcd[6], intel_dp->dpcd[7]);
2115

Z
Zhenyu Wang 已提交
2116 2117 2118
	if (status != connector_status_connected)
		return status;

2119 2120
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2121
	} else {
2122
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2123 2124 2125 2126 2127
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			connector->display_info.raw_edid = NULL;
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
2128 2129 2130
	}

	return connector_status_connected;
2131 2132 2133 2134
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
2135
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2136
	struct drm_device *dev = intel_dp->base.base.dev;
2137 2138
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
2139 2140 2141 2142

	/* We should parse the EDID data and find out if it has an audio sink
	 */

2143
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2144
	if (ret) {
2145
		if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2146 2147 2148
			struct drm_display_mode *newmode;
			list_for_each_entry(newmode, &connector->probed_modes,
					    head) {
2149 2150
				if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
					intel_dp->panel_fixed_mode =
2151 2152 2153 2154 2155
						drm_mode_duplicate(dev, newmode);
					break;
				}
			}
		}
2156
		return ret;
2157
	}
2158 2159

	/* if eDP has no EDID, try to use fixed panel mode from VBT */
2160
	if (is_edp(intel_dp)) {
2161
		/* initialize panel mode from VBT if available for eDP */
2162 2163
		if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
			intel_dp->panel_fixed_mode =
2164
				drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2165 2166
			if (intel_dp->panel_fixed_mode) {
				intel_dp->panel_fixed_mode->type |=
2167 2168 2169
					DRM_MODE_TYPE_PREFERRED;
			}
		}
2170
		if (intel_dp->panel_fixed_mode) {
2171
			struct drm_display_mode *mode;
2172
			mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2173 2174 2175 2176 2177
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
2178 2179
}

2180 2181 2182 2183 2184 2185 2186
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

2187
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

2198 2199 2200 2201 2202
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
2203
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
2204 2205 2206 2207 2208 2209 2210
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

2211
	if (property == dev_priv->force_audio_property) {
2212 2213 2214 2215
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
2216 2217
			return 0;

2218
		intel_dp->force_audio = i;
2219

2220
		if (i == HDMI_AUDIO_AUTO)
2221 2222
			has_audio = intel_dp_detect_audio(connector);
		else
2223
			has_audio = (i == HDMI_AUDIO_ON);
2224 2225

		if (has_audio == intel_dp->has_audio)
2226 2227
			return 0;

2228
		intel_dp->has_audio = has_audio;
2229 2230 2231
		goto done;
	}

2232 2233 2234 2235 2236 2237 2238 2239
	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_dp->color_range)
			return 0;

		intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
		goto done;
	}

2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
	return -EINVAL;

done:
	if (intel_dp->base.base.crtc) {
		struct drm_crtc *crtc = intel_dp->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

2253
static void
2254
intel_dp_destroy(struct drm_connector *connector)
2255
{
2256 2257 2258 2259 2260
	struct drm_device *dev = connector->dev;

	if (intel_dpd_is_edp(dev))
		intel_panel_destroy_backlight(dev);

2261 2262
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
2263
	kfree(connector);
2264 2265
}

2266 2267 2268 2269 2270 2271
static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
2272 2273 2274 2275
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		ironlake_panel_vdd_off_sync(intel_dp);
	}
2276 2277 2278
	kfree(intel_dp);
}

2279 2280 2281
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.dpms = intel_dp_dpms,
	.mode_fixup = intel_dp_mode_fixup,
2282
	.prepare = intel_dp_prepare,
2283
	.mode_set = intel_dp_mode_set,
2284
	.commit = intel_dp_commit,
2285 2286 2287 2288 2289 2290
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
2291
	.set_property = intel_dp_set_property,
2292 2293 2294 2295 2296 2297
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
2298
	.best_encoder = intel_best_encoder,
2299 2300 2301
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2302
	.destroy = intel_dp_encoder_destroy,
2303 2304
};

2305
static void
2306
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2307
{
C
Chris Wilson 已提交
2308
	struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2309

2310
	intel_dp_check_link_status(intel_dp);
2311
}
2312

2313 2314
/* Return which DP Port should be selected for Transcoder DP control */
int
2315
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2316 2317 2318 2319 2320 2321
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_encoder *encoder;

	list_for_each_entry(encoder, &mode_config->encoder_list, head) {
C
Chris Wilson 已提交
2322 2323
		struct intel_dp *intel_dp;

2324
		if (encoder->crtc != crtc)
2325 2326
			continue;

C
Chris Wilson 已提交
2327
		intel_dp = enc_to_intel_dp(encoder);
2328 2329
		if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_dp->base.type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
2330
			return intel_dp->output_reg;
2331
	}
C
Chris Wilson 已提交
2332

2333 2334 2335
	return -1;
}

2336
/* check the VBT to see whether the eDP is on DP-D port */
2337
bool intel_dpd_is_edp(struct drm_device *dev)
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i;

	if (!dev_priv->child_dev_num)
		return false;

	for (i = 0; i < dev_priv->child_dev_num; i++) {
		p_child = dev_priv->child_dev + i;

		if (p_child->dvo_port == PORT_IDPD &&
		    p_child->device_type == DEVICE_TYPE_eDP)
			return true;
	}
	return false;
}

2356 2357 2358
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
2359
	intel_attach_force_audio_property(connector);
2360
	intel_attach_broadcast_rgb_property(connector);
2361 2362
}

2363 2364 2365 2366 2367
void
intel_dp_init(struct drm_device *dev, int output_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
C
Chris Wilson 已提交
2368
	struct intel_dp *intel_dp;
2369
	struct intel_encoder *intel_encoder;
2370
	struct intel_connector *intel_connector;
2371
	const char *name = NULL;
2372
	int type;
2373

C
Chris Wilson 已提交
2374 2375
	intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
	if (!intel_dp)
2376 2377
		return;

2378
	intel_dp->output_reg = output_reg;
2379
	intel_dp->dpms_mode = -1;
2380

2381 2382
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
C
Chris Wilson 已提交
2383
		kfree(intel_dp);
2384 2385
		return;
	}
C
Chris Wilson 已提交
2386
	intel_encoder = &intel_dp->base;
2387

C
Chris Wilson 已提交
2388
	if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2389
		if (intel_dpd_is_edp(dev))
C
Chris Wilson 已提交
2390
			intel_dp->is_pch_edp = true;
2391

2392
	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2393 2394 2395 2396 2397 2398 2399
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
	} else {
		type = DRM_MODE_CONNECTOR_DisplayPort;
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
	}

2400
	connector = &intel_connector->base;
2401
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2402 2403
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

2404 2405
	connector->polled = DRM_CONNECTOR_POLL_HPD;

2406
	if (output_reg == DP_B || output_reg == PCH_DP_B)
2407
		intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2408
	else if (output_reg == DP_C || output_reg == PCH_DP_C)
2409
		intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2410
	else if (output_reg == DP_D || output_reg == PCH_DP_D)
2411
		intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2412

2413
	if (is_edp(intel_dp)) {
2414
		intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2415 2416 2417
		INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
				  ironlake_panel_vdd_work);
	}
Z
Zhenyu Wang 已提交
2418

J
Jesse Barnes 已提交
2419
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2420 2421 2422
	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

2423
	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2424
			 DRM_MODE_ENCODER_TMDS);
2425
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2426

2427
	intel_connector_attach_encoder(intel_connector, intel_encoder);
2428 2429 2430
	drm_sysfs_connector_add(connector);

	/* Set up the DDC bus. */
2431
	switch (output_reg) {
2432 2433 2434
		case DP_A:
			name = "DPDDC-A";
			break;
2435 2436
		case DP_B:
		case PCH_DP_B:
2437 2438
			dev_priv->hotplug_supported_mask |=
				HDMIB_HOTPLUG_INT_STATUS;
2439 2440 2441 2442
			name = "DPDDC-B";
			break;
		case DP_C:
		case PCH_DP_C:
2443 2444
			dev_priv->hotplug_supported_mask |=
				HDMIC_HOTPLUG_INT_STATUS;
2445 2446 2447 2448
			name = "DPDDC-C";
			break;
		case DP_D:
		case PCH_DP_D:
2449 2450
			dev_priv->hotplug_supported_mask |=
				HDMID_HOTPLUG_INT_STATUS;
2451 2452 2453 2454
			name = "DPDDC-D";
			break;
	}

J
Jesse Barnes 已提交
2455 2456
	/* Cache some DPCD data in the eDP case */
	if (is_edp(intel_dp)) {
2457
		bool ret;
2458 2459
		struct edp_power_seq	cur, vbt;
		u32 pp_on, pp_off, pp_div;
2460 2461

		pp_on = I915_READ(PCH_PP_ON_DELAYS);
2462
		pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2463
		pp_div = I915_READ(PCH_PP_DIVISOR);
J
Jesse Barnes 已提交
2464

2465 2466 2467 2468 2469 2470 2471
		if (!pp_on || !pp_off || !pp_div) {
			DRM_INFO("bad panel power sequencing delays, disabling panel\n");
			intel_dp_encoder_destroy(&intel_dp->base.base);
			intel_dp_destroy(&intel_connector->base);
			return;
		}

2472 2473 2474 2475 2476 2477
		/* Pull timing values out of registers */
		cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
			PANEL_POWER_UP_DELAY_SHIFT;

		cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
			PANEL_LIGHT_ON_DELAY_SHIFT;
2478

2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509
		cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
			PANEL_LIGHT_OFF_DELAY_SHIFT;

		cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
			PANEL_POWER_DOWN_DELAY_SHIFT;

		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
			       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

		DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
			      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

		vbt = dev_priv->edp.pps;

		DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
			      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

#define get_delay(field)	((max(cur.field, vbt.field) + 9) / 10)

		intel_dp->panel_power_up_delay = get_delay(t1_t3);
		intel_dp->backlight_on_delay = get_delay(t8);
		intel_dp->backlight_off_delay = get_delay(t9);
		intel_dp->panel_power_down_delay = get_delay(t10);
		intel_dp->panel_power_cycle_delay = get_delay(t11_t12);

		DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
			      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
			      intel_dp->panel_power_cycle_delay);

		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
			      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2510 2511

		ironlake_edp_panel_vdd_on(intel_dp);
2512
		ret = intel_dp_get_dpcd(intel_dp);
2513
		ironlake_edp_panel_vdd_off(intel_dp, false);
2514

2515
		if (ret) {
2516 2517 2518
			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
				dev_priv->no_aux_handshake =
					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
J
Jesse Barnes 已提交
2519 2520
					DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		} else {
2521
			/* if this fails, presume the device is a ghost */
2522
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2523
			intel_dp_encoder_destroy(&intel_dp->base.base);
2524
			intel_dp_destroy(&intel_connector->base);
2525
			return;
J
Jesse Barnes 已提交
2526 2527 2528
		}
	}

2529 2530
	intel_dp_i2c_init(intel_dp, intel_connector, name);

2531
	intel_encoder->hot_plug = intel_dp_hot_plug;
2532

2533
	if (is_edp(intel_dp)) {
2534 2535
		dev_priv->int_edp_connector = connector;
		intel_panel_setup_backlight(dev);
2536 2537
	}

2538 2539
	intel_dp_add_properties(intel_dp, connector);

2540 2541 2542 2543 2544 2545 2546 2547 2548
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}