i915_drv.h 80.3 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hash.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/mm_types.h>
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#include <linux/perf_event.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>
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#include <linux/stackdepot.h>
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#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include <drm/drm_util.h>
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#include <drm/drm_dsc.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_connector.h>
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#include <drm/i915_mei_hdcp_interface.h>
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#include "i915_fixed.h"
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_frontbuffer.h"
#include "display/intel_opregion.h"

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#include "gt/intel_lrc.h"
#include "gt/intel_engine.h"
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#include "gt/intel_gt_types.h"
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#include "gt/intel_workarounds.h"

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#include "intel_device_info.h"
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#include "intel_runtime_pm.h"
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#include "intel_uc.h"
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#include "intel_uncore.h"
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#include "intel_wakeref.h"
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#include "intel_wopcm.h"
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#include "i915_gem.h"
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#include "gem/i915_gem_context_types.h"
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#include "i915_gem_fence_reg.h"
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#include "i915_gem_gtt.h"
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#include "i915_gpu_error.h"
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#include "i915_request.h"
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#include "i915_scheduler.h"
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#include "gt/intel_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20190619"
#define DRIVER_TIMESTAMP	1560947544
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
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		if (!WARN(i915_modparams.verbose_state_checks, format))	\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)
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bool i915_error_injected(void);

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#else
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#define i915_inject_load_failure() false
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#define i915_error_injected() false

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#endif
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#define i915_load_error(i915, fmt, ...)					 \
	__i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
		      fmt, ##__VA_ARGS__)

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struct drm_i915_gem_object;

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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_PORT_F,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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/* Threshold == 5 for long IRQs, 50 for short */
#define HPD_STORM_DEFAULT_THRESHOLD 50
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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;
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	/* Whether or not to count short HPD IRQs in HPD storms */
	u8 hpd_short_storm_enabled;
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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
	} mm;
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	struct idr context_idr;
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	struct mutex context_idr_lock; /* guards context_idr */
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	struct idr vm_idr;
	struct mutex vm_idr_lock; /* guards vm_idr */

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	unsigned int bsd_engine;
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/*
 * Every context ban increments per client ban score. Also
 * hangs in short succession increments ban score. If ban threshold
 * is reached, client is considered banned and submitting more work
 * will fail. This is a stop gap measure to limit the badly behaving
 * clients access to gpu. Note that unbannable contexts never increment
 * the client ban score.
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 */
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#define I915_CLIENT_SCORE_HANG_FAST	1
#define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
#define I915_CLIENT_SCORE_CONTEXT_BAN   3
#define I915_CLIENT_SCORE_BANNED	9
	/** ban_score: Accumulated score of all ctx bans and fast hangs. */
	atomic_t ban_score;
	unsigned long hang_timestamp;
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};

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct intel_overlay;
struct intel_overlay_error_state;

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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct intel_cdclk_state;
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struct drm_i915_display_funcs {
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	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
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	void (*set_cdclk)(struct drm_i915_private *dev_priv,
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			  const struct intel_cdclk_state *cdclk_state,
			  enum pipe pipe);
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	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
			     enum i9xx_plane_id i9xx_plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
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	void (*initial_watermarks)(struct intel_atomic_state *state,
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				   struct intel_crtc_state *crtc_state);
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	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
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					 struct intel_crtc_state *crtc_state);
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	void (*optimize_watermarks)(struct intel_atomic_state *state,
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				    struct intel_crtc_state *crtc_state);
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	int (*compute_global_watermarks)(struct intel_atomic_state *state);
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	void (*update_wm)(struct intel_crtc *crtc);
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	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
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			    struct intel_atomic_state *old_state);
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	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
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			     struct intel_atomic_state *old_state);
	void (*update_crtcs)(struct intel_atomic_state *state);
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	void (*audio_codec_enable)(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state);
	void (*audio_codec_disable)(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state);
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	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
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	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
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	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	int (*color_check)(struct intel_crtc_state *crtc_state);
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	/*
	 * Program double buffered color management registers during
	 * vblank evasion. The registers should then latch during the
	 * next vblank start, alongside any other double buffered registers
	 * involved with the same commit.
	 */
	void (*color_commit)(const struct intel_crtc_state *crtc_state);
	/*
	 * Load LUTs (and other single buffered color management
	 * registers). Will (hopefully) be called during the vblank
	 * following the latching of any double buffered registers
	 * involved with the same commit.
	 */
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	void (*load_luts)(const struct intel_crtc_state *crtc_state);
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	void (*read_luts)(struct intel_crtc_state *crtc_state);
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};

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struct intel_csr {
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	struct work_struct work;
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	const char *fw_path;
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	u32 required_version;
	u32 max_fw_size; /* bytes */
	u32 *dmc_payload;
	u32 dmc_fw_size; /* dwords */
	u32 version;
	u32 mmio_count;
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	i915_reg_t mmioaddr[20];
	u32 mmiodata[20];
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	u32 dc_state;
	u32 allowed_dc_mask;
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	intel_wakeref_t wakeref;
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};

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enum i915_cache_level {
	I915_CACHE_NONE = 0,
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	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
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	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
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};

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#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

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struct intel_fbc {
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	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
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	unsigned threshold;
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	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
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	unsigned int visible_pipes_mask;
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	struct intel_crtc *crtc;
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	struct drm_mm_node compressed_fb;
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	struct drm_mm_node *compressed_llb;

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	bool false_color;

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	bool enabled;
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	bool active;
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	bool flip_pending;
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	bool underrun_detected;
	struct work_struct underrun_work;

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	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
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	struct intel_fbc_state_cache {
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		struct i915_vma *vma;
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		unsigned long flags;
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		struct {
			unsigned int mode_flags;
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			u32 hsw_bdw_pixel_rate;
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		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
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			/*
			 * Display surface base address adjustement for
			 * pageflips. Note that on gen4+ this only adjusts up
			 * to a tile, offsets within a tile are handled in
			 * the hw itself (with the TILEOFF register).
			 */
			int adjusted_x;
			int adjusted_y;
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			int y;
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			u16 pixel_blend_mode;
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		} plane;

		struct {
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			const struct drm_format_info *format;
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			unsigned int stride;
		} fb;
	} state_cache;

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	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
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	struct intel_fbc_reg_params {
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		struct i915_vma *vma;
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		unsigned long flags;
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		struct {
			enum pipe pipe;
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			enum i9xx_plane_id i9xx_plane;
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			unsigned int fence_y_offset;
		} crtc;

		struct {
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			const struct drm_format_info *format;
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			unsigned int stride;
		} fb;

		int cfb_size;
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		unsigned int gen9_wa_cfb_stride;
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	} params;

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	const char *no_fbc_reason;
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};

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/*
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 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
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};

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struct intel_dp;
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struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

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struct i915_psr {
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	struct mutex lock;
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#define I915_PSR_DEBUG_MODE_MASK	0x0f
#define I915_PSR_DEBUG_DEFAULT		0x00
#define I915_PSR_DEBUG_DISABLE		0x01
#define I915_PSR_DEBUG_ENABLE		0x02
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#define I915_PSR_DEBUG_FORCE_PSR1	0x03
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#define I915_PSR_DEBUG_IRQ		0x10

	u32 debug;
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	bool sink_support;
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	bool enabled;
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	struct intel_dp *dp;
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	enum pipe pipe;
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	bool active;
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	struct work_struct work;
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	unsigned busy_frontbuffer_bits;
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	bool sink_psr2_support;
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	bool link_standby;
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	bool colorimetry_support;
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	bool psr2_enabled;
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	u8 sink_sync_latency;
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	ktime_t last_entry_attempt;
	ktime_t last_exit;
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	bool sink_not_reliable;
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	bool irq_aux_error;
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	u16 su_x_granularity;
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};
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/*
 * Sorted by south display engine compatibility.
 * If the new PCH comes with a south display engine that is not
 * inherited from the latest item, please do not add it to the
 * end. Instead, add it right after its "parent" PCH.
 */
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enum intel_pch {
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	PCH_NOP = -1,	/* PCH without south display */
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	PCH_NONE = 0,	/* No PCH present */
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	PCH_IBX,	/* Ibexpeak PCH */
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	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
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	PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
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	PCH_CNP,        /* Cannon/Comet Lake PCH */
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	PCH_ICP,	/* Ice Lake PCH */
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	PCH_MCC,        /* Mule Creek Canyon PCH */
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};

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#define QUIRK_LVDS_SSC_DISABLE (1<<1)
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#define QUIRK_INVERT_BRIGHTNESS (1<<2)
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#define QUIRK_BACKLIGHT_PRESENT (1<<3)
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#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
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#define QUIRK_INCREASE_T12_DELAY (1<<6)
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#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
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struct intel_fbdev;
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struct intel_fbc_work;
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struct intel_gmbus {
	struct i2c_adapter adapter;
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#define GMBUS_FORCE_BIT_RETRY (1U << 31)
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	u32 force_bit;
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	u32 reg0;
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	i915_reg_t gpio_reg;
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	struct i2c_algo_bit_data bit_algo;
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	struct drm_i915_private *dev_priv;
};

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struct i915_suspend_saved_registers {
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	u32 saveDSPARB;
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	u32 saveFBC_CONTROL;
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	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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	u32 saveSWF0[16];
	u32 saveSWF1[16];
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	u32 saveSWF3[3];
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	u64 saveFENCE[I915_MAX_NUM_FENCES];
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	u32 savePCH_PORT_HOTPLUG;
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	u16 saveGCDGMBUS;
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};
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struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
632
	u32 pcbr;
633 634 635
	u32 clock_gate_dis2;
};

636
struct intel_rps_ei {
637
	ktime_t ktime;
638 639
	u32 render_c0;
	u32 media_c0;
640 641
};

642
struct intel_rps {
643 644
	struct mutex lock; /* protects enabling and the worker */

I
Imre Deak 已提交
645 646 647 648
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
649
	struct work_struct work;
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Imre Deak 已提交
650
	bool interrupts_enabled;
651
	u32 pm_iir;
652

653
	/* PM interrupt bits that should never be masked */
654
	u32 pm_intrmsk_mbz;
655

656 657 658 659 660 661 662 663 664 665 666 667 668 669 670
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
671
	u8 boost_freq;		/* Frequency to request when wait boosting */
672
	u8 idle_freq;		/* Frequency to request when we are idle */
673 674 675
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
676
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
677

678
	int last_adj;
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Chris Wilson 已提交
679 680 681 682 683 684 685 686 687 688

	struct {
		struct mutex mutex;

		enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
		unsigned int interactive;

		u8 up_threshold; /* Current %busy required to uplock */
		u8 down_threshold; /* Current %busy required to downclock */
	} power;
689

690
	bool enabled;
691 692
	atomic_t num_waiters;
	atomic_t boosts;
693

694
	/* manual wa residency calculations */
695
	struct intel_rps_ei ei;
696 697
};

698 699
struct intel_rc6 {
	bool enabled;
700 701
	u64 prev_hw_residency[4];
	u64 cur_residency[4];
702 703 704 705 706 707
};

struct intel_llc_pstate {
	bool enabled;
};

708 709
struct intel_gen6_power_mgmt {
	struct intel_rps rps;
710 711
	struct intel_rc6 rc6;
	struct intel_llc_pstate llc_pstate;
712 713
};

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Daniel Vetter 已提交
714 715 716
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

717 718 719 720 721 722 723 724 725 726 727
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
728
	u64 last_time2;
729 730 731 732 733 734 735
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

736
#define MAX_L3_SLICES 2
737
struct intel_l3_parity {
738
	u32 *remap_info[MAX_L3_SLICES];
739
	struct work_struct error_work;
740
	int which_slice;
741 742
};

743 744 745
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
746 747 748 749
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

750 751 752
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

753
	/**
754
	 * List of objects which are purgeable.
755
	 */
756 757
	struct list_head purge_list;

758
	/**
759
	 * List of objects which have allocated pages and are shrinkable.
760
	 */
761
	struct list_head shrink_list;
762

763 764 765 766 767
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
768
	spinlock_t free_lock;
769 770 771 772 773
	/**
	 * Count of objects pending destructions. Used to skip needlessly
	 * waiting on an RCU barrier if no objects are waiting to be freed.
	 */
	atomic_t free_count;
774

775 776 777
	/**
	 * Small stash of WC pages
	 */
778
	struct pagestash wc_stash;
779

M
Matthew Auld 已提交
780 781 782 783 784
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

785
	/** PPGTT used for aliasing the PPGTT with the GTT */
786
	struct i915_ppgtt *aliasing_ppgtt;
787

788
	struct notifier_block oom_notifier;
789
	struct notifier_block vmap_notifier;
790
	struct shrinker shrinker;
791

792 793 794 795 796 797 798
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

799 800
	u64 unordered_timeline;

801
	/* the indicator for dispatch video commands on two BSD rings */
802
	atomic_t bsd_engine_dispatch_index;
803

804
	/** Bit 6 swizzling required for X tiling */
805
	u32 bit_6_swizzle_x;
806
	/** Bit 6 swizzling required for Y tiling */
807
	u32 bit_6_swizzle_y;
808

809 810 811
	/* shrinker accounting, also useful for userland debugging */
	u64 shrink_memory;
	u32 shrink_count;
812 813
};

814 815
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */

816 817 818
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

819 820 821
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

822 823
#define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */

824
struct ddi_vbt_port_info {
825 826 827
	/* Non-NULL if port present. */
	const struct child_device_config *child;

828 829
	int max_tmds_clock;

830 831 832 833 834 835
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
836
	u8 hdmi_level_shift;
837

838 839 840 841 842 843
	u8 supports_dvi:1;
	u8 supports_hdmi:1;
	u8 supports_dp:1;
	u8 supports_edp:1;
	u8 supports_typec_usb:1;
	u8 supports_tbt:1;
844

845 846
	u8 alternate_aux_channel;
	u8 alternate_ddc_pin;
847

848 849
	u8 dp_boost_level;
	u8 hdmi_boost_level;
850
	int dp_max_link_rate;		/* 0 for not limited by VBT */
851 852
};

R
Rodrigo Vivi 已提交
853 854 855 856 857
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
858 859
};

860 861 862 863 864 865 866 867 868
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
869
	unsigned int int_lvds_support:1;
870 871
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
872
	unsigned int panel_type:4;
873 874
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
875
	enum drm_panel_orientation orientation;
876

877 878
	enum drrs_support_type drrs_type;

879 880 881 882 883
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
884
		bool low_vswing;
885 886 887 888
		bool initialized;
		int bpp;
		struct edp_power_seq pps;
	} edp;
889

R
Rodrigo Vivi 已提交
890
	struct {
891
		bool enable;
R
Rodrigo Vivi 已提交
892 893 894 895
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
896 897
		int tp1_wakeup_time_us;
		int tp2_tp3_wakeup_time_us;
898
		int psr2_tp2_tp3_wakeup_time_us;
R
Rodrigo Vivi 已提交
899 900
	} psr;

901 902
	struct {
		u16 pwm_freq_hz;
903
		bool present;
904
		bool active_low_pwm;
905
		u8 min_brightness;	/* min_brightness/255 of max */
906
		u8 controller;		/* brightness controller number */
907
		enum intel_backlight_type type;
908 909
	} backlight;

910 911 912
	/* MIPI DSI */
	struct {
		u16 panel_id;
913 914
		struct mipi_config *config;
		struct mipi_pps_data *pps;
915 916
		u16 bl_ports;
		u16 cabc_ports;
917 918 919
		u8 seq_version;
		u32 size;
		u8 *data;
920
		const u8 *sequence[MIPI_SEQ_MAX];
921
		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
922
		enum drm_panel_orientation orientation;
923 924
	} dsi;

925 926 927
	int crt_ddc_pin;

	int child_dev_num;
928
	struct child_device_config *child_dev;
929 930

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
931
	struct sdvo_device_mapping sdvo_mappings[2];
932 933
};

934 935 936 937 938
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

939 940
struct intel_wm_level {
	bool enable;
941 942 943 944
	u32 pri_val;
	u32 spr_val;
	u32 cur_val;
	u32 fbc_val;
945 946
};

947
struct ilk_wm_values {
948 949 950 951
	u32 wm_pipe[3];
	u32 wm_lp[3];
	u32 wm_lp_spr[3];
	u32 wm_linetime[3];
952 953 954 955
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

956
struct g4x_pipe_wm {
957 958
	u16 plane[I915_MAX_PLANES];
	u16 fbc;
959
};
960

961
struct g4x_sr_wm {
962 963 964
	u16 plane;
	u16 cursor;
	u16 fbc;
965 966 967
};

struct vlv_wm_ddl_values {
968
	u8 plane[I915_MAX_PLANES];
969
};
970

971
struct vlv_wm_values {
972 973
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
974
	struct vlv_wm_ddl_values ddl[3];
975
	u8 level;
976
	bool cxsr;
977 978
};

979 980 981 982 983 984 985 986 987
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

988
struct skl_ddb_entry {
989
	u16 start, end;	/* in number of blocks, 'end' is exclusive */
990 991
};

992
static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
993
{
994
	return entry->end - entry->start;
995 996
}

997 998 999 1000 1001 1002 1003 1004 1005
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1006
struct skl_ddb_allocation {
1007
	u8 enabled_slices; /* GEN11 has configurable 2 slices */
1008 1009
};

1010
struct skl_ddb_values {
1011
	unsigned dirty_pipes;
1012
	struct skl_ddb_allocation ddb;
1013 1014 1015
};

struct skl_wm_level {
1016
	u16 min_ddb_alloc;
1017 1018
	u16 plane_res_b;
	u8 plane_res_l;
1019
	bool plane_en;
1020
	bool ignore_lines;
1021 1022
};

1023 1024 1025 1026
/* Stores plane specific WM parameters */
struct skl_wm_params {
	bool x_tiled, y_tiled;
	bool rc_surface;
1027
	bool is_planar;
1028 1029 1030 1031 1032
	u32 width;
	u8 cpp;
	u32 plane_pixel_rate;
	u32 y_min_scanlines;
	u32 plane_bytes_per_line;
1033 1034
	uint_fixed_16_16_t plane_blocks_per_line;
	uint_fixed_16_16_t y_tile_minimum;
1035 1036
	u32 linetime_us;
	u32 dbuf_block_size;
1037 1038
};

1039 1040 1041 1042
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
1043 1044 1045 1046 1047
	INTEL_PIPE_CRC_SOURCE_PLANE3,
	INTEL_PIPE_CRC_SOURCE_PLANE4,
	INTEL_PIPE_CRC_SOURCE_PLANE5,
	INTEL_PIPE_CRC_SOURCE_PLANE6,
	INTEL_PIPE_CRC_SOURCE_PLANE7,
1048
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1049 1050 1051 1052 1053
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1054
	INTEL_PIPE_CRC_SOURCE_AUTO,
1055 1056 1057
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1058
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1059
struct intel_pipe_crc {
1060
	spinlock_t lock;
T
Tomeu Vizoso 已提交
1061
	int skipped;
1062
	enum intel_pipe_crc_source source;
1063 1064
};

1065
struct i915_frontbuffer_tracking {
1066
	spinlock_t lock;
1067 1068 1069 1070 1071 1072 1073 1074 1075

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1076 1077
struct i915_virtual_gpu {
	bool active;
1078
	u32 caps;
1079 1080
};

1081 1082 1083 1084 1085 1086 1087
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1088 1089 1090 1091 1092
struct i915_oa_format {
	u32 format;
	int size;
};

1093 1094 1095 1096 1097
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111
struct i915_oa_config {
	char uuid[UUID_STRING_LEN + 1];
	int id;

	const struct i915_oa_reg *mux_regs;
	u32 mux_regs_len;
	const struct i915_oa_reg *b_counter_regs;
	u32 b_counter_regs_len;
	const struct i915_oa_reg *flex_regs;
	u32 flex_regs_len;

	struct attribute_group sysfs_metric;
	struct attribute *attrs[2];
	struct device_attribute sysfs_metric_id;
1112 1113

	atomic_t ref_count;
1114 1115
};

1116 1117
struct i915_perf_stream;

1118 1119 1120
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1121
struct i915_perf_stream_ops {
1122 1123 1124 1125
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1126 1127 1128
	 */
	void (*enable)(struct i915_perf_stream *stream);

1129 1130 1131 1132
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1133 1134 1135
	 */
	void (*disable)(struct i915_perf_stream *stream);

1136 1137
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1138 1139 1140 1141 1142 1143
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1144 1145 1146
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1147
	 * wait queue that would be passed to poll_wait().
1148 1149 1150
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1151 1152 1153 1154 1155 1156 1157
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1158
	 *
1159 1160
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1161
	 *
1162 1163
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1164
	 *
1165 1166 1167
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1168 1169 1170 1171 1172 1173
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1174 1175
	/**
	 * @destroy: Cleanup any stream specific resources.
1176 1177 1178 1179 1180 1181
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1182 1183 1184
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1185
struct i915_perf_stream {
1186 1187 1188
	/**
	 * @dev_priv: i915 drm device
	 */
1189 1190
	struct drm_i915_private *dev_priv;

1191 1192 1193
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1194 1195
	struct list_head link;

1196 1197 1198 1199
	/**
	 * @wakeref: As we keep the device awake while the perf stream is
	 * active, we track our runtime pm reference for later release.
	 */
1200 1201
	intel_wakeref_t wakeref;

1202 1203 1204 1205 1206
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1207
	u32 sample_flags;
1208 1209 1210 1211 1212 1213

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1214
	int sample_size;
1215

1216 1217 1218 1219
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1220
	struct i915_gem_context *ctx;
1221 1222 1223 1224 1225 1226

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1227 1228
	bool enabled;

1229 1230 1231 1232
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1233
	const struct i915_perf_stream_ops *ops;
1234 1235 1236 1237 1238

	/**
	 * @oa_config: The OA configuration used by the stream.
	 */
	struct i915_oa_config *oa_config;
1239 1240
};

1241 1242 1243
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1244
struct i915_oa_ops {
1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263
	/**
	 * @is_valid_b_counter_reg: Validates register's address for
	 * programming boolean counters for a particular platform.
	 */
	bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
				       u32 addr);

	/**
	 * @is_valid_mux_reg: Validates register's address for programming mux
	 * for a particular platform.
	 */
	bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

	/**
	 * @is_valid_flex_reg: Validates register's address for programming
	 * flex EU filtering for a particular platform.
	 */
	bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

1264 1265 1266 1267
	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
1268 1269
	 * disabling EU clock gating as required.
	 */
1270
	int (*enable_metric_set)(struct i915_perf_stream *stream);
1271 1272 1273 1274 1275

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
1276
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1277 1278 1279 1280

	/**
	 * @oa_enable: Enable periodic sampling
	 */
1281
	void (*oa_enable)(struct i915_perf_stream *stream);
1282 1283 1284 1285

	/**
	 * @oa_disable: Disable periodic sampling
	 */
1286
	void (*oa_disable)(struct i915_perf_stream *stream);
1287 1288 1289 1290 1291

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
1292 1293 1294 1295
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
1296 1297

	/**
1298
	 * @oa_hw_tail_read: read the OA tail pointer register
1299
	 *
1300 1301 1302
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
1303
	 */
1304
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1305 1306
};

1307
struct intel_cdclk_state {
1308
	unsigned int cdclk, vco, ref, bypass;
1309
	u8 voltage_level;
1310 1311
};

1312
struct drm_i915_private {
1313 1314
	struct drm_device drm;

1315
	const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1316
	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1317
	struct intel_driver_caps caps;
1318

1319 1320 1321
	/**
	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
	 * end of stolen which we can optionally use to create GEM objects
1322
	 * backed by stolen memory. Note that stolen_usable_size tells us
1323 1324 1325 1326
	 * exactly how much of this we are actually allowed to use, given that
	 * some portion of it is in fact reserved for use by hardware functions.
	 */
	struct resource dsm;
1327 1328 1329 1330
	/**
	 * Reseved portion of Data Stolen Memory
	 */
	struct resource dsm_reserved;
1331

1332 1333 1334 1335 1336 1337 1338 1339 1340
	/*
	 * Stolen memory is segmented in hardware with different portions
	 * offlimits to certain functions.
	 *
	 * The drm_mm is initialised to the total accessible range, as found
	 * from the PCI config. On Broadwell+, this is further restricted to
	 * avoid the first page! The upper end of stolen memory is reserved for
	 * hardware functions and similarly removed from the accessible range.
	 */
1341
	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
1342

1343
	struct intel_uncore uncore;
1344

1345 1346
	struct i915_virtual_gpu vgpu;

1347
	struct intel_gvt *gvt;
1348

1349 1350
	struct intel_wopcm wopcm;

1351
	struct intel_huc huc;
1352 1353
	struct intel_guc guc;

1354 1355
	struct intel_csr csr;

1356
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1357

1358 1359 1360 1361 1362
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
1363 1364
	 * Base address of where the gmbus and gpio blocks are located (either
	 * on PCH or on SoC for platforms without PCH).
1365
	 */
1366
	u32 gpio_mmio_base;
1367

1368
	/* MMIO base address for MIPI regs */
1369
	u32 mipi_mmio_base;
1370

1371
	u32 psr_mmio_base;
1372

1373
	u32 pps_mmio_base;
1374

1375 1376
	wait_queue_head_t gmbus_wait_queue;

1377
	struct pci_dev *bridge_dev;
1378
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1379 1380 1381 1382
	/* Context used internally to idle the GPU and setup initial state */
	struct i915_gem_context *kernel_context;
	/* Context only to be used for injecting preemption commands */
	struct i915_gem_context *preempt_context;
1383 1384
	struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
					    [MAX_ENGINE_INSTANCE + 1];
1385 1386 1387 1388 1389 1390

	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1391 1392
	bool display_irqs_enabled;

1393 1394 1395
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1396 1397
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1398
	struct pm_qos_request sb_qos;
1399 1400

	/** Cached value of IMR to avoid reads in updating the bitfield */
1401 1402 1403 1404
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1405
	u32 gt_irq_mask;
1406 1407
	u32 pm_imr;
	u32 pm_ier;
1408
	u32 pm_rps_events;
1409
	u32 pm_guc_events;
1410
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1411

1412
	struct i915_hotplug hotplug;
1413
	struct intel_fbc fbc;
1414
	struct i915_drrs drrs;
1415
	struct intel_opregion opregion;
1416
	struct intel_vbt_data vbt;
1417

1418 1419
	bool preserve_bios_swizzle;

1420 1421 1422
	/* overlay */
	struct intel_overlay *overlay;

1423
	/* backlight registers and fields in struct intel_panel */
1424
	struct mutex backlight_lock;
1425

1426 1427 1428
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1429 1430 1431
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1432
	unsigned int fsb_freq, mem_freq, is_ddr3;
1433
	unsigned int skl_preferred_vco_freq;
1434
	unsigned int max_cdclk_freq;
1435

M
Mika Kahola 已提交
1436
	unsigned int max_dotclk_freq;
1437
	unsigned int rawclk_freq;
1438
	unsigned int hpll_freq;
1439
	unsigned int fdi_pll_freq;
1440
	unsigned int czclk_freq;
1441

1442
	struct {
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
1457
		struct intel_cdclk_state hw;
1458 1459

		int force_min_cdclk;
1460
	} cdclk;
1461

1462 1463 1464 1465 1466 1467 1468
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1469 1470
	struct workqueue_struct *wq;

1471 1472 1473
	/* ordered wq for modesets */
	struct workqueue_struct *modeset_wq;

1474 1475 1476 1477 1478
	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1479
	unsigned short pch_id;
1480 1481 1482

	unsigned long quirks;

1483
	struct drm_atomic_state *modeset_restore_state;
1484
	struct drm_modeset_acquire_ctx reset_ctx;
1485

1486
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1487

1488
	struct i915_gem_mm mm;
1489 1490
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1491 1492 1493

	/* Kernel Modesetting */

1494 1495
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1496

1497 1498 1499 1500
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1501
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1502 1503
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1504
	const struct intel_dpll_mgr *dpll_mgr;
1505

1506 1507 1508 1509 1510 1511 1512
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1513
	unsigned int active_crtcs;
1514 1515
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
1516 1517
	/* minimum acceptable voltage level for each pipe */
	u8 min_voltage_level[I915_MAX_PIPES];
1518

1519
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1520

1521
	struct i915_wa_list gt_wa_list;
1522

1523 1524
	struct i915_frontbuffer_tracking fb_tracking;

1525 1526 1527 1528 1529
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

1530
	u16 orig_clock;
1531

1532
	bool mchbar_need_disable;
1533

1534 1535
	struct intel_l3_parity l3_parity;

1536 1537 1538 1539 1540
	/*
	 * edram size in MB.
	 * Cannot be determined by PCIID. You must always read a register.
	 */
	u32 edram_size_mb;
B
Ben Widawsky 已提交
1541

1542 1543
	/* gen6+ GT PM state */
	struct intel_gen6_power_mgmt gt_pm;
1544

1545 1546
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1547
	struct intel_ilk_power_mgmt ips;
1548

1549
	struct i915_power_domains power_domains;
1550

R
Rodrigo Vivi 已提交
1551
	struct i915_psr psr;
1552

1553
	struct i915_gpu_error gpu_error;
1554

1555 1556
	struct drm_i915_gem_object *vlv_pctx;

1557 1558
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1559
	struct work_struct fbdev_suspend_work;
1560 1561

	struct drm_property *broadcast_rgb_property;
1562
	struct drm_property *force_audio_property;
1563

I
Imre Deak 已提交
1564
	/* hda/i915 audio component */
1565
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1566
	bool audio_component_registered;
1567 1568 1569 1570 1571
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
1572
	int audio_power_refcount;
I
Imre Deak 已提交
1573

1574
	struct {
1575
		struct mutex mutex;
1576
		struct list_head list;
1577 1578
		struct llist_head free_list;
		struct work_struct free_work;
1579 1580 1581 1582 1583 1584 1585

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1586
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1587
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1588
		struct list_head hw_id_list;
1589
	} contexts;
1590

1591
	u32 fdi_rx_config;
1592

1593
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1594
	u32 chv_phy_control;
1595 1596 1597 1598 1599 1600
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1601
	u32 bxt_phy_grc;
1602

1603
	u32 suspend_count;
1604
	bool power_domains_suspended;
1605
	struct i915_suspend_saved_registers regfile;
1606
	struct vlv_s0ix_state vlv_s0ix_state;
1607

1608
	enum {
1609 1610 1611 1612 1613
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
1614

1615 1616 1617 1618 1619 1620 1621
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
1622
		u16 pri_latency[5];
1623
		/* sprite */
1624
		u16 spr_latency[5];
1625
		/* cursor */
1626
		u16 cur_latency[5];
1627 1628 1629 1630 1631
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
1632
		u16 skl_latency[8];
1633 1634

		/* current hardware state */
1635 1636
		union {
			struct ilk_wm_values hw;
1637
			struct skl_ddb_values skl_hw;
1638
			struct vlv_wm_values vlv;
1639
			struct g4x_wm_values g4x;
1640
		};
1641

1642
		u8 max_level;
1643 1644 1645 1646

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
1647
		 * crtc_state->wm.need_postvbl_update.
1648 1649
		 */
		struct mutex wm_mutex;
1650 1651 1652 1653 1654 1655 1656

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
1657 1658
	} wm;

1659 1660
	struct dram_info {
		bool valid;
1661
		bool is_16gb_dimm;
1662
		u8 num_channels;
1663
		u8 ranks;
1664
		u32 bandwidth_kbps;
1665
		bool symmetric_memory;
V
Ville Syrjälä 已提交
1666 1667 1668 1669 1670 1671 1672
		enum intel_dram_type {
			INTEL_DRAM_UNKNOWN,
			INTEL_DRAM_DDR3,
			INTEL_DRAM_DDR4,
			INTEL_DRAM_LPDDR3,
			INTEL_DRAM_LPDDR4
		} type;
1673 1674
	} dram_info;

1675
	struct intel_bw_info {
1676 1677 1678
		unsigned int deratedbw[3]; /* for each QGV point */
		u8 num_qgv_points;
		u8 num_planes;
1679 1680 1681 1682
	} max_bw[6];

	struct drm_private_obj bw_obj;

1683
	struct intel_runtime_pm runtime_pm;
1684

1685 1686
	struct {
		bool initialized;
1687

1688
		struct kobject *metrics_kobj;
1689
		struct ctl_table_header *sysctl_header;
1690

1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
		/*
		 * Lock associated with adding/modifying/removing OA configs
		 * in dev_priv->perf.metrics_idr.
		 */
		struct mutex metrics_lock;

		/*
		 * List of dynamic configurations, you need to hold
		 * dev_priv->perf.metrics_lock to access it.
		 */
		struct idr metrics_idr;

		/*
		 * Lock associated with anything below within this structure
		 * except exclusive_stream.
		 */
1707 1708
		struct mutex lock;
		struct list_head streams;
1709 1710

		struct {
1711 1712 1713 1714 1715 1716
			/*
			 * The stream currently using the OA unit. If accessed
			 * outside a syscall associated to its file
			 * descriptor, you need to hold
			 * dev_priv->drm.struct_mutex.
			 */
1717 1718
			struct i915_perf_stream *exclusive_stream;

1719
			struct intel_context *pinned_ctx;
1720
			u32 specific_ctx_id;
1721
			u32 specific_ctx_id_mask;
1722 1723 1724 1725 1726

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

1727 1728 1729 1730 1731 1732
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

1733 1734 1735
			bool periodic;
			int period_exponent;

1736
			struct i915_oa_config test_config;
1737 1738 1739 1740

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
1741
				u32 last_ctx_id;
1742 1743
				int format;
				int format_size;
1744

1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

1798 1799 1800 1801 1802 1803 1804 1805 1806 1807
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
1808 1809 1810
			} oa_buffer;

			u32 gen7_latched_oastatus1;
1811 1812 1813 1814 1815 1816 1817 1818 1819
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
1820 1821 1822

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
1823
		} oa;
1824 1825
	} perf;

1826
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1827
	struct intel_gt gt;
1828 1829

	struct {
1830 1831
		struct notifier_block pm_notifier;

1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
1848
		struct work_struct idle_work;
1849
	} gem;
1850

1851 1852 1853 1854 1855 1856 1857 1858
	/* For i945gm vblank irq vs. C3 workaround */
	struct {
		struct work_struct work;
		struct pm_qos_request pm_qos;
		u8 c3_disable_latency;
		u8 enabled;
	} i945gm_vblank;

1859 1860 1861
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
1862 1863
	bool ipc_enabled;

1864 1865
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1866

1867 1868 1869 1870 1871 1872
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

1873 1874
	struct i915_pmu pmu;

1875 1876 1877 1878 1879 1880
	struct i915_hdcp_comp_master *hdcp_master;
	bool hdcp_comp_added;

	/* Mutex to protect the above hdcp component related values. */
	struct mutex hdcp_comp_mutex;

1881 1882 1883 1884
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1885
};
L
Linus Torvalds 已提交
1886

1887 1888 1889 1890
struct dram_dimm_info {
	u8 size, width, ranks;
};

1891
struct dram_channel_info {
1892
	struct dram_dimm_info dimm_l, dimm_s;
1893
	u8 ranks;
1894
	bool is_16gb_dimm;
1895 1896
};

1897 1898
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
1899
	return container_of(dev, struct drm_i915_private, drm);
1900 1901
}

1902
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
1903
{
1904
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
1905 1906
}

1907 1908 1909 1910 1911
static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
{
	return container_of(wopcm, struct drm_i915_private, wopcm);
}

1912 1913 1914 1915 1916
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
1917 1918 1919 1920 1921
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

1922
/* Simple iterator over all initialised engines */
1923 1924 1925 1926 1927
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1928 1929

/* Iterator over subset of engines selected by mask */
1930
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
1931
	for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
1932 1933 1934
	     (tmp__) ? \
	     ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
	     0;)
1935

1936 1937 1938 1939 1940 1941 1942
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

1943
#define I915_GTT_OFFSET_NONE ((u32)-1)
1944

1945 1946
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1947
 * considered to be the frontbuffer for the given plane interface-wise. This
1948 1949 1950 1951 1952
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
1953
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1954 1955 1956 1957 1958
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
	BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
	BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
	BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
})
1959
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1960
	BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1961
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1962 1963
	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
		INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1964

1965
#define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
1966
#define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
1967
#define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
1968

1969
#define INTEL_GEN(dev_priv)	(INTEL_INFO(dev_priv)->gen)
1970
#define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
1971

1972
#define REVID_FOREVER		0xff
1973
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
1974

1975 1976 1977
#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
R
Rodrigo Vivi 已提交
1978
	GENMASK((e) - 1, (s) - 1))
1979

R
Rodrigo Vivi 已提交
1980
/* Returns true if Gen is in inclusive range [Start, End] */
1981
#define IS_GEN_RANGE(dev_priv, s, e) \
1982
	(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1983

1984 1985
#define IS_GEN(dev_priv, n) \
	(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1986
	 INTEL_INFO(dev_priv)->gen == (n))
1987

1988 1989 1990 1991 1992 1993 1994 1995
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info *info,
		      enum intel_platform p)
{
	const unsigned int pbits =
		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;

	/* Expand the platform_mask array if this fails. */
	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
		     pbits * ARRAY_SIZE(info->platform_mask));

	return p / pbits;
}

static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info *info,
		    enum intel_platform p)
{
	const unsigned int pbits =
		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;

	return p % pbits + INTEL_SUBPLATFORM_BITS;
}

static inline u32
intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
{
	const unsigned int pi = __platform_mask_index(info, p);

	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
}

static __always_inline bool
IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
{
	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(info, p);
	const unsigned int pb = __platform_mask_bit(info, p);

	BUILD_BUG_ON(!__builtin_constant_p(p));

	return info->platform_mask[pi] & BIT(pb);
}

static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private *i915,
	       enum intel_platform p, unsigned int s)
{
	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(info, p);
	const unsigned int pb = __platform_mask_bit(info, p);
	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
	const u32 mask = info->platform_mask[pi];

	BUILD_BUG_ON(!__builtin_constant_p(p));
	BUILD_BUG_ON(!__builtin_constant_p(s));
	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);

	/* Shift and test on the MSB position so sign flag can be used. */
	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
}
T
Tvrtko Ursulin 已提交
2057

2058 2059
#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)

T
Tvrtko Ursulin 已提交
2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
2072
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
T
Tvrtko Ursulin 已提交
2073 2074
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
2075 2076 2077
#define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
#define IS_IRONLAKE_M(dev_priv) \
	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
T
Tvrtko Ursulin 已提交
2078
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2079
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
2080
				 INTEL_INFO(dev_priv)->gt == 1)
T
Tvrtko Ursulin 已提交
2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2091
#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2092
#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2093 2094
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2095 2096 2097 2098
#define IS_BDW_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
#define IS_BDW_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2099
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
2100
				 INTEL_INFO(dev_priv)->gt == 3)
2101 2102
#define IS_HSW_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2103
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
2104
				 INTEL_INFO(dev_priv)->gt == 3)
2105
#define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
2106
				 INTEL_INFO(dev_priv)->gt == 1)
2107
/* ULX machines are also considered ULT. */
2108 2109 2110 2111 2112 2113 2114 2115 2116 2117
#define IS_HSW_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
#define IS_SKL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_SKL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_KBL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_KBL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2118
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2119
				 INTEL_INFO(dev_priv)->gt == 2)
2120
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2121
				 INTEL_INFO(dev_priv)->gt == 3)
2122
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2123
				 INTEL_INFO(dev_priv)->gt == 4)
2124
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2125
				 INTEL_INFO(dev_priv)->gt == 2)
2126
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2127
				 INTEL_INFO(dev_priv)->gt == 3)
2128 2129
#define IS_CFL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2130 2131
#define IS_CFL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2132
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
2133
				 INTEL_INFO(dev_priv)->gt == 2)
2134
#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
2135
				 INTEL_INFO(dev_priv)->gt == 3)
2136 2137 2138 2139
#define IS_CNL_WITH_PORT_F(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
#define IS_ICL_WITH_PORT_F(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2140

2141 2142 2143 2144 2145 2146
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2147 2148
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2149

2150 2151
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2152
#define BXT_REVID_A0		0x0
2153
#define BXT_REVID_A1		0x1
2154
#define BXT_REVID_B0		0x3
2155
#define BXT_REVID_B_LAST	0x8
2156
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2157

2158 2159
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2160

M
Mika Kuoppala 已提交
2161 2162
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2163 2164 2165
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2166

2167 2168
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2169

2170 2171 2172 2173 2174 2175
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2176 2177
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
2178
#define CNL_REVID_C0		0x2
2179 2180 2181 2182

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2183 2184 2185 2186 2187 2188 2189 2190 2191
#define ICL_REVID_A0		0x0
#define ICL_REVID_A2		0x1
#define ICL_REVID_B0		0x3
#define ICL_REVID_B2		0x4
#define ICL_REVID_C0		0x5

#define IS_ICL_REVID(p, since, until) \
	(IS_ICELAKE(p) && IS_REVID(p, since, until))

2192
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2193 2194
#define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2195

2196
#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2197

2198 2199 2200 2201
#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({		\
	unsigned int first__ = (first);					\
	unsigned int count__ = (count);					\
	(INTEL_INFO(dev_priv)->engine_mask &				\
2202
	 GENMASK(first__ + count__ - 1, first__)) >> first__;		\
2203 2204 2205 2206 2207 2208
})
#define VDBOX_MASK(dev_priv) \
	ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(dev_priv) \
	ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)

2209 2210
#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
2211
#define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
2212 2213
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2214

2215
#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
2216

2217
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2218
		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2219
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2220
		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2221
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2222
		(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2223 2224 2225

#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

2226
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2227 2228 2229 2230 2231
#define HAS_PPGTT(dev_priv) \
	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)

2232 2233
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
2234
	((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2235
})
2236

2237
#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)
2238
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2239
		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2240

2241
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2242
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2243

2244
/* WaRsDisableCoarsePowerGating:skl,cnl */
2245
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2246 2247
	(IS_CANNONLAKE(dev_priv) || \
	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2248

2249
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
R
Ramalingam C 已提交
2250 2251 2252
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
					IS_GEMINILAKE(dev_priv) || \
					IS_KABYLAKE(dev_priv))
2253

2254 2255 2256
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2257
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2258 2259
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2260 2261
#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
2262

2263
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
2264
#define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_fbc)
R
Rodrigo Vivi 已提交
2265
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2266

2267
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2268

2269
#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
2270

2271 2272 2273
#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
2274
#define HAS_TRANSCODER_EDP(dev_priv)	 (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2275

2276 2277
#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
2278
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
P
Paulo Zanoni 已提交
2279

2280 2281
#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)

2282
#define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->display.has_csr)
2283

2284 2285
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2286

2287
#define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
2288

2289 2290 2291 2292 2293
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2294
#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
2295 2296
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2297 2298 2299

/* For now, anything with a GuC has also HuC */
#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
2300
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2301

2302
/* Having a GuC is not the same as using a GuC */
2303 2304 2305
#define USES_GUC(dev_priv)		intel_uc_is_using_guc(dev_priv)
#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission(dev_priv)
#define USES_HUC(dev_priv)		intel_uc_is_using_huc(dev_priv)
2306

2307
#define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
2308

2309
#define INTEL_PCH_DEVICE_ID_MASK		0xff80
2310 2311 2312 2313 2314
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2315 2316
#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
2317 2318
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2319
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
2320
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
2321
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
2322
#define INTEL_PCH_CMP_DEVICE_ID_TYPE		0x0280
2323
#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
2324
#define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
2325
#define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
2326
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2327
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2328
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2329

2330
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2331
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2332
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
2333
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2334
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2335 2336
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2337
#define HAS_PCH_LPT_LP(dev_priv) \
2338 2339
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2340
#define HAS_PCH_LPT_H(dev_priv) \
2341 2342
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2343 2344 2345 2346
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2347

R
Rodrigo Vivi 已提交
2348
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2349

2350
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2351

2352
/* DPF == dynamic parity feature */
2353
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2354 2355
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2356

2357
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2358
#define GEN9_FREQ_SCALER 3
2359

2360 2361
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)

2362 2363
#include "i915_trace.h"

2364
static inline bool intel_vtd_active(void)
2365 2366
{
#ifdef CONFIG_INTEL_IOMMU
2367
	if (intel_iommu_gfx_mapped)
2368 2369 2370 2371 2372
		return true;
#endif
	return false;
}

2373 2374 2375 2376 2377
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

2378 2379 2380
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
2381
	return IS_BROXTON(dev_priv) && intel_vtd_active();
2382 2383
}

2384
/* i915_drv.c */
2385 2386 2387 2388 2389 2390 2391
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2392
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2393 2394
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2395 2396
#else
#define i915_compat_ioctl NULL
2397
#endif
2398 2399 2400 2401 2402
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2403

2404
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2405
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2406
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2407

2408 2409
u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);

2410 2411 2412 2413
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

2414
	if (unlikely(!i915_modparams.enable_hangcheck))
2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2427 2428
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2429
	return dev_priv->gvt;
2430 2431
}

2432
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2433
{
2434
	return dev_priv->vgpu.active;
2435
}
2436

2437
/* i915_gem.c */
2438 2439
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2440
void i915_gem_sanitize(struct drm_i915_private *i915);
2441 2442
int i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2443
int i915_gem_freeze(struct drm_i915_private *dev_priv);
2444 2445
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

2446 2447
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
2448 2449
	/*
	 * A single pass should suffice to release all the freed objects (along
2450 2451 2452 2453 2454
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
2455 2456
	while (atomic_read(&i915->mm.free_count)) {
		flush_work(&i915->mm.free_work);
2457
		rcu_barrier();
2458
	}
2459 2460
}

2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
2471
	 * than 3 passes to catch all _recursive_ RCU delayed work.
2472 2473
	 *
	 */
2474
	int pass = 3;
2475
	do {
2476
		flush_workqueue(i915->wq);
2477
		rcu_barrier();
2478
		i915_gem_drain_freed_objects(i915);
2479
	} while (--pass);
2480
	drain_workqueue(i915->wq);
2481 2482
}

C
Chris Wilson 已提交
2483
struct i915_vma * __must_check
2484 2485
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
2486
			 u64 size,
2487 2488
			 u64 alignment,
			 u64 flags);
2489

2490 2491 2492
int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
			   unsigned long flags);
#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
2493

2494 2495
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

2496 2497 2498 2499 2500 2501
static inline int __must_check
i915_mutex_lock_interruptible(struct drm_device *dev)
{
	return mutex_lock_interruptible(&dev->struct_mutex);
}

2502 2503 2504
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
2505
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2506
		      u32 handle, u64 *offset);
2507
int i915_gem_mmap_gtt_version(void);
2508 2509 2510 2511 2512

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2513
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2514

2515
static inline bool __i915_wedged(struct i915_gpu_error *error)
2516
{
2517
	return unlikely(test_bit(I915_WEDGED, &error->flags));
2518 2519
}

2520 2521 2522 2523 2524
static inline bool i915_reset_failed(struct drm_i915_private *i915)
{
	return __i915_wedged(&i915->gpu_error);
}

M
Mika Kuoppala 已提交
2525 2526
static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
2527
	return READ_ONCE(error->reset_count);
2528
}
2529

2530 2531 2532 2533 2534 2535
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
					  struct intel_engine_cs *engine)
{
	return READ_ONCE(error->reset_engine_count[engine->id]);
}

2536
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
2537
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
2538

2539
void i915_gem_init_mmio(struct drm_i915_private *i915);
2540 2541
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2542
void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
2543
void i915_gem_fini(struct drm_i915_private *dev_priv);
2544
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2545
			   unsigned int flags, long timeout);
2546
void i915_gem_suspend(struct drm_i915_private *dev_priv);
2547
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2548
void i915_gem_resume(struct drm_i915_private *dev_priv);
2549
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2550

2551
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2552
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2553

2554 2555 2556
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

2557 2558 2559 2560 2561 2562
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

2563 2564 2565 2566 2567 2568
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
	return idr_find(&file_priv->context_idr, id);
}

2569 2570 2571 2572 2573
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

2574 2575 2576 2577 2578
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
2579 2580 2581 2582

	return ctx;
}

2583 2584
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
2585 2586 2587 2588
int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
2589
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2590
			    struct intel_context *ce,
2591
			    u32 *reg_state);
2592

2593
/* i915_gem_evict.c */
2594
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2595
					  u64 min_size, u64 alignment,
2596
					  unsigned cache_level,
2597
					  u64 start, u64 end,
2598
					  unsigned flags);
2599 2600 2601
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
2602
int i915_gem_evict_vm(struct i915_address_space *vm);
2603

2604
/* i915_gem_stolen.c */
2605 2606 2607
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
2608 2609 2610 2611
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
2612 2613
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
2614
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
2615
void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
2616
struct drm_i915_gem_object *
2617 2618
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
			      resource_size_t size);
2619
struct drm_i915_gem_object *
2620
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
2621 2622 2623
					       resource_size_t stolen_offset,
					       resource_size_t gtt_offset,
					       resource_size_t size);
2624

2625 2626 2627
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2628
				phys_addr_t size);
2629

2630
/* i915_gem_shrinker.c */
2631
unsigned long i915_gem_shrink(struct drm_i915_private *i915,
2632
			      unsigned long target,
2633
			      unsigned long *nr_scanned,
2634
			      unsigned flags);
2635 2636 2637 2638 2639 2640
#define I915_SHRINK_UNBOUND	BIT(0)
#define I915_SHRINK_BOUND	BIT(1)
#define I915_SHRINK_ACTIVE	BIT(2)
#define I915_SHRINK_VMAPS	BIT(3)
#define I915_SHRINK_WRITEBACK	BIT(4)

2641 2642 2643
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_shrinker_register(struct drm_i915_private *i915);
void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
2644 2645
void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
				    struct mutex *mutex);
2646

2647
/* i915_gem_tiling.c */
2648
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2649
{
2650
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2651 2652

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2653
		i915_gem_object_is_tiled(obj);
2654 2655
}

2656 2657 2658 2659 2660
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

2661
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2662

2663
/* i915_cmd_parser.c */
2664
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2665
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2666 2667 2668 2669 2670 2671 2672
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
2673

2674 2675 2676
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
2677 2678
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
2679

2680
/* i915_suspend.c */
2681 2682
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
2683

B
Ben Widawsky 已提交
2684
/* i915_sysfs.c */
D
David Weinehall 已提交
2685 2686
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
2687

2688 2689 2690 2691
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
2692
	return (struct intel_device_info *)INTEL_INFO(dev_priv);
2693 2694
}

J
Jesse Barnes 已提交
2695
/* modesetting */
2696
extern void intel_modeset_init_hw(struct drm_device *dev);
2697
extern int intel_modeset_init(struct drm_device *dev);
J
Jesse Barnes 已提交
2698
extern void intel_modeset_cleanup(struct drm_device *dev);
2699 2700
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
2701
extern void intel_display_resume(struct drm_device *dev);
2702 2703
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
2704
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
2705

B
Ben Widawsky 已提交
2706 2707
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
2708

2709 2710
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
2711
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2712
					    struct intel_display_error_state *error);
2713

2714 2715
#define __I915_REG_OP(op__, dev_priv__, ...) \
	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2716

2717 2718
#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))
#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
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#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
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/* These are untraced mmio-accessors that are only valid to be used inside
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 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
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 * controlled.
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 *
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 * Think twice, and think again, before using these.
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 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
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 */
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#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
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/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
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void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

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/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

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/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

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static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

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static inline enum i915_map_type
i915_coherent_map_type(struct drm_i915_private *i915)
{
	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
}

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static inline void add_taint_for_CI(unsigned int taint)
{
	/*
	 * The system is "ok", just about surviving for the user, but
	 * CI results are now unreliable as the HW is very suspect.
	 * CI checks the taint state after every test and will reboot
	 * the machine if the kernel is tainted.
	 */
	add_taint(taint, LOCKDEP_STILL_OK);
}

L
Linus Torvalds 已提交
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#endif